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FMC TDC 1ns 5cha - Gateware
Commit 7bc6f27d authored by penacoba's avatar penacoba
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Simulation folder updated 


git-svn-id: http://svn.ohwr.org/fmc-tdc@63 85dfdc96-de2c-444c-878d-45b388be74a9
parent 7f3e7a0e
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hdl/spec/sim/.cxl.ncsim.version 0 → 100644
View file @ 7bc6f27d
TOOL: ncvhdl 08.20-s004
hdl/spec/sim/cds.lib
View file @ 7bc6f27d
include $CDS_INST_DIR/tools/inca/files/cds.lib
define worklib /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/worklib
DEFINE unimacro /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/unimacro
DEFINE unisim /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/unisim
DEFINE xilinxcorelib /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/xilinxcorelib
define worklib /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/worklib
DEFINE secureip /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/secureip
DEFINE unimacro /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/unimacro
DEFINE unisim /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/unisim
DEFINE xilinxcorelib /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/xilinxcorelib
hdl/spec/sim/data_vectors/acam_test_cmd0.vec
View file @ 7bc6f27d
......@@ -34,6 +34,9 @@ wait %d60000
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
-- Gonzalo: 3 writings outside of the BAR defined memory space to check that
-- the BFM model does not forward them to the Local bus
wr 0000000040000808 F 0001F04C
wait %d50
wr 0000000040000800 F 00021040
......@@ -41,6 +44,9 @@ wait %d50
wr 0000000040000800 F 00025000
wait %d50
-- Gonzalo: 5 reads inside Matthieu's core memory space to check that the core
-- does not forward them to the wishbone bus
rd 0000000000000000 F 0000A0A1
wait %d20
rd 0000000000000004 F 0000A0A2
......@@ -52,6 +58,8 @@ wait %d20
rd 0000000000000010 F 0000A0A5
wait %d60
-- Gonzalo: actual wr and rd for test
wr 0000000000080000 F 0000FC81
wait %d50
wr 000000000008002C F 00FF0000
......
hdl/spec/sim/data_vectors/atdc_test_cmd0.vec 0 → 100644
View file @ 7bc6f27d
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
---- Gonzalo: 3 writings outside of the BAR defined memory space to check that
---- the BFM model does not forward them to the Local bus
--wr 0000000040000808 F 0001F04C
--wait %d20
--wr 0000000040000800 F 00021040
--wait %d20
--wr 0000000040000800 F 00025000
--wait %d60
---- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
---- does not forward them to the wishbone bus
--rd 0000000000000000 F 0000A0A1
--wait %d20
--rd 0000000000000004 F 0000A0A2
--wait %d20
--rd 0000000000000008 F 0000A0A3
--wait %d60
-- Gonzalo: actual wr and rd on the application memory space for test
-- writing stuff on the TDC config
wr 0000000000080080 F 00000040
wait %d20
wr 0000000000080084 F 00000000
wait %d20
wr 0000000000080088 F 00000000
wait %d60
-- writing stuff for the ACAM config
wr 0000000000080000 F 01F0FC81
wait %d20
wr 0000000000080004 F 00000000
wait %d20
wr 0000000000080008 F 00000E02
wait %d60
-- loading the utc time
wr 00000000000800FC F 00000200
wait %d200
-- loading the acam config
wr 00000000000800FC F 00000004
wait %d200
-- reading back the acam config
wr 00000000000800FC F 00000008
wait %d200
-- activate acquisition
wr 00000000000800FC F 00000001
wait %d540000
-- read circular buffer wr pointer
rd 000000000008009C F 00000000
wait %d200
-- prepare and launch DMA transfer
wr 000000000000000C F 36EF8000
wait %d20
wr 0000000000000014 F 00000210
wait %d100
wr 0000000000000000 F 00000001
wait %d100
-- deactivate acquisition
wr 00000000000800FC F 00000002
wait %d200
-- read acam status
wr 00000000000800FC F 00000010
wait %d100
rd 0000000000080070 F 00000000
wait %d100
-- read acam ififo1
wr 00000000000800FC F 00000020
wait %d100
rd 0000000000080060 F 00000000
wait %d100
-- read acam ififo2
wr 00000000000800FC F 00000040
wait %d100
rd 0000000000080064 F 00000000
wait %d100
-- read acam start01 register
wr 00000000000800FC F 00000080
wait %d100
rd 0000000000080068 F 00000000
wait %d100
-- reset acam
wr 00000000000800FC F 00000100
wait %d200
--rd 0000000000080000 F 00001234
--wait %d20
--rd 0000000000080004 F 00005678
--wait %d20
--rd 0000000000080008 F 0000abcd
--wait %d20
--rd 000000000008000C F 0000ef90
--wait %d60
--
--wr 00000000000800FC F 00000001
--wait %d100
--wr 00000000000800FC F 00000002
--wait %d100
---- Gonzalo: registers inside Matthieu's core memory space are written with the
---- settings for DMA transfer
--
---- Start address on the carrier local memory
--wr 0000000000000008 F 00000000
--wait %d20
--
---- Start addresses on the PCI host memory
--wr 000000000000000C F 0000A0A4
--wait %d20
--wr 0000000000000010 F 0000A0A5
--wait %d20
--
---- Transfer length
--wr 0000000000000014 F 00000060
--wait %d20
--
---- Chain control
--wr 0000000000000020 F 00000000
--wait %d60
--
---- Start transfer through the Control register and check through the status register
--wr 0000000000000000 F 00000001
--wait %d100
--rd 0000000000000004 F 00000001
--wait %d100
--
--
hdl/spec/sim/data_vectors/memo_test_cmd0.vec 0 → 100644
View file @ 7bc6f27d
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
-- Gonzalo: 3 writings outside of the BAR defined memory space to check that
-- the BFM model does not forward them to the Local bus
wr 0000000040000808 F 0001F04C
wait %d20
wr 0000000040000800 F 00021040
wait %d20
wr 0000000040000800 F 00025000
wait %d60
-- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
-- does not forward them to the wishbone bus
rd 0000000000000000 F 0000A0A1
wait %d20
rd 0000000000000004 F 0000A0A2
wait %d20
rd 0000000000000008 F 0000A0A3
wait %d60
-- Gonzalo: actual wr and rd on the application memory space for test
wr 0000000000080000 F 00001234
wait %d20
wr 0000000000080004 F 00005678
wait %d20
wr 0000000000080008 F 0000abcd
wait %d20
wr 000000000008000C F 0000ef90
wait %d60
rd 0000000000080000 F 00001234
wait %d20
rd 0000000000080004 F 00005678
wait %d20
rd 0000000000080008 F 0000abcd
wait %d20
rd 000000000008000C F 0000ef90
wait %d60
wr 0000000000080100 F 00000001
wait %d100
wr 0000000000080100 F 00000002
wait %d100
-- Gonzalo: registers inside Matthieu's core memory space are written with the
-- settings for DMA transfer
-- Start address on the carrier local memory
wr 0000000000000008 F 00000000
wait %d20
-- Start addresses on the PCI host memory
wr 000000000000000C F 0000A0A4
wait %d20
wr 0000000000000010 F 0000A0A5
wait %d20
-- Transfer length
wr 0000000000000014 F 00000060
wait %d20
-- Chain control
wr 0000000000000020 F 00000000
wait %d60
-- Start transfer through the Control register and check through the status register
wr 0000000000000000 F 00000001
wait %d100
rd 0000000000000004 F 00000001
wait %d100
hdl/spec/sim/data_vectors/pulses.txt
View file @ 7bc6f27d
1100 us,5,505 ns
1300 us,1,5 us
6 us,2,505 ns
750 us,5,505 ns
1850 us,1,5 us
800 us,2,505 ns
162 ps,3,505 ns
840 us,4,505 ns
1400 ps,5,505 ns
500 us,4,505 ns
400 ps,1,505 ns
hdl/spec/sim/nclaunch.key
View file @ 7bc6f27d
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/sim/sim.tcl
View file @ 7bc6f27d
......@@ -27,6 +27,11 @@ ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work wor
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/data_engine.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/acam_timecontrol_interface.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/acam_databus_interface.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/mem_core/reg_mem_gen_v6_2.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/circular_buffer.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/reg_ctrl.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/data_engine.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/top_tdc.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/test_tdc_acam/top_test_acam.vhd
......
hdl/spec/sim/waves.tcl
View file @ 7bc6f27d
......@@ -4,22 +4,22 @@ probe -create -shm -waveform :dut:clk
probe -create -shm -waveform :dut:gnum_reset
probe -create -shm -waveform :dut:general_reset
probe -create -shm -waveform :dut:clks_rsts_mgment:pll_sclk_o
probe -create -shm -waveform :dut:clks_rsts_mgment:pll_sdi_o
probe -create -shm -waveform :dut:clks_rsts_mgment:pll_cs_o
probe -create -shm -waveform :dut:clks_rsts_mgment:bit_index
probe -create -shm -waveform :dut:clks_rsts_mgment:byte_index
#probe -create -shm -waveform :dut:clks_rsts_mgment:bit_being_sent
probe -create -shm -waveform :dut:clks_rsts_mgment:word_being_sent
probe -create -shm -waveform :dut:clks_rsts_mgment:pll_init_st
#probe -create -shm -waveform :dut:clks_rsts_mgment:nxt_pll_init_st
probe -create -shm -waveform :dut:clks_rsts_mgment:gral_incr
probe -create -shm -waveform :dut:clks_rsts_mgment:general_poreset:current_value
probe -create -shm -waveform :spec_led_green
probe -create -shm -waveform :spec_led_red
probe -create -shm -waveform :tdc_led_status
#probe -create -shm -waveform :dut:clks_rsts_mgment:pll_sclk_o
#probe -create -shm -waveform :dut:clks_rsts_mgment:pll_sdi_o
#probe -create -shm -waveform :dut:clks_rsts_mgment:pll_cs_o
#probe -create -shm -waveform :dut:clks_rsts_mgment:bit_index
#probe -create -shm -waveform :dut:clks_rsts_mgment:byte_index
##probe -create -shm -waveform :dut:clks_rsts_mgment:bit_being_sent
#probe -create -shm -waveform :dut:clks_rsts_mgment:word_being_sent
#probe -create -shm -waveform :dut:clks_rsts_mgment:pll_init_st
##probe -create -shm -waveform :dut:clks_rsts_mgment:nxt_pll_init_st
#probe -create -shm -waveform :dut:clks_rsts_mgment:gral_incr
#probe -create -shm -waveform :dut:clks_rsts_mgment:general_poreset:current_value
#probe -create -shm -waveform :spec_led_green
#probe -create -shm -waveform :spec_led_red
#probe -create -shm -waveform :tdc_led_status
#probe -create -shm -waveform :dut:tdc_led_count_done
#probe -create -shm -waveform :dut:spec_led_count_done
......@@ -31,29 +31,45 @@ probe -create -shm -waveform :tdc_led_status
#probe -create -shm -waveform :dut:one_second_block:one_hz_p_pre
#probe -create -shm -waveform :dut:one_second_block:one_hz_p_post
probe -create -shm -waveform :dut:one_second_block:one_hz_p_o
probe -create -shm -waveform :dut:int_flag_i
probe -create -shm -waveform :dut:acam_fall_intflag_p
#probe -create -shm -waveform :dut:start_retrigger_block:roll_over_reset
#probe -create -shm -waveform :dut:start_retrigger_block:add_roll_over
probe -create -shm -waveform :dut:start_retrigger_block:roll_over_value
#probe -create -shm -waveform :dut:start_retrigger_block:retrig_nb_reset
probe -create -shm -waveform :dut:start_retrigger_block:current_retrig_nb
#probe -create -shm -waveform :dut:start_retrigger_block:retrig_period_reset
probe -create -shm -waveform :dut:start_retrigger_block:retrig_p
probe -create -shm -waveform :dut:start_retrigger_block:current_cycles
probe -create -shm -waveform :dut:start_retrigger_block:clk_cycles_offset
probe -create -shm -waveform :dut:start_retrigger_block:retrig_nb_offset
probe -create -shm -waveform :dut:start_trig
probe -create -shm -waveform :dut:acam_timing_block:start_trig_edge
probe -create -shm -waveform :dut:acam_timing_block:waitingfor_refclk
probe -create -shm -waveform :dut:acam_timing_block:window_delay
#probe -create -shm -waveform :dut:acam_timing_block:waitingfor_refclk
probe -create -shm -waveform :dut:acam_timing_block:refclk_edge
probe -create -shm -waveform :dut:acam_timing_block:window_prepulse
probe -create -shm -waveform :dut:acam_timing_block:counter_reset
probe -create -shm -waveform :dut:acam_timing_block:window_active
probe -create -shm -waveform :dut:acam_timing_block:counter_value
probe -create -shm -waveform :start_dis_o
#probe -create -shm -waveform :dut:acam_timing_block:start_trig_received
#probe -create -shm -waveform :dut:acam_timing_block:counter_reset
#probe -create -shm -waveform :dut:acam_timing_block:window_active
#probe -create -shm -waveform :dut:acam_timing_block:counter_value
#probe -create -shm -waveform :start_dis_o
probe -create -shm -waveform :start_from_fpga_o
#probe -create -shm -waveform :stop_dis_o
probe -create -shm -waveform :acam:timing_block:start01
probe -create -shm -waveform :acam:timing_block:start_retrig_p
probe -create -shm -waveform :acam:timing_block:start_retrig_nb
#probe -create -shm -waveform :acam:timing_block:start01
#probe -create -shm -waveform :acam:timing_block:start_retrig_p
#probe -create -shm -waveform :acam:timing_block:start_retrig_nb
probe -create -shm -waveform :dut:acam_timing_block:int_flag_i
probe -create -shm -waveform :dut:start_retrigger_block:acam_fall_intflag_p_i
probe -create -shm -waveform :dut:start_retrigger_block:acam_rise_intflag_p_i
probe -create -shm -waveform :dut:start_retrigger_block:acam_halfcounter_gone
probe -create -shm -waveform :dut:start_retrigger_block:add_offset
probe -create -shm -waveform :dut:start_retrigger_block:start_nb_offset_o
#probe -create -shm -waveform :dut:acam_timing_block:int_flag_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_fall_intflag_p_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_rise_intflag_p_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_halfcounter_gone
#probe -create -shm -waveform :dut:start_retrigger_block:add_offset
#probe -create -shm -waveform :dut:start_retrigger_block:start_nb_offset_o
probe -create -shm -waveform :tstop1
probe -create -shm -waveform :tstop2
......@@ -61,6 +77,10 @@ probe -create -shm -waveform :tstop3
probe -create -shm -waveform :tstop4
probe -create -shm -waveform :tstop5
probe -create -shm -waveform :dut:data_formatting_block:local_utc
probe -create -shm -waveform :dut:data_formatting_block:coarse_time
probe -create -shm -waveform :dut:data_formatting_block:fine_time
#probe -create -shm -waveform :RSTINn
#probe -create -shm -waveform :RSTOUT18n
#probe -create -shm -waveform :RSTOUT33n
......@@ -73,46 +93,57 @@ probe -create -shm -waveform :P2L_DATA
#probe -create -shm -waveform :P2L_DATA_32
probe -create -shm -waveform :P2L_DFRAME
probe -create -shm -waveform :P2L_VALID
probe -create -shm -waveform :P2L_RDY
probe -create -shm -waveform :P_WR_REQ
probe -create -shm -waveform :P_WR_RDY
#probe -create -shm -waveform :P2L_RDY
#probe -create -shm -waveform :P_WR_REQ
#probe -create -shm -waveform :P_WR_RDY
probe -create -shm -waveform :RX_ERROR
probe -create -shm -waveform :VC_RDY
#probe -create -shm -waveform :VC_RDY
probe -create -shm -waveform :L2P_CLKp
#probe -create -shm -waveform :L2P_CLKn
probe -create -shm -waveform :L2P_DATA
#probe -create -shm -waveform :L2P_DATA_32
probe -create -shm -waveform :L2P_DFRAME
probe -create -shm -waveform :L2P_VALID
probe -create -shm -waveform :L2P_EDB
probe -create -shm -waveform :L2P_RDY
probe -create -shm -waveform :L_WR_RDY
probe -create -shm -waveform :P_RD_D_RDY
#probe -create -shm -waveform :L2P_EDB
#probe -create -shm -waveform :L2P_RDY
#probe -create -shm -waveform :L_WR_RDY
#probe -create -shm -waveform :P_RD_D_RDY
probe -create -shm -waveform :TX_ERROR
#probe -create -shm -waveform :GPIO
#probe -create -shm -waveform :dut:acm_adr
#probe -create -shm -waveform :dut:acm_cyc
#probe -create -shm -waveform :dut:acm_dat_w
#probe -create -shm -waveform :dut:acm_stb
#probe -create -shm -waveform :dut:acm_we
#probe -create -shm -waveform :dut:acm_ack
#probe -create -shm -waveform :dut:acm_dat_r
probe -create -shm -waveform :dut:clk
probe -create -shm -waveform :dut:csr_clk
probe -create -shm -waveform :dut:csr_cyc
probe -create -shm -waveform :dut:csr_sel
probe -create -shm -waveform :dut:csr_adr
probe -create -shm -waveform :dut:csr_dat_r
probe -create -shm -waveform :dut:csr_dat_w
probe -create -shm -waveform :dut:csr_cyc
probe -create -shm -waveform :dut:csr_we
probe -create -shm -waveform :dut:csr_stb
probe -create -shm -waveform :dut:csr_ack
probe -create -shm -waveform :dut:csr_we
probe -create -shm -waveform :dut:csr_dat_r
probe -create -shm -waveform :dut:csr_dat_w
#probe -create -shm -waveform :dut:csr_sel
probe -create -shm -waveform :dut:acam_data_block:acam_data_st
probe -create -shm -waveform :dut:acam_data_block:nxt_acam_data_st
probe -create -shm -waveform :dut:acam_config
probe -create -shm -waveform :dut:acam_config_rdbk
#probe -create -shm -waveform :dut:reg_control_block:control_register
probe -create -shm -waveform :dut:activate_acq
probe -create -shm -waveform :dut:deactivate_acq
probe -create -shm -waveform :dut:load_acam_config
probe -create -shm -waveform :dut:read_acam_config
probe -create -shm -waveform :dut:read_acam_status
probe -create -shm -waveform :dut:reset_acam
probe -create -shm -waveform :dut:data_engine_block:engine_st
probe -create -shm -waveform :dut:acm_adr
probe -create -shm -waveform :dut:acm_cyc
probe -create -shm -waveform :dut:acm_dat_w
probe -create -shm -waveform :dut:acm_stb
probe -create -shm -waveform :dut:acm_we
probe -create -shm -waveform :dut:acm_ack
probe -create -shm -waveform :dut:acm_dat_r
#probe -create -shm -waveform :dut:acam_data_block:acam_data_st
#probe -create -shm -waveform :dut:acam_data_block:nxt_acam_data_st
probe -create -shm -waveform :dut:ef1_i
probe -create -shm -waveform :dut:ef2_i
......@@ -123,10 +154,62 @@ probe -create -shm -waveform :dut:address_o
probe -create -shm -waveform :dut:cs_n_o
probe -create -shm -waveform :dut:oe_n_o
probe -create -shm -waveform :dut:rd_n_o
waveform format -using "Waveform 1" ":dut:rd_n_o" -color "red"
probe -create -shm -waveform :dut:wr_n_o
waveform format -using "Waveform 1" ":dut:rd_n_o" -color "red"
probe -create -shm -waveform :dut:acam_data_block:acam_data_st
#probe -create -shm -waveform :dut:acam_data_block:wr_extend
#probe -create -shm -waveform :dut:acam_data_block:wr_remove
#probe -create -shm -waveform :dut:acam_data_block:wr
waveform format -using "Waveform 1" ":dut:wr_n_o" -color "magenta"
probe -create -shm -waveform :dut:acam_timestamp1
probe -create -shm -waveform :dut:acam_timestamp1_valid
probe -create -shm -waveform :dut:acam_timestamp2
probe -create -shm -waveform :dut:acam_timestamp2_valid
probe -create -shm -waveform :dut:data_formatting_block:metadata
probe -create -shm -waveform :dut:data_formatting_block:local_utc
probe -create -shm -waveform :dut:data_formatting_block:coarse_time
probe -create -shm -waveform :dut:data_formatting_block:fine_time
probe -create -shm -waveform :dut:data_formatting_block:wr_pointer
probe -create -shm -waveform :dut:wr_pointer
probe -create -shm -waveform :dut:mem_class_adr
probe -create -shm -waveform :dut:mem_class_cyc
probe -create -shm -waveform :dut:mem_class_we
probe -create -shm -waveform :dut:mem_class_stb
probe -create -shm -waveform :dut:mem_class_ack
probe -create -shm -waveform :dut:mem_class_dat_r
probe -create -shm -waveform :dut:mem_class_dat_w
probe -create -shm -waveform :dut:circular_buffer_block:class_adr
probe -create -shm -waveform :dut:circular_buffer_block:class_data_wr
probe -create -shm -waveform :dut:circular_buffer_block:class_data_rd
probe -create -shm -waveform :dut:circular_buffer_block:class_we
probe -create -shm -waveform :dut:circular_buffer_block:class_en
probe -create -shm -waveform :dut:circular_buffer_block:wb_pipelined_st
probe -create -shm -waveform :dut:circular_buffer_block:pipe_adr
probe -create -shm -waveform :dut:circular_buffer_block:pipe_data_rd
probe -create -shm -waveform :dut:circular_buffer_block:pipe_we
probe -create -shm -waveform :dut:circular_buffer_block:pipe_en
probe -create -shm -waveform :dut:dma_clk
probe -create -shm -waveform :dut:dma_adr
probe -create -shm -waveform :dut:dma_cyc
probe -create -shm -waveform :dut:dma_we
probe -create -shm -waveform :dut:dma_stb
probe -create -shm -waveform :dut:dma_ack
probe -create -shm -waveform :dut:dma_dat_r
probe -create -shm -waveform :dut:dma_dat_w
#probe -create -shm -waveform :dut:dma_sel
probe -create -shm -waveform :dut:gnum_interface_block:cmp_dma_controller:dma_ctrl_current_state
#probe -create -shm -waveform :acam:data_block:interface_fifo1:wr_pointer
#probe -create -shm -waveform :acam:data_block:interface_fifo1:rd_pointer
#probe -create -shm -waveform :acam:data_block:interface_fifo1:level
#probe -create -shm -waveform :acam:data_block:wr_falling_time
#probe -create -shm -waveform :acam:data_block:wr_rising_time
......@@ -183,4 +266,5 @@ waveform format -using "Waveform 1" ":dut:wr_n_o" -color "magenta"
#set intovf_severity_level warning
run 2 ms
#run 1400 us
run 5 ms
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