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FMC TDC 1ns 5cha - Gateware
Commit 7f103f41 authored by egousiou's avatar egousiou
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small change on TDC LEDs behavior (to include termination enable) 

+code commenting

git-svn-id: http://svn.ohwr.org/fmc-tdc@176 85dfdc96-de2c-444c-878d-45b388be74a9
parent 2aeccb02
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hdl/rtl/clks_rsts_manager.vhd
View file @ 7f103f41
......@@ -110,7 +110,7 @@ entity clks_rsts_manager is
send_dac_word_p_i : in std_logic; -- pulse upon PCIe/VME request for a DAC reconfiguration
dac_word_i : in std_logic_vector(23 downto 0); -- DAC Vout = Vref (dac_word/65536)
-- Signals from the white rabbit unit for the reconfiguration of the DAC
-- Signals from the White Rabbit unit for the reconfiguration of the DAC
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
......
hdl/rtl/data_engine.vhd
View file @ 7f103f41
......@@ -43,7 +43,10 @@
-- Last changes |
-- 06/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 04/2014 v1 EG added state RD_START01 |
-- 04/2014 v1 EG added states for reading the RD_START01 (currently though the start01 |
-- is not essential absolute timestamp calculations). added wait state |
-- before starting receiving timestamps, to ensure that the start pulse has|
-- been sent and the ACAM IRflag has toggled once |
-- |
---------------------------------------------------------------------------------------------------
......@@ -145,7 +148,8 @@ end data_engine;
architecture rtl of data_engine is
type engine_state_ty is (ACTIVE, INACTIVE, GET_STAMP1, GET_STAMP2, WR_CONFIG, RDBK_CONFIG,
RD_STATUS, RD_IFIFO1, RD_IFIFO2, RD_START01, WR_RESET, WAIT_FOR_START01, WAIT_START_FROM_FPGA, WAIT_UTC);
RD_STATUS, RD_IFIFO1, RD_IFIFO2, RD_START01, WR_RESET,
WAIT_FOR_START01, WAIT_START_FROM_FPGA, WAIT_UTC);
signal engine_st, nxt_engine_st : engine_state_ty;
signal acam_cyc, acam_stb, acam_we : std_logic;
......@@ -247,7 +251,7 @@ begin
-- ACTIVE, GET_STAMP1, GET_STAMP2: intensive acquisition of timestamps from ACAM.
-- ACAM can receive and tag pulses with an overall rate up to 31.25 MHz;
-- therefore locally, running with a 125 MHz clk, in order to be able to receive timestamps
-- as fast as they arrive, it is needed to use up to 4 clk cycles to retreive each of them.
-- as fast as they arrive, it is needed to use up to 4 clk cycles to retrieve each of them.
-- Timestamps are received as soon as the ef1, ef2 flags are at zero (indicating that the
-- iFIFOs are not empty!). In order to avoid metastabilities locally, the ef signals are
-- synchronized using a set of two registers.
......@@ -268,7 +272,7 @@ begin
-- = 16 ns after an rdn falling edge the ef_synch1 should be stable.
--
-- Using the ef_synch1 signal instead of the ef_synch2 makes it possible to realise
-- timestamps' aquisitions from ACAM in just 4 clk cycles.
-- timestamps' acquisitions from ACAM in just 4 clk cycles.
-- clk --|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
-- ef ------|_______________________________________________________|--------------
-- ef_meta -----------|_____________________________________________________|-----------
......@@ -304,7 +308,7 @@ begin
when WAIT_FOR_START01 => -- wait for some time until the acam Start01 is available
when WAIT_FOR_START01 => -- wait for some time until the ACAM Start01 is available
-----------------------------------------------
acam_cyc <= '0';
acam_stb <= '0';
......@@ -321,7 +325,7 @@ begin
when RD_START01 => -- read now the acam Start01
when RD_START01 => -- read now the ACAM Start01
-----------------------------------------------
acam_cyc <= '1';
acam_stb <= '1';
......@@ -337,8 +341,8 @@ begin
end if;
when WAIT_UTC => -- wait until the next utc comes; now the offsets of the start_retrig_ctrl unit are defined
-- the acam is disabled during this period
when WAIT_UTC => -- wait until the next UTC comes; now the offsets of the start_retrig_ctrl unit are defined
-- the ACAM is disabled during this period
-----------------------------------------------
acam_cyc <= '0';
acam_stb <= '0';
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 7f103f41
......@@ -410,6 +410,7 @@ begin
---------------------------------------------------------------------------------------------------
-- WHITE RABBIT STUFF --
-- only synthesized if g_with_wrabbit_core is TRUE --
---------------------------------------------------------------------------------------------------
cmp_wrabbit_synch: wrabbit_sync
generic map
......
hdl/rtl/leds_manager.vhd
View file @ 7f103f41
......@@ -18,15 +18,35 @@
-- | | |
-- | O O | 1, 2 |
-- | O O | 3, 4 |
-- | O O | 5, 6 |
-- | O O | 5, STA |
-- |______| |
-- |
-- TDC LED 1 orange: division of the 125 MHz clock; one hz pulses |
-- TDC LED 2 orange: Channel 1 termination enable |
-- TDC LED 3 orange: Channel 2 termination enable |
-- TDC LED 4 orange: Channel 3 termination enable |
-- TDC LED 5 orange: Channel 4 termination enable |
-- TDC LED 6 orange: Channel 5 termination enable |
-- TDC LED 1 orange :blink upon timestamp registration for Channel 1; |
-- if the input termination for Channel 1 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 1 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED 2 orange: blink upon timestamp registration for Channel 2; |
-- if the input termination for Channel 2 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 2 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED 3 orange: blink upon timestamp registration for Channel 2; |
-- if the input termination for Channel 3 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 3 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED 4 orange: blink upon timestamp registration for Channel 4; |
-- if the input termination for Channel 4 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 4 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED 5 orange: blink upon timestamp registration for Channel 5; |
-- if the input termination for Channel 5 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 5 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED STA orange:division of the 125 MHz clock; one hz pulses |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Date 05/2012 |
......@@ -88,8 +108,8 @@ entity leds_manager is
-- activation comes through dedicated reg c_ACAM_INPUTS_EN_ADR
-- Signal for debugging
acam_channel_i : in std_logic_vector(5 downto 0); -- for debugging, currently not used
tstamp_wr_p_i : in std_logic;
acam_channel_i : in std_logic_vector(5 downto 0); -- identification of the channel for which a timestamp has arrived
tstamp_wr_p_i : in std_logic; -- pulse upon the writing of the timestamp in the circular buffer
-- OUTPUTS
......@@ -159,11 +179,31 @@ begin
led_1to5_outputs: process (clk_i)
begin
if rising_edge (clk_i) then
tdc_led_trig1_o <= blink_led1; --acam_inputs_en_i(0) and blink_led1;
tdc_led_trig2_o <= blink_led2; --acam_inputs_en_i(1) and blink_led2;
tdc_led_trig3_o <= blink_led3; --acam_inputs_en_i(2) and blink_led3;
tdc_led_trig4_o <= blink_led4; --acam_inputs_en_i(3) and blink_led4;
tdc_led_trig5_o <= blink_led5; --acam_inputs_en_i(4) and blink_led5;
if acam_inputs_en_i(0) = '1' then
tdc_led_trig1_o <= blink_led1;
else
tdc_led_trig1_o <= not blink_led1;
end if;
if acam_inputs_en_i(1) = '1' then
tdc_led_trig2_o <= blink_led2;
else
tdc_led_trig2_o <= not blink_led2;
end if;
if acam_inputs_en_i(2) = '1' then
tdc_led_trig3_o <= blink_led3;
else
tdc_led_trig3_o <= not blink_led3;
end if;
if acam_inputs_en_i(3) = '1' then
tdc_led_trig4_o <= blink_led4;
else
tdc_led_trig4_o <= not blink_led4;
end if;
if acam_inputs_en_i(4) = '1' then
tdc_led_trig5_o <= blink_led5;
else
tdc_led_trig5_o <= not blink_led5;
end if;
end if;
end process;
......
hdl/syn/spec/no_wrabbit/spec_tdc.par
View file @ 7f103f41
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Tue Jun 17 19:39:36 2014
PCBE13136:: Wed Jun 18 10:50:02 2014
par -w -intstyle ise -ol high -xe c -mt off spec_tdc_map.ncd spec_tdc.ncd
spec_tdc.pcf
......@@ -40,7 +40,7 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,877 out of 27,288 14%
Number of Slice LUTs: 3,871 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
......@@ -53,18 +53,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 94
Number with same-slice register load: 61
Number with same-slice carry load: 33
Number used exclusively as route-thrus: 88
Number with same-slice register load: 54
Number with same-slice carry load: 34
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,513 out of 6,822 22%
Number of occupied Slices: 1,514 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,843
Number with an unused Flip Flop: 1,551 out of 4,843 32%
Number with an unused LUT: 966 out of 4,843 19%
Number of fully used LUT-FF pairs: 2,326 out of 4,843 48%
Number of LUT Flip Flop pairs used: 4,830
Number with an unused Flip Flop: 1,533 out of 4,830 31%
Number with an unused LUT: 959 out of 4,830 19%
Number of fully used LUT-FF pairs: 2,338 out of 4,830 48%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -76,7 +76,7 @@ Slice Logic Distribution:
IO Utilization:
Number of bonded IOBs: 134 out of 296 45%
Number of LOCed IOBs: 133 out of 134 99%
Number of LOCed IOBs: 134 out of 134 100%
IOB Flip Flops: 55
Specific Feature Utilization:
......@@ -123,8 +123,8 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 14 secs
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -134,31 +134,31 @@ WARNING:Par:288 - The signal pll_sdo_i_IBUF has no load. PAR will not attempt t
Starting Router
Phase 1 : 24033 unrouted; REAL time: 16 secs
Phase 1 : 24030 unrouted; REAL time: 11 secs
Phase 2 : 20691 unrouted; REAL time: 19 secs
Phase 2 : 20693 unrouted; REAL time: 13 secs
Phase 3 : 8553 unrouted; REAL time: 33 secs
Phase 3 : 8930 unrouted; REAL time: 22 secs
Phase 4 : 8565 unrouted; (Setup:0, Hold:1951, Component Switching Limit:0) REAL time: 38 secs
Phase 4 : 8938 unrouted; (Setup:0, Hold:2351, Component Switching Limit:0) REAL time: 25 secs
Updating file: spec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:1951, Component Switching Limit:0) REAL time: 57 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:2249, Component Switching Limit:0) REAL time: 42 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1951, Component Switching Limit:0) REAL time: 57 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:2249, Component Switching Limit:0) REAL time: 42 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1951, Component Switching Limit:0) REAL time: 57 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:2249, Component Switching Limit:0) REAL time: 42 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1951, Component Switching Limit:0) REAL time: 57 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:2249, Component Switching Limit:0) REAL time: 42 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:1951, Component Switching Limit:0) REAL time: 58 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:2249, Component Switching Limit:0) REAL time: 42 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 58 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 43 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins
Total REAL time to Router completion: 1 mins
Total CPU time to Router completion: 47 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 44 secs
Total REAL time to Router completion: 44 secs
Total CPU time to Router completion: 45 secs
Partition Implementation Status
-------------------------------
......@@ -176,13 +176,13 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_125m | BUFGMUX_X3Y7| No | 919 | 0.551 | 1.762 |
| clk_125m | BUFGMUX_X3Y7| No | 914 | 0.551 | 1.762 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X3Y13| No | 237 | 0.518 | 1.729 |
| clk | BUFGMUX_X3Y13| No | 236 | 0.518 | 1.729 |
+---------------------+--------------+------+------+------------+-------------+
|clk_20m_vcxo_buf_BUF | | | | | |
| G | BUFGMUX_X2Y3| No | 25 | 0.526 | 1.737 |
| G | BUFGMUX_X2Y3| No | 26 | 0.518 | 1.737 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -190,7 +190,7 @@ Generating Clock Report
|cmp_tdc_mezz/cmp_tdc | | | | | |
|_core/data_engine_bl | | | | | |
|ock/engine_st[3]_PWR | | | | | |
| _227_o_Mux_41_o | Local| | 2 | 0.006 | 0.474 |
| _227_o_Mux_41_o | Local| | 2 | 0.000 | 0.469 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -212,11 +212,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.032ns| 7.968ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.297ns| | 0| 0
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.036ns| 7.964ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.226ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.080ns| 4.920ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.042ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.134ns| 4.866ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.088ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
......@@ -246,7 +246,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_ | MINPERIOD | 4.876ns| 3.124ns| 0| 0
clk_125m_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | SETUP | 45.274ns| 4.726ns| 0| 0
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | SETUP | 43.570ns| 6.430ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | HOLD | 0.369ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
......@@ -288,12 +288,12 @@ Derived Constraints for TS_p2l_clk_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 4.920ns| 0| 0| 0| 5842|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.920ns| 0| 0| 0| 5842|
|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 4.866ns| 0| 0| 0| 5842|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.866ns| 0| 0| 0| 5842|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.920ns| N/A| 0| 0| 5842| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.866ns| N/A| 0| 0| 5842| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -311,10 +311,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 5 secs
Total CPU time to PAR completion: 50 secs
Total REAL time to PAR completion: 46 secs
Total CPU time to PAR completion: 47 secs
Peak Memory Usage: 331 MB
Peak Memory Usage: 334 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/syn/spec/no_wrabbit/spec_tdc.twr
View file @ 7f103f41
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/no_wrabbit/spec_tdc_map.map
View file @ 7f103f41
......@@ -10,7 +10,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 19:36:47 2014
Mapped Date : Wed Jun 18 10:48:16 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
......@@ -25,60 +25,56 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 21 secs
Total REAL time at the beginning of Placer: 16 secs
Total CPU time at the beginning of Placer: 16 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:2600903f) REAL time: 23 secs
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 18 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 134 IOs, 133 are locked
and 1 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:2600903f) REAL time: 24 secs
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 19 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:2600903f) REAL time: 24 secs
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 19 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:ec6e8cf2) REAL time: 56 secs
(Checksum:46e77852) REAL time: 49 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:ec6e8cf2) REAL time: 56 secs
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 49 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:ec6e8cf2) REAL time: 56 secs
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 49 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:1cc69456) REAL time: 57 secs
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 49 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:1cc69456) REAL time: 57 secs
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 50 secs
Phase 9.8 Global Placement
.........................
.......................................................
..............................................................
.............................
......................................................................................................................
....................................
...........................
Phase 9.8 Global Placement (Checksum:a68d4d0b) REAL time: 1 mins 35 secs
Phase 9.8 Global Placement (Checksum:986ae115) REAL time: 1 mins 18 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:a68d4d0b) REAL time: 1 mins 35 secs
Phase 10.5 Local Placement Optimization (Checksum:986ae115) REAL time: 1 mins 18 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:53438eda) REAL time: 1 mins 54 secs
Phase 11.18 Placement Optimization (Checksum:49eeddee) REAL time: 1 mins 33 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:53438eda) REAL time: 1 mins 54 secs
Phase 12.5 Local Placement Optimization (Checksum:49eeddee) REAL time: 1 mins 33 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:101dbd96) REAL time: 1 mins 55 secs
Phase 13.34 Placement Validation (Checksum:8fcb33fb) REAL time: 1 mins 33 secs
Total REAL time to Placer completion: 2 mins 10 secs
Total CPU time to Placer completion: 1 mins 45 secs
Total REAL time to Placer completion: 1 mins 40 secs
Total CPU time to Placer completion: 1 mins 40 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -98,7 +94,7 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,877 out of 27,288 14%
Number of Slice LUTs: 3,871 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
......@@ -111,18 +107,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 94
Number with same-slice register load: 61
Number with same-slice carry load: 33
Number used exclusively as route-thrus: 88
Number with same-slice register load: 54
Number with same-slice carry load: 34
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,513 out of 6,822 22%
Number of occupied Slices: 1,514 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,843
Number with an unused Flip Flop: 1,551 out of 4,843 32%
Number with an unused LUT: 966 out of 4,843 19%
Number of fully used LUT-FF pairs: 2,326 out of 4,843 48%
Number of LUT Flip Flop pairs used: 4,830
Number with an unused Flip Flop: 1,533 out of 4,830 31%
Number with an unused LUT: 959 out of 4,830 19%
Number of fully used LUT-FF pairs: 2,338 out of 4,830 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
......@@ -135,7 +131,7 @@ Slice Logic Distribution:
IO Utilization:
Number of bonded IOBs: 134 out of 296 45%
Number of LOCed IOBs: 133 out of 134 99%
Number of LOCed IOBs: 134 out of 134 100%
IOB Flip Flops: 55
Specific Feature Utilization:
......@@ -178,9 +174,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 354 MB
Total REAL time to MAP completion: 2 mins 21 secs
Total CPU time to MAP completion: 1 mins 49 secs
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 1 mins 45 secs
Total CPU time to MAP completion: 1 mins 44 secs
Mapping completed.
See MAP report file "spec_tdc_map.mrp" for details.
hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp 0 → 100644
View file @ 7f103f41
Release 13.4 Map O.87xd (nt)
Xilinx Mapping Report File for Design 'spec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o spec_tdc_map.ncd spec_tdc.ngd spec_tdc.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 10:48:16 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Slice Logic Utilization:
Number of Slice Registers: 3,584 out of 54,576 6%
Number used as Flip Flops: 3,559
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,871 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
Number using O5 and O6: 1,202
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 88
Number with same-slice register load: 54
Number with same-slice carry load: 34
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,514 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,830
Number with an unused Flip Flop: 1,533 out of 4,830 31%
Number with an unused LUT: 959 out of 4,830 19%
Number of fully used LUT-FF pairs: 2,338 out of 4,830 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 134 out of 296 45%
Number of LOCed IOBs: 134 out of 134 100%
IOB Flip Flops: 55
Specific Feature Utilization:
Number of RAMB16BWERs: 11 out of 116 9%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 60 out of 376 15%
Number used as ILOGIC2s: 40
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 35 out of 376 9%
Number used as OLOGIC2s: 15
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 1 mins 45 secs
Total CPU time to MAP completion: 1 mins 44 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_227_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
Section 3 - Informational
-------------------------
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:LIT:243 - Logical network button1_i has no load.
INFO:LIT:395 - The above info message is repeated 142 more times for the
following (max. 5 shown):
button2_i,
tdc_in_fpga_1_i,
tdc_in_fpga_2_i,
tdc_in_fpga_3_i,
tdc_in_fpga_4_i
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
60 block(s) removed
3 block(s) optimized away
169 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" is loadless and has
been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" (ROM)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<5>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_5" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter5" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<5>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv1_INV_0"
(BUF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_8" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter8" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<8>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<6>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_6" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter6" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<6>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<7>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_7" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter7" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<7>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<0>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_0" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<0>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<1>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_1" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter1" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<1>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<2>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_2" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter2" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<2>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<3>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_3" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter3" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<3>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<4>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_4" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<4>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0364_inv1" (ROM)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[11].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[12].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[13].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[14].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[15].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[1].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[2].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[3].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[4].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[5].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[6].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[7].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[8].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[9].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25"
(ROM) removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)" is
sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| carrier_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| irq_p_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| l2p_clk_n_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| l2p_clk_p_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| l2p_data_o<0> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<1> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<2> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<3> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<4> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<5> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<6> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<7> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<8> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<9> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<10> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<11> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<12> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<13> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<14> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<15> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_dframe_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_edb_o | IOB | OUTPUT | SSTL18_I | | | | OFF | | |
| l2p_rdy_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
| l2p_valid_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l_wr_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| l_wr_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| led_green_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_red_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| mezz_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| mezz_sys_scl_b | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| mezz_sys_sda_b | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| p2l_clk_n_i | IOB | INPUT | DIFF_SSTL18_I | | | | | | |
| p2l_clk_p_i | IOB | INPUT | DIFF_SSTL18_I | | | | ISERDES | | VARIABLE |
| p2l_data_i<0> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<1> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<2> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<3> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<4> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<5> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<6> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<7> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<8> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<9> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<10> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<11> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<12> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<13> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<14> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<15> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_dframe_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_rdy_o | IOB | OUTPUT | SSTL18_I | | | | | | |
| p2l_valid_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p_rd_d_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| p_rd_d_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| p_wr_rdy_o<0> | IOB | OUTPUT | SSTL18_I | | | | | | |
| p_wr_rdy_o<1> | IOB | OUTPUT | SSTL18_I | | | | | | |
| p_wr_req_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
| p_wr_req_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
| pcb_ver_i<0> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
| pll_cs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_dac_sync_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| prsnt_m2c_n_i | IOB | INPUT | LVCMOS25 | | | | | | |
| rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| rst_n_a_i | IOB | INPUT | LVCMOS18 | | | | | | |
| rx_error_o | IOB | OUTPUT | SSTL18_I | | | | | | |
| start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc_clk_125m_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc_clk_125m_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tx_error_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
| vc_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
| vc_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
| wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
View file @ 7f103f41
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Tue Jun 17 20:01:10 2014
PCBE13136:: Wed Jun 18 11:30:31 2014
par -w -intstyle ise -ol high -xe c -mt off wr_spec_tdc_map.ncd wr_spec_tdc.ncd
wr_spec_tdc.pcf
......@@ -40,10 +40,10 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,697 out of 27,288 39%
Number of Slice LUTs: 10,661 out of 27,288 39%
Number used as logic: 10,390 out of 27,288 38%
Number using O6 output only: 7,384
Number using O5 output only: 775
Number using O6 output only: 7,383
Number using O5 output only: 776
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
......@@ -56,18 +56,18 @@ Slice Logic Utilization:
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 240
Number with same-slice register load: 164
Number with same-slice carry load: 76
Number used exclusively as route-thrus: 204
Number with same-slice register load: 133
Number with same-slice carry load: 71
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,977 out of 6,822 58%
Number of occupied Slices: 4,024 out of 6,822 58%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,389
Number with an unused Flip Flop: 4,852 out of 12,389 39%
Number with an unused LUT: 1,692 out of 12,389 13%
Number of fully used LUT-FF pairs: 5,845 out of 12,389 47%
Number of LUT Flip Flop pairs used: 12,505
Number with an unused Flip Flop: 4,934 out of 12,505 39%
Number with an unused LUT: 1,844 out of 12,505 14%
Number of fully used LUT-FF pairs: 5,727 out of 12,505 45%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -130,7 +130,7 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 21 secs
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 21 secs
WARNING:Par:288 - The signal sfp_rate_select_b_IBUF has no load. PAR will not attempt to route this signal.
......@@ -144,51 +144,51 @@ WARNING:Par:288 - The signal p_wr_req_i<1>_IBUF has no load. PAR will not attem
WARNING:Par:288 - The signal pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sfp_los_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
PAR will not attempt to route this signal.
Starting Router
Phase 1 : 70784 unrouted; REAL time: 23 secs
Phase 1 : 70597 unrouted; REAL time: 23 secs
Phase 2 : 62138 unrouted; REAL time: 28 secs
Phase 2 : 62018 unrouted; REAL time: 27 secs
Phase 3 : 32916 unrouted; REAL time: 58 secs
Phase 3 : 32669 unrouted; REAL time: 1 mins 3 secs
Phase 4 : 32945 unrouted; (Setup:0, Hold:77234, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 4 : 32678 unrouted; (Setup:0, Hold:74926, Component Switching Limit:0) REAL time: 1 mins 6 secs
Updating file: wr_spec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:74776, Component Switching Limit:0) REAL time: 2 mins 19 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:69648, Component Switching Limit:0) REAL time: 2 mins 24 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:74776, Component Switching Limit:0) REAL time: 2 mins 19 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:69648, Component Switching Limit:0) REAL time: 2 mins 24 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:74776, Component Switching Limit:0) REAL time: 2 mins 19 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:69648, Component Switching Limit:0) REAL time: 2 mins 24 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:74776, Component Switching Limit:0) REAL time: 2 mins 19 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:69648, Component Switching Limit:0) REAL time: 2 mins 24 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:74776, Component Switching Limit:0) REAL time: 2 mins 19 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:69648, Component Switching Limit:0) REAL time: 2 mins 24 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 21 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 25 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 26 secs
Total REAL time to Router completion: 2 mins 26 secs
Total CPU time to Router completion: 2 mins 30 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 29 secs
Total REAL time to Router completion: 2 mins 30 secs
Total CPU time to Router completion: 2 mins 33 secs
Partition Implementation Status
-------------------------------
......@@ -206,24 +206,24 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_62m5_sys | BUFGMUX_X3Y13| No | 1632 | 0.529 | 1.740 |
| clk_62m5_sys | BUFGMUX_X3Y13| No | 1623 | 0.529 | 1.740 |
+---------------------+--------------+------+------+------------+-------------+
| clk_125m_mezz | BUFGMUX_X3Y7| No | 802 | 0.551 | 1.762 |
| clk_125m_mezz | BUFGMUX_X3Y7| No | 733 | 0.549 | 1.762 |
+---------------------+--------------+------+------+------------+-------------+
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 140 | 0.076 | 1.290 |
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 145 | 0.077 | 1.290 |
+---------------------+--------------+------+------+------------+-------------+
|clk_125m_pllref_BUFG | | | | | |
| | BUFGMUX_X2Y1| No | 146 | 0.068 | 1.281 |
| | BUFGMUX_X2Y1| No | 136 | 0.061 | 1.281 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y4| No | 236 | 0.522 | 1.733 |
| clk | BUFGMUX_X2Y4| No | 238 | 0.522 | 1.733 |
+---------------------+--------------+------+------+------------+-------------+
| clk_dmtd | BUFGMUX_X2Y2| No | 75 | 0.023 | 1.241 |
| clk_dmtd | BUFGMUX_X2Y2| No | 90 | 0.039 | 1.250 |
+---------------------+--------------+------+------+------------+-------------+
|U_WR_CORE/WRPC/LM32_ | | | | | |
|CORE/gen_profile_med | | | | | |
|ium_icache_debug.U_W | | | | | |
| rapped_LM32/jtck | Local| | 8 | 3.580 | 6.244 |
| rapped_LM32/jtck | Local| | 9 | 1.747 | 4.075 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc_mezz/cmp_tdc | | | | | |
|_core/data_engine_bl | | | | | |
......@@ -261,36 +261,32 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.028ns| 7.972ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.299ns| | 0| 0
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.054ns| 7.946ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.388ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | SETUP | 0.045ns| 7.910ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | HOLD | 0.379ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_RXTS = MAXDELAY FROM TIMEGRP "rx_ts_tr | SETUP | 0.080ns| 1.920ns| 0| 0
ig" TO TIMEGRP "FFS" 2 ns DATAPAT | HOLD | 0.439ns| | 0| 0
TS_RXTS = MAXDELAY FROM TIMEGRP "rx_ts_tr | SETUP | 0.058ns| 1.942ns| 0| 0
ig" TO TIMEGRP "FFS" 2 ns DATAPAT | HOLD | 0.485ns| | 0| 0
HONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.255ns| 4.745ns| 0| 0
1_1 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.055ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.078ns| 4.922ns| 0| 0
1_1 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.077ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_1" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP " | SETUP | 0.316ns| 7.684ns| 0| 0
U_GTP_ch1_rx_divclk" TS_U_GTP_ch1 | HOLD | 0.322ns| | 0| 0
TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP " | SETUP | 0.187ns| 7.813ns| 0| 0
U_GTP_ch1_rx_divclk" TS_U_GTP_ch1 | HOLD | 0.343ns| | 0| 0
_gtp_clkout_int_1_ HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ = MAXDELAY FROM TIMEGRP "skew_limit" | SETUP | 0.939ns| 1.061ns| 0| 0
TO TIMEGRP "FFS" 2 ns DATAPATHONLY | HOLD | 0.412ns| | 0| 0
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | SETUP | 0.307ns| 7.693ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | HOLD | 0.426ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_pllout_clk_sys = PERIOD TIMEGRP "pllou | SETUP | 1.038ns| 14.962ns| 0| 0
t_clk_sys" TS_clk_20m_vcxo_i / 3.125 | HOLD | 0.108ns| | 0| 0
HIGH 50% | | | | |
TS_ = MAXDELAY FROM TIMEGRP "skew_limit" | SETUP | 0.795ns| 1.205ns| 0| 0
TO TIMEGRP "FFS" 2 ns DATAPATHONLY | HOLD | 0.436ns| | 0| 0
----------------------------------------------------------------------------------------------------------
ts_x3 = MAXDELAY FROM TIMEGRP "clk_62m5_s | SETUP | 1.290ns| 8.710ns| 0| 0
ys" TO TIMEGRP "U_GTP_ch1_rx_divclk" | HOLD | 0.469ns| | 0| 0
10 ns DATAPATHONLY | | | | |
TS_pllout_clk_sys = PERIOD TIMEGRP "pllou | SETUP | 1.107ns| 14.893ns| 0| 0
t_clk_sys" TS_clk_20m_vcxo_i / 3.125 | HOLD | 0.263ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
= PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
......@@ -321,31 +317,39 @@ Asterisk (*) preceding a constraint indicates it was not met.
re_cmp_clk_in_rx_pllout_x1" TS_cm | | | | |
p_gn4124_core_cmp_clk_in_buf_P_clk PHASE | | | | |
1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock = MAXDELAY FROM TIME | SETUP | 2.487ns| 7.513ns| 0| 0
GRP "clk_62m5_sys" TO TIMEGRP "td | HOLD | 0.519ns| | 0| 0
c_clk_125m_p_i" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p_i" 5 ns HIGH 50% | | | | |
ts_x3 = MAXDELAY FROM TIMEGRP "clk_62m5_s | SETUP | 2.944ns| 7.056ns| 0| 0
ys" TO TIMEGRP "U_GTP_ch1_rx_divclk" | HOLD | 0.609ns| | 0| 0
10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
n_i" 5 ns HIGH 50% | | | | |
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | SETUP | 3.299ns| 6.701ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "clk_1 | HOLD | 0.386ns| | 0| 0
25m_pllref_n_i" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_x4 = MAXDELAY FROM TIMEGRP "U_GTP_ch1_ | SETUP | 3.696ns| 6.304ns| 0| 0
rx_divclk" TO TIMEGRP "clk_62m5_sys" | HOLD | 0.346ns| | 0| 0
10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_P_clk = PER | MINPERIOD | 4.075ns| 0.925ns| 0| 0
IOD TIMEGRP "cmp_gn4124_core/cmp_ | | | | |
clk_in/P_clk" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock = MAXDELAY FROM TIME | SETUP | 4.138ns| 5.862ns| 0| 0
GRP "clk_62m5_sys" TO TIMEGRP "td | HOLD | 0.547ns| | 0| 0
c_clk_125m_p_i" 10 ns DATAPATHONLY | | | | |
TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
n_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | SETUP | 4.381ns| 5.619ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "clk_1 | HOLD | 0.479ns| | 0| 0
25m_pllref_n_i" 10 ns DATAPATHONLY | | | | |
TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_x4 = MAXDELAY FROM TIMEGRP "U_GTP_ch1_ | SETUP | 4.642ns| 5.358ns| 0| 0
rx_divclk" TO TIMEGRP "clk_62m5_sys" | HOLD | 0.376ns| | 0| 0
10 ns DATAPATHONLY | | | | |
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 4.099ns| 5.901ns| 0| 0
"clk_125m_pllref_p_i" TO TIMEGRP | HOLD | 0.569ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_gtp_p_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
_125m_gtp_p_i" 8 ns HIGH 50% | | | | |
......@@ -356,21 +360,17 @@ Asterisk (*) preceding a constraint indicates it was not met.
TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_ | MINPERIOD | 4.876ns| 3.124ns| 0| 0
clk_125m_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 5.084ns| 4.916ns| 0| 0
"clk_125m_pllref_p_i" TO TIMEGRP | HOLD | 0.452ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllo | SETUP | 6.131ns| 9.869ns| 0| 0
ut_clk_dmtd" TS_clk_20m_vcxo_i / | HOLD | 0.096ns| | 0| 0
TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllo | SETUP | 6.496ns| 9.504ns| 0| 0
ut_clk_dmtd" TS_clk_20m_vcxo_i / | HOLD | 0.233ns| | 0| 0
3.125 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock2 = MAXDELAY FROM TIM | SETUP | 6.237ns| 3.763ns| 0| 0
EGRP "tdc_clk_125m_p_i" TO TIMEGRP | HOLD | 0.377ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD T | MINPERIOD | 7.075ns| 0.925ns| 0| 0
IMEGRP "U_GTP/ch1_gtp_clkout_int<1>" | | | | |
125 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock2 = MAXDELAY FROM TIM | SETUP | 7.565ns| 2.435ns| 0| 0
EGRP "tdc_clk_125m_p_i" TO TIMEGRP | HOLD | 0.497ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int = PERIOD TIMEGRP "cmp_gn412 | | | | |
......@@ -402,9 +402,9 @@ Derived Constraints for TS_clk_20m_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 46.756ns| 0| 0| 0| 1682692|
| TS_pllout_clk_dmtd | 16.000ns| 9.869ns| N/A| 0| 0| 9425| 0|
| TS_pllout_clk_sys | 16.000ns| 14.962ns| N/A| 0| 0| 1673267| 0|
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 46.541ns| 0| 0| 0| 1682692|
| TS_pllout_clk_dmtd | 16.000ns| 9.504ns| N/A| 0| 0| 9425| 0|
| TS_pllout_clk_sys | 16.000ns| 14.893ns| N/A| 0| 0| 1673267| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_p2l_clk_p_i
......@@ -443,13 +443,13 @@ Derived Constraints for TS_cmp_gn4124_core_cmp_clk_in_P_clk
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_cmp_gn4124_core_cmp_clk_in_P| 5.000ns| 0.925ns| 4.745ns| 0| 0| 0| 5838|
|TS_cmp_gn4124_core_cmp_clk_in_P| 5.000ns| 0.925ns| 4.922ns| 0| 0| 0| 5838|
|_clk | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.745ns| 0| 0| 0| 5838|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.922ns| 0| 0| 0| 5838|
| buf_P_clk_1 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_1 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.745ns| N/A| 0| 0| 5838| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.922ns| N/A| 0| 0| 5838| 0|
| _rx_pllout_x1_1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -459,8 +459,8 @@ Derived Constraints for TS_U_GTP_ch1_gtp_clkout_int_1_
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_GTP_ch1_gtp_clkout_int_1_ | 8.000ns| 0.925ns| 7.684ns| 0| 0| 0| 20096|
| TS_U_GTP_ch1_rx_divclk | 8.000ns| 7.684ns| N/A| 0| 0| 20096| 0|
|TS_U_GTP_ch1_gtp_clkout_int_1_ | 8.000ns| 0.925ns| 7.813ns| 0| 0| 0| 20096|
| TS_U_GTP_ch1_rx_divclk | 8.000ns| 7.813ns| N/A| 0| 0| 20096| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
......@@ -477,10 +477,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 16 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 2 mins 32 secs
Total CPU time to PAR completion: 2 mins 36 secs
Total REAL time to PAR completion: 2 mins 36 secs
Total CPU time to PAR completion: 2 mins 39 secs
Peak Memory Usage: 458 MB
Peak Memory Usage: 459 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
View file @ 7f103f41
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/with_wrabbit/wr_spec_tdc.xise
View file @ 7f103f41
......@@ -1041,7 +1041,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../../top/spec/with_wrabbit/wr_spec_tdc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="326"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map
View file @ 7f103f41
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 19:54:15 2014
Mapped Date : Wed Jun 18 11:23:56 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
......@@ -26,57 +26,57 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 45 secs
Total CPU time at the beginning of Placer: 41 secs
Total REAL time at the beginning of Placer: 42 secs
Total CPU time at the beginning of Placer: 39 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:7ac4c860) REAL time: 49 secs
Phase 1.1 Initial Placement Analysis (Checksum:1353f92f) REAL time: 46 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:7ac4c860) REAL time: 51 secs
Phase 2.7 Design Feasibility Check (Checksum:1353f92f) REAL time: 47 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:403893f8) REAL time: 51 secs
Phase 3.31 Local Placement Optimization (Checksum:e55e413f) REAL time: 47 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:bb368ef0) REAL time: 1 mins 43 secs
(Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:bb368ef0) REAL time: 1 mins 43 secs
Phase 5.36 Local Placement Optimization (Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:bb368ef0) REAL time: 1 mins 43 secs
Phase 6.30 Global Clock Region Assignment (Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:bb368ef0) REAL time: 1 mins 43 secs
Phase 7.3 Local Placement Optimization (Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:bb368ef0) REAL time: 1 mins 44 secs
Phase 8.5 Local Placement Optimization (Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 9.8 Global Placement
......................
..........................................................................................
.............................................................................................................................................................................
........................................................................................................................................................
......................................................................
Phase 9.8 Global Placement (Checksum:12a29ddc) REAL time: 5 mins 35 secs
........................
.....................................................
............................................................................................................................................................................
..................................................................................................................................................................................
.................................................................................
Phase 9.8 Global Placement (Checksum:3d13c910) REAL time: 5 mins 19 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:12a29ddc) REAL time: 5 mins 36 secs
Phase 10.5 Local Placement Optimization (Checksum:3d13c910) REAL time: 5 mins 20 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:befb4ab8) REAL time: 6 mins 22 secs
Phase 11.18 Placement Optimization (Checksum:a2ead40e) REAL time: 6 mins 1 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:befb4ab8) REAL time: 6 mins 22 secs
Phase 12.5 Local Placement Optimization (Checksum:a2ead40e) REAL time: 6 mins 1 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:a3dc479f) REAL time: 6 mins 23 secs
Phase 13.34 Placement Validation (Checksum:6637292) REAL time: 6 mins 2 secs
Total REAL time to Placer completion: 6 mins 42 secs
Total CPU time to Placer completion: 6 mins 32 secs
Total REAL time to Placer completion: 6 mins 21 secs
Total CPU time to Placer completion: 6 mins 14 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -85,19 +85,19 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
......@@ -105,7 +105,7 @@ WARNING:PhysDesignRules:367 - The signal
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......@@ -133,10 +133,10 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,697 out of 27,288 39%
Number of Slice LUTs: 10,661 out of 27,288 39%
Number used as logic: 10,390 out of 27,288 38%
Number using O6 output only: 7,384
Number using O5 output only: 775
Number using O6 output only: 7,383
Number using O5 output only: 776
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
......@@ -149,18 +149,18 @@ Slice Logic Utilization:
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 240
Number with same-slice register load: 164
Number with same-slice carry load: 76
Number used exclusively as route-thrus: 204
Number with same-slice register load: 133
Number with same-slice carry load: 71
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,977 out of 6,822 58%
Number of occupied Slices: 4,024 out of 6,822 58%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,389
Number with an unused Flip Flop: 4,852 out of 12,389 39%
Number with an unused LUT: 1,692 out of 12,389 13%
Number of fully used LUT-FF pairs: 5,845 out of 12,389 47%
Number of LUT Flip Flop pairs used: 12,505
Number with an unused Flip Flop: 4,934 out of 12,505 39%
Number with an unused LUT: 1,844 out of 12,505 14%
Number of fully used LUT-FF pairs: 5,727 out of 12,505 45%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 990 out of 54,576 1%
......@@ -220,9 +220,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 480 MB
Total REAL time to MAP completion: 6 mins 54 secs
Total CPU time to MAP completion: 6 mins 44 secs
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 33 secs
Total CPU time to MAP completion: 6 mins 26 secs
Mapping completed.
See MAP report file "wr_spec_tdc_map.mrp" for details.
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp 0 → 100644
View file @ 7f103f41
Release 13.4 Map O.87xd (nt)
Xilinx Mapping Report File for Design 'wr_spec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o wr_spec_tdc_map.ncd wr_spec_tdc.ngd
wr_spec_tdc.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 11:23:56 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 9
Slice Logic Utilization:
Number of Slice Registers: 8,194 out of 54,576 15%
Number used as Flip Flops: 8,168
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,661 out of 27,288 39%
Number used as logic: 10,390 out of 27,288 38%
Number using O6 output only: 7,383
Number using O5 output only: 776
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 24
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 43
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 204
Number with same-slice register load: 133
Number with same-slice carry load: 71
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,024 out of 6,822 58%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,505
Number with an unused Flip Flop: 4,934 out of 12,505 39%
Number with an unused LUT: 1,844 out of 12,505 14%
Number of fully used LUT-FF pairs: 5,727 out of 12,505 45%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 990 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 152 out of 296 51%
Number of LOCed IOBs: 152 out of 152 100%
IOB Flip Flops: 57
Number of bonded IPADs: 4 out of 16 25%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 8 25%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 62 out of 116 53%
Number of RAMB8BWERs: 9 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 7
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 61 out of 376 16%
Number used as ILOGIC2s: 41
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 36 out of 376 9%
Number used as OLOGIC2s: 16
Number used as OSERDES2s: 20
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of GTPA1_DUALs: 1 out of 2 50%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 3 out of 4 75%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 33 secs
Total CPU time to MAP completion: 6 mins 26 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_441_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
.U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
READ_FIRST mode has certain restrictions. Make sure that there is no address
collision. A read/write on one port and a write operation from the other port
at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
bits wide, A13-7 including A5 cannot be the same. Violating this restriction
may result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:LIT:243 - Logical network tdc_in_fpga_2_i has no load.
INFO:LIT:395 - The above info message is repeated 144 more times for the
following (max. 5 shown):
tdc_in_fpga_3_i,
tdc_in_fpga_4_i,
tdc_in_fpga_5_i,
carrier_scl_b,
carrier_sda_b
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
60 block(s) removed
3 block(s) optimized away
169 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" is loadless and has
been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" (ROM)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<5>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_5" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter5" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<5>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv1_INV_0"
(BUF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_8" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter8" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<8>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<6>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_6" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter6" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<6>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<7>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_7" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter7" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<7>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<0>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_0" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<0>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<1>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_1" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter1" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<1>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<2>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_2" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter2" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<2>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<3>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_3" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter3" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<3>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<4>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_4" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<4>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0364_inv1" (ROM)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[11].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[12].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[13].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[14].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[15].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[1].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[2].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[3].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[4].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[5].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[6].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[7].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[8].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[9].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25"
(ROM) removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)" is
sourceless and has been removed.
The signal
"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)" is
sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| button1_i | IOB | INPUT | LVCMOS18 | | | | | | |
| button2_i | IOB | INPUT | LVCMOS18 | | | | | | |
| carrier_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| clk_125m_gtp_n_i | IPAD | INPUT | | | | | | | |
| clk_125m_gtp_p_i | IPAD | INPUT | | | | | | | |
| clk_125m_pllref_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| clk_125m_pllref_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| dac_cs1_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dac_cs2_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dac_din_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dac_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| irq_p_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| l2p_clk_n_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| l2p_clk_p_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| l2p_data_o<0> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<1> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<2> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<3> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<4> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<5> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<6> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<7> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<8> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<9> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<10> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<11> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<12> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<13> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<14> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_data_o<15> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_dframe_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l2p_edb_o | IOB | OUTPUT | SSTL18_I | | | | OFF | | |
| l2p_rdy_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
| l2p_valid_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| l_wr_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| l_wr_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| led_green | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_red | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| mezz_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| mezz_sys_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| mezz_sys_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| p2l_clk_n_i | IOB | INPUT | DIFF_SSTL18_I | | | | | | |
| p2l_clk_p_i | IOB | INPUT | DIFF_SSTL18_I | | | | ISERDES | | VARIABLE |
| p2l_data_i<0> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<1> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<2> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<3> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<4> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<5> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<6> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<7> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<8> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<9> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<10> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<11> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<12> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<13> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<14> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_data_i<15> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_dframe_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p2l_rdy_o | IOB | OUTPUT | SSTL18_I | | | | | | |
| p2l_valid_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| p_rd_d_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| p_rd_d_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
| p_wr_rdy_o<0> | IOB | OUTPUT | SSTL18_I | | | | | | |
| p_wr_rdy_o<1> | IOB | OUTPUT | SSTL18_I | | | | | | |
| p_wr_req_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
| p_wr_req_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
| pcb_ver_i<0> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
| pll_cs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_dac_sync_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| prsnt_m2c_n_i | IOB | INPUT | LVCMOS25 | | | | | | |
| rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| rst_n_a_i | IOB | INPUT | LVCMOS18 | | | | | | |
| rx_error_o | IOB | OUTPUT | SSTL18_I | | | | | | |
| sfp_los_i | IOB | INPUT | LVCMOS25 | | | | | | |
| sfp_mod_def0_b | IOB | INPUT | LVCMOS25 | | | | | | |
| sfp_mod_def1_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| sfp_mod_def2_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| sfp_rate_select_b | IOB | INPUT | LVCMOS25 | | | | | | |
| sfp_rxn_i | IPAD | INPUT | | | | | | | |
| sfp_rxp_i | IPAD | INPUT | | | | | | | |
| sfp_tx_disable_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| sfp_tx_fault_i | IOB | INPUT | LVCMOS25 | | | | | | |
| sfp_txn_o | OPAD | OUTPUT | | | | | | | |
| sfp_txp_o | OPAD | OUTPUT | | | | | | | |
| start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc_clk_125m_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc_clk_125m_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc_in_fpga_1_i | IOB | INPUT | LVCMOS25 | | | | | | |
| tdc_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tx_error_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
| uart_rxd_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| uart_txd_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| vc_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
| vc_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
| wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
hdl/syn/svec/no_wrabbit/svec_tdc.par
View file @ 7f103f41
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Tue Jun 17 20:09:53 2014
PCBE13136:: Wed Jun 18 12:30:56 2014
par -w -intstyle ise -ol high -xe c -mt off svec_tdc_map.ncd svec_tdc.ncd
svec_tdc.pcf
......@@ -40,11 +40,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,215 out of 92,152 9%
Number used as logic: 9,025 out of 92,152 9%
Number using O6 output only: 5,907
Number of Slice LUTs: 9,203 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,767
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
......@@ -53,18 +53,18 @@ Slice Logic Utilization:
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 155
Number with same-slice register load: 88
Number with same-slice carry load: 67
Number used exclusively as route-thrus: 142
Number with same-slice register load: 67
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,268 out of 23,038 14%
Number of occupied Slices: 3,359 out of 23,038 14%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,508
Number with an unused Flip Flop: 4,082 out of 10,508 38%
Number with an unused LUT: 1,293 out of 10,508 12%
Number of fully used LUT-FF pairs: 5,133 out of 10,508 48%
Number of LUT Flip Flop pairs used: 10,598
Number with an unused Flip Flop: 4,155 out of 10,598 39%
Number with an unused LUT: 1,395 out of 10,598 13%
Number of fully used LUT-FF pairs: 5,048 out of 10,598 47%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -118,8 +118,8 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 20 secs
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal tdc1_prsntm2c_n_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc1_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
......@@ -128,10 +128,139 @@ WARNING:Par:288 - The signal tdc2_prsntm2c_n_i_IBUF has no load. PAR will not a
Starting Router
Phase 1 : 56331 unrouted; REAL time: 23 secs
Phase 1 : 56357 unrouted; REAL time: 21 secs
Phase 2 : 49801 unrouted; REAL time: 30 secs
Phase 2 : 49824 unrouted; REAL time: 27 secs
Phase 3 : 21943 unrouted; REAL time: 1 mins 10 secs
Phase 3 : 21985 unrouted; REAL time: 1 mins 2 secs
Phase 4 : 21943 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 4 : 21986 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 8 secs
Updating file: svec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 50 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 50 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 50 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 50 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 50 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 50 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Total REAL time to Router completion: 1 mins 52 secs
Total CPU time to Router completion: 1 mins 53 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| tdc2_125m_clk | BUFGMUX_X2Y12| No | 752 | 0.820 | 1.917 |
+---------------------+--------------+------+------+------------+-------------+
| clk_62m5_sys | BUFGMUX_X2Y3| No | 860 | 0.755 | 1.923 |
+---------------------+--------------+------+------+------------+-------------+
| tdc1_125m_clk | BUFGMUX_X3Y7| No | 760 | 0.830 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc2/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_76_ | | | | | |
| o_Mux_41_o | Local| | 2 | 0.000 | 0.956 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc1/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_76_ | | | | | |
| o_Mux_41_o | Local| | 2 | 0.325 | 0.632 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 3
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP | SETUP | 0.253ns| 7.747ns| 0| 0
"tdc2_125m_clk_n_i" 8 ns HIGH 50% | HOLD | 0.271ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "td | SETUP | 0.259ns| 7.741ns| 0| 0
c1_125m_clk_p_i" 8 ns HIGH 50% | HOLD | 0.407ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc1_tdc_125m_clk_n_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc1_125m_clk_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_tdc2_tdc_125m_clk_p_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc2_125m_clk_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 17.555ns| 2.445ns| 0| 0
"tdc2_125m_clk" TO TIMEGRP "clk_ | HOLD | 0.365ns| | 0| 0
62m5_sys" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP | SETUP | 18.787ns| 1.213ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "tdc2_ | HOLD | 0.527ns| | 0| 0
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | N/A | N/A| N/A| N/A| N/A
"clk_62m5_sys" TO TIMEGRP "tdc2_ | | | | |
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 4 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 57 secs
Total CPU time to PAR completion: 1 mins 58 secs
Peak Memory Usage: 539 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 6
Number of info messages: 2
Writing design to file svec_tdc.ncd
PAR done!
hdl/syn/svec/no_wrabbit/svec_tdc.twr
View file @ 7f103f41
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/no_wrabbit/svec_tdc.xise
View file @ 7f103f41
......@@ -1045,7 +1045,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../../top/svec/no_wrabbit/svec_tdc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="316"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/syn/svec/no_wrabbit/svec_tdc_map.map
View file @ 7f103f41
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 20:06:12 2014
Mapped Date : Wed Jun 18 12:27:04 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
......@@ -25,56 +25,56 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 32 secs
Total CPU time at the beginning of Placer: 31 secs
Total REAL time at the beginning of Placer: 33 secs
Total CPU time at the beginning of Placer: 32 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:be5d5549) REAL time: 39 secs
Phase 1.1 Initial Placement Analysis (Checksum:a7de1977) REAL time: 39 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:be5d5549) REAL time: 41 secs
Phase 2.7 Design Feasibility Check (Checksum:a7de1977) REAL time: 41 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:be5d5549) REAL time: 41 secs
Phase 3.31 Local Placement Optimization (Checksum:a7de1977) REAL time: 41 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:daa240) REAL time: 54 secs
(Checksum:2b539d14) REAL time: 55 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:daa240) REAL time: 54 secs
Phase 5.36 Local Placement Optimization (Checksum:2b539d14) REAL time: 55 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:daa240) REAL time: 54 secs
Phase 6.30 Global Clock Region Assignment (Checksum:2b539d14) REAL time: 55 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:daa240) REAL time: 55 secs
Phase 7.3 Local Placement Optimization (Checksum:2b539d14) REAL time: 55 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:daa240) REAL time: 55 secs
Phase 8.5 Local Placement Optimization (Checksum:2b539d14) REAL time: 56 secs
Phase 9.8 Global Placement
...................................
................................................................................................................................................................................................................
..................................................................................................................................................................................
.................................................
Phase 9.8 Global Placement (Checksum:76fab4b7) REAL time: 1 mins 57 secs
.........................................
...............................................................................................................................................................................................................
.........................................................................................................................................................................................
.......................................................................
Phase 9.8 Global Placement (Checksum:4c7cc37c) REAL time: 2 mins
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:76fab4b7) REAL time: 1 mins 57 secs
Phase 10.5 Local Placement Optimization (Checksum:4c7cc37c) REAL time: 2 mins
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:a0540d59) REAL time: 2 mins 45 secs
Phase 11.18 Placement Optimization (Checksum:4ab5face) REAL time: 2 mins 54 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:a0540d59) REAL time: 2 mins 45 secs
Phase 12.5 Local Placement Optimization (Checksum:4ab5face) REAL time: 2 mins 54 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:fbe1fef2) REAL time: 2 mins 46 secs
Phase 13.34 Placement Validation (Checksum:ed98fec0) REAL time: 2 mins 55 secs
Total REAL time to Placer completion: 3 mins 31 secs
Total CPU time to Placer completion: 3 mins 28 secs
Total REAL time to Placer completion: 3 mins 41 secs
Total CPU time to Placer completion: 3 mins 39 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -102,11 +102,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,215 out of 92,152 9%
Number used as logic: 9,025 out of 92,152 9%
Number using O6 output only: 5,907
Number of Slice LUTs: 9,203 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,767
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
......@@ -115,18 +115,18 @@ Slice Logic Utilization:
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 155
Number with same-slice register load: 88
Number with same-slice carry load: 67
Number used exclusively as route-thrus: 142
Number with same-slice register load: 67
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,268 out of 23,038 14%
Number of occupied Slices: 3,359 out of 23,038 14%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,508
Number with an unused Flip Flop: 4,082 out of 10,508 38%
Number with an unused LUT: 1,293 out of 10,508 12%
Number of fully used LUT-FF pairs: 5,133 out of 10,508 48%
Number of LUT Flip Flop pairs used: 10,598
Number with an unused Flip Flop: 4,155 out of 10,598 39%
Number with an unused LUT: 1,395 out of 10,598 13%
Number of fully used LUT-FF pairs: 5,048 out of 10,598 47%
Number of unique control sets: 264
Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1%
......@@ -177,9 +177,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 534 MB
Total REAL time to MAP completion: 3 mins 40 secs
Total CPU time to MAP completion: 3 mins 37 secs
Peak Memory Usage: 529 MB
Total REAL time to MAP completion: 3 mins 50 secs
Total CPU time to MAP completion: 3 mins 47 secs
Mapping completed.
See MAP report file "svec_tdc_map.mrp" for details.
hdl/syn/svec/no_wrabbit/svec_tdc_map.mrp
View file @ 7f103f41
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 20:06:12 2014
Mapped Date : Wed Jun 18 12:27:04 2014
Design Summary
--------------
......@@ -22,11 +22,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,215 out of 92,152 9%
Number used as logic: 9,025 out of 92,152 9%
Number using O6 output only: 5,907
Number of Slice LUTs: 9,203 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,767
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
......@@ -35,18 +35,18 @@ Slice Logic Utilization:
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 155
Number with same-slice register load: 88
Number with same-slice carry load: 67
Number used exclusively as route-thrus: 142
Number with same-slice register load: 67
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,268 out of 23,038 14%
Number of occupied Slices: 3,359 out of 23,038 14%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,508
Number with an unused Flip Flop: 4,082 out of 10,508 38%
Number with an unused LUT: 1,293 out of 10,508 12%
Number of fully used LUT-FF pairs: 5,133 out of 10,508 48%
Number of LUT Flip Flop pairs used: 10,598
Number with an unused Flip Flop: 4,155 out of 10,598 39%
Number with an unused LUT: 1,395 out of 10,598 13%
Number of fully used LUT-FF pairs: 5,048 out of 10,598 47%
Number of unique control sets: 264
Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1%
......@@ -97,9 +97,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 534 MB
Total REAL time to MAP completion: 3 mins 40 secs
Total CPU time to MAP completion: 3 mins 37 secs
Peak Memory Usage: 529 MB
Total REAL time to MAP completion: 3 mins 50 secs
Total CPU time to MAP completion: 3 mins 47 secs
Table of Contents
-----------------
......
hdl/syn/svec/with_wrabbit/wr_svec_tdc.par
View file @ 7f103f41
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Tue Jun 17 19:52:40 2014
PCBE13136:: Wed Jun 18 12:18:06 2014
par -w -intstyle ise -ol high -xe c -mt off wr_svec_tdc_map.ncd wr_svec_tdc.ncd
wr_svec_tdc.pcf
......@@ -27,11 +27,6 @@ to function, but you no longer qualify for Xilinx software updates or new releas
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.21 2012-01-07".
......@@ -45,10 +40,10 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,088 out of 92,152 17%
Number of Slice LUTs: 16,200 out of 92,152 17%
Number used as logic: 15,786 out of 92,152 17%
Number using O6 output only: 11,162
Number using O5 output only: 844
Number using O6 output only: 11,163
Number using O5 output only: 843
Number using O5 and O6: 3,780
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
......@@ -61,18 +56,18 @@ Slice Logic Utilization:
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 215
Number with same-slice register load: 110
Number with same-slice carry load: 105
Number used exclusively as route-thrus: 327
Number with same-slice register load: 220
Number with same-slice carry load: 107
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,165 out of 23,038 26%
Number of occupied Slices: 6,331 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,518
Number with an unused Flip Flop: 7,828 out of 18,518 42%
Number with an unused LUT: 2,430 out of 18,518 13%
Number of fully used LUT-FF pairs: 8,260 out of 18,518 44%
Number of LUT Flip Flop pairs used: 18,576
Number with an unused Flip Flop: 7,974 out of 18,576 42%
Number with an unused LUT: 2,376 out of 18,576 12%
Number of fully used LUT-FF pairs: 8,226 out of 18,576 44%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -83,10 +78,13 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 263 out of 540 48%
Number of bonded IOBs: 269 out of 540 49%
Number of LOCed IOBs: 269 out of 269 100%
IOB Flip Flops: 203
Number of bonded IPADs: 4 out of 32 12%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 16 12%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 65 out of 268 24%
......@@ -125,55 +123,63 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 23 secs
Finished initial Timing Analysis. REAL time: 23 secs
WARNING:Par:288 - The signal sfp_tx_fault_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc1_prsntm2c_n_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sfp_los_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc1_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc2_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc2_prsntm2c_n_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
PAR will not attempt to route this signal.
Starting Router
Phase 1 : 102577 unrouted; REAL time: 27 secs
Phase 1 : 102696 unrouted; REAL time: 27 secs
Phase 2 : 90904 unrouted; REAL time: 33 secs
Phase 2 : 91041 unrouted; REAL time: 37 secs
Phase 3 : 45316 unrouted; REAL time: 2 mins 16 secs
Phase 3 : 42856 unrouted; REAL time: 2 mins 29 secs
Phase 4 : 45331 unrouted; (Par is working to improve performance) REAL time: 2 mins 25 secs
Phase 4 : 42856 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 36 secs
Updating file: wr_svec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 4 mins 9 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 35 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 4 mins 9 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 35 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 4 mins 9 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 35 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 4 mins 9 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 35 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 4 mins 9 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 35 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 4 mins 10 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 35 secs
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 4 mins 17 secs
Total REAL time to Router completion: 4 mins 17 secs
Total CPU time to Router completion: 4 mins 18 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 38 secs
Total REAL time to Router completion: 3 mins 38 secs
Total CPU time to Router completion: 3 mins 35 secs
Partition Implementation Status
-------------------------------
......@@ -183,8 +189,62 @@ Partition Implementation Status
-------------------------------
Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_62m5_sys | BUFGMUX_X2Y3| No | 2246 | 0.839 | 1.923 |
+---------------------+--------------+------+------+------------+-------------+
| tdc2_125m_clk | BUFGMUX_X2Y12| No | 720 | 0.830 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
| tdc1_125m_clk | BUFGMUX_X3Y7| No | 719 | 0.830 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
| clk_dmtd | BUFGMUX_X3Y13| No | 114 | 0.274 | 1.360 |
+---------------------+--------------+------+------+------------+-------------+
|clk_125m_pllref_BUFG | | | | | |
| | BUFGMUX_X2Y4| No | 138 | 0.325 | 1.411 |
+---------------------+--------------+------+------+------------+-------------+
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 142 | 0.321 | 1.412 |
+---------------------+--------------+------+------+------------+-------------+
|U_Buf_CLK_GTP_ML_IBU | | | | | |
| F2 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|U_Buf_CLK_GTP_ML_IBU | | | | | |
| F1 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|U_WR_CORE/WRPC/LM32_ | | | | | |
|CORE/gen_profile_med | | | | | |
|ium_icache_debug.U_W | | | | | |
| rapped_LM32/jtck | Local| | 8 | 1.951 | 6.980 |
+---------------------+--------------+------+------+------------+-------------+
| clk_125m_gtp | Local| | 1 | 0.000 | 0.001 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc2/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_290 | | | | | |
| _o_Mux_41_o | Local| | 2 | 1.508 | 2.327 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc1/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_290 | | | | | |
| _o_Mux_41_o | Local| | 2 | 0.000 | 0.302 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 6
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
......@@ -193,27 +253,41 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 14.784ns| N/A| 0
_62m5_sys | HOLD | 0.259ns| | 0| 0
TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP | SETUP | 0.274ns| 7.726ns| 0| 0
"tdc2_125m_clk_n_i" 8 ns HIGH 50% | HOLD | 0.222ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "td | SETUP | 0.289ns| 7.711ns| 0| 0
c1_125m_clk_p_i" 8 ns HIGH 50% | HOLD | 0.367ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | SETUP | 0.541ns| 6.918ns| 0| 0
clk_125m_pllref_p_i" 8 ns HIGH 50% | HOLD | 0.380ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | MINPERIOD | 1.750ns| 6.250ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_gtp_n_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
_125m_gtp_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 5.976ns| N/A| 0
_dmtd | HOLD | 0.379ns| | 0| 0
TS_clk_125m_gtp_p_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
_125m_gtp_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 8.701ns| N/A| 0
_125m_pllref_BUFG | HOLD | 0.395ns| | 0| 0
TS_tdc1_tdc_125m_clk_n_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc1_125m_clk_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net tdc | SETUP | N/A| 9.616ns| N/A| 0
1_125m_clk | HOLD | 0.266ns| | 0| 0
TS_tdc2_tdc_125m_clk_p_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc2_125m_clk_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net tdc | SETUP | N/A| 10.874ns| N/A| 0
2_125m_clk | HOLD | 0.268ns| | 0| 0
ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP | SETUP | 11.610ns| 8.390ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "tdc2_ | HOLD | 0.590ns| | 0| 0
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net phy | SETUP | N/A| 8.026ns| N/A| 0
_rx_rbclk | HOLD | 0.322ns| | 0| 0
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 15.433ns| 4.567ns| 0| 0
"tdc2_125m_clk" TO TIMEGRP "clk_ | HOLD | 0.569ns| | 0| 0
62m5_sys" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U_W | SETUP | N/A| 1.769ns| N/A| 0
R_CORE/WRPC/LM32_CORE/gen_profile_medium_ | HOLD | 0.452ns| | 0| 0
icache_debug.U_Wrapped_LM32/jtck | | | | |
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | N/A | N/A| N/A| N/A| N/A
"clk_62m5_sys" TO TIMEGRP "tdc2_ | | | | |
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
......@@ -229,19 +303,20 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 4 mins 25 secs
Total CPU time to PAR completion: 4 mins 26 secs
Total REAL time to PAR completion: 3 mins 45 secs
Total CPU time to PAR completion: 3 mins 42 secs
Peak Memory Usage: 715 MB
Peak Memory Usage: 662 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 8
Number of info messages: 3
Number of warning messages: 14
Number of info messages: 2
Writing design to file wr_svec_tdc.ncd
......
hdl/syn/svec/with_wrabbit/wr_svec_tdc.twr
View file @ 7f103f41
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/with_wrabbit/wr_svec_tdc.xise
View file @ 7f103f41
......@@ -1046,7 +1046,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../../top/svec/with_wrabbit/wr_svec_tdc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="316"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.map
View file @ 7f103f41
......@@ -11,7 +11,7 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 20:09:58 2014
Mapped Date : Wed Jun 18 12:12:19 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
......@@ -26,33 +26,202 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 55 secs
Total CPU time at the beginning of Placer: 51 secs
Total REAL time at the beginning of Placer: 51 secs
Total CPU time at the beginning of Placer: 48 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:1eda26af) REAL time: 1 mins 4 secs
Phase 1.1 Initial Placement Analysis (Checksum:58a5c00) REAL time: 1 mins 1 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:1eda26af) REAL time: 1 mins 6 secs
Phase 2.7 Design Feasibility Check (Checksum:58a5c00) REAL time: 1 mins 3 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:9eebb6e8) REAL time: 1 mins 6 secs
Phase 3.31 Local Placement Optimization (Checksum:4be425da) REAL time: 1 mins 3 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:d9d30fd2) REAL time: 1 mins 26 secs
(Checksum:a584c7a0) REAL time: 1 mins 21 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:d9d30fd2) REAL time: 1 mins 26 secs
Phase 5.36 Local Placement Optimization (Checksum:a584c7a0) REAL time: 1 mins 21 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:d9d30fd2) REAL time: 1 mins 26 secs
Phase 6.30 Global Clock Region Assignment (Checksum:a584c7a0) REAL time: 1 mins 21 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:d9d30fd2) REAL time: 1 mins 27 secs
Phase 7.3 Local Placement Optimization (Checksum:a584c7a0) REAL time: 1 mins 22 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:d9d30fd2) REAL time: 1 mins 27 secs
Phase 8.5 Local Placement Optimization (Checksum:a584c7a0) REAL time: 1 mins 22 secs
Phase 9.8 Global Placement
.....................
.........................................
................................
.....................................................
..........................
Phase 9.8 Global Placement (Checksum:ac8519a8) REAL time: 3 mins 5 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:ac8519a8) REAL time: 3 mins 6 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:b020cb03) REAL time: 3 mins 56 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:b020cb03) REAL time: 3 mins 56 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:a3adcfe9) REAL time: 3 mins 57 secs
Total REAL time to Placer completion: 5 mins 30 secs
Total CPU time to Placer completion: 5 mins 25 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
.U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
READ_FIRST mode has certain restrictions. Make sure that there is no address
collision. A read/write on one port and a write operation from the other port
at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
bits wide, A13-7 including A5 cannot be the same. Violating this restriction
may result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 10
Slice Logic Utilization:
Number of Slice Registers: 11,683 out of 184,304 6%
Number used as Flip Flops: 11,632
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,200 out of 92,152 17%
Number used as logic: 15,786 out of 92,152 17%
Number using O6 output only: 11,163
Number using O5 output only: 843
Number using O5 and O6: 3,780
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 24
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 63
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 327
Number with same-slice register load: 220
Number with same-slice carry load: 107
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,331 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,576
Number with an unused Flip Flop: 7,974 out of 18,576 42%
Number with an unused LUT: 2,376 out of 18,576 12%
Number of fully used LUT-FF pairs: 8,226 out of 18,576 44%
Number of unique control sets: 502
Number of slice register sites lost
to control set restrictions: 1,223 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 269 out of 540 49%
Number of LOCed IOBs: 269 out of 269 100%
IOB Flip Flops: 203
Number of bonded IPADs: 4 out of 32 12%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 16 12%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 65 out of 268 24%
Number of RAMB8BWERs: 13 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 6 out of 16 37%
Number used as BUFGs: 6
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 139 out of 586 23%
Number used as ILOGIC2s: 139
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 64 out of 586 10%
Number used as OLOGIC2s: 64
Number used as OSERDES2s: 0
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 180 1%
Number of GTPA1_DUALs: 1 out of 4 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 2 out of 6 33%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 5 mins 46 secs
Total CPU time to MAP completion: 5 mins 40 secs
Mapping completed.
See MAP report file "wr_svec_tdc_map.mrp" for details.
hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.mrp
View file @ 7f103f41
......@@ -11,17 +11,19 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 20:09:58 2014
Mapped Date : Wed Jun 18 12:12:19 2014
Interim Summary
---------------
Design Summary
--------------
Number of errors: 0
Number of warnings: 10
Slice Logic Utilization:
Number of Slice Registers: 11,683 out of 184,304 6%
Number used as Flip Flops: 11,632
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 15,980 out of 92,152 17%
Number of Slice LUTs: 16,200 out of 92,152 17%
Number used as logic: 15,786 out of 92,152 17%
Number using O6 output only: 11,163
Number using O5 output only: 843
......@@ -37,17 +39,18 @@ Slice Logic Utilization:
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 107
Number with same-slice register load: 0
Number used exclusively as route-thrus: 327
Number with same-slice register load: 220
Number with same-slice carry load: 107
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,331 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 20,492
Number with an unused Flip Flop: 9,641 out of 20,492 47%
Number with an unused LUT: 4,512 out of 20,492 22%
Number of fully used LUT-FF pairs: 6,339 out of 20,492 30%
Number of LUT Flip Flop pairs used: 18,576
Number with an unused Flip Flop: 7,974 out of 18,576 42%
Number with an unused LUT: 2,376 out of 18,576 12%
Number of fully used LUT-FF pairs: 8,226 out of 18,576 44%
Number of unique control sets: 502
Number of slice register sites lost
to control set restrictions: 1,223 out of 184,304 1%
......@@ -100,3 +103,1016 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 5 mins 46 secs
Total CPU time to MAP completion: 5 mins 40 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
.U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
READ_FIRST mode has certain restrictions. Make sure that there is no address
collision. A read/write on one port and a write operation from the other port
at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
bits wide, A13-7 including A5 cannot be the same. Violating this restriction
may result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
INFO:LIT:243 - Logical network VME_BBSY_n_i has no load.
INFO:LIT:395 - The above info message is repeated 273 more times for the
following (max. 5 shown):
tdc1_in_fpga_1_i,
tdc1_in_fpga_2_i,
tdc1_in_fpga_3_i,
tdc1_in_fpga_4_i,
tdc1_in_fpga_5_i
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) removed
4 block(s) optimized away
256 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block
"cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25" (ROM)
removed.
Loadless block
"cmp_tdc2/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25" (ROM)
removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)"
is sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
GND cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| VME_ADDR_DIR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_ADDR_OE_N_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_ADDR_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_AM_i<0> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<1> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<2> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<3> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<4> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<5> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AS_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_BERR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_DATA_DIR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DATA_OE_N_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DATA_b<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DS_n_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_DS_n_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_DTACK_OE_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DTACK_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_GA_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IACKIN_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IACKOUT_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IACK_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IRQ_n_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_LWORD_n_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_RETRY_OE_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_RETRY_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_RST_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_WRITE_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| carrier_onewire_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| clk_125m_gtp_n_i | IPAD | INPUT | | | | | | | |
| clk_125m_gtp_p_i | IPAD | INPUT | | | | | | | |
| clk_125m_pllref_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| clk_125m_pllref_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| fp_led_column_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pcb_ver_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| pll20dac_din_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll20dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll20dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_din_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| por_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_los_i | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_mod_def0_b | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_mod_def1_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| sfp_mod_def2_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| sfp_rxn_i | IPAD | INPUT | | | | | | | |
| sfp_rxp_i | IPAD | INPUT | | | | | | | |
| sfp_tx_disable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| sfp_tx_fault_i | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_txn_o | OPAD | OUTPUT | | | | | | | |
| sfp_txp_o | OPAD | OUTPUT | | | | | | | |
| tdc1_125m_clk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_125m_clk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| tdc1_address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| tdc1_pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_prsntm2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc1_rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| tdc1_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| tdc1_start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_125m_clk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_125m_clk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| tdc2_address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| tdc2_pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_prsntm2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc2_rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_scl_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc2_sda_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc2_start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| uart_rxd_i | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| uart_txd_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
hdl/top/spec/no_wrabbit/spec_tdc.ucf
View file @ 7f103f41
......@@ -330,8 +330,8 @@ NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#NET "spec_aux5_o" IOSTANDARD = "LVCMOS18";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
#NET "led_red_o" LOC = D5;
#NET "led_red_o" IOSTANDARD = "LVCMOS25";
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# False Path
......
hdl/top/spec/no_wrabbit/spec_tdc.vhd
View file @ 7f103f41
......@@ -585,12 +585,13 @@ begin
(g_width => 5000000)
port map
(clk_i => clk_125m,
rst_n_i => not(rst_125m),
rst_n_i => rst_125m_n,
pulse_i => irq_to_gn4124,
extended_o => led_red);
-- -- -- -- -- -- --
led_red_o <= led_red;
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
---------------------------------------------------------------------------------------------------
......
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