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FMC TDC 1ns 5cha - Gateware
Commit 8250f67c authored by penacoba's avatar penacoba
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Raw_timestamps version 


git-svn-id: http://svn.ohwr.org/fmc-tdc@53 85dfdc96-de2c-444c-878d-45b388be74a9
parent 757b8fff
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Showing with 269 additions and 83 deletions
hdl/spec/src/rtl/circular_buffer.vhd
View file @ 8250f67c
......@@ -121,8 +121,10 @@ begin
begin
if class_reset ='1' then
class_ack <= '0';
elsif class_stb ='1' and class_cyc ='1' and class_ack ='0' then
class_ack <= '1';
else
class_ack <= class_stb and class_cyc;
class_ack <= '0';
end if;
wait until class_clk ='1';
end process;
......
hdl/spec/src/rtl/data_engine.vhd
View file @ 8250f67c
......@@ -2,12 +2,16 @@
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : data polling engine (data_engine)
-- unit name : data managing engine (data_engine)
-- author : G. Penacoba
-- date : June 2011
-- version : Revision 1
-- description : engine polling data continuouly from the acam interface provided the FIFO is not
-- empty. acts as a wishbone master.
-- description : engine managing the configuration and acquisition modes of operation for the ACAM.
-- in acquisition mode: monitors permanently the Empty Flags of the ACAM iFIFOs
-- and reads timestamps accordingly.
-- when acquisition mode is inactive: allows the configuration and readback of ACAM
-- registers.
-- Acts as a wishbone master.
-- dependencies:
-- references :
-- modified by :
......@@ -15,8 +19,7 @@
----------------------------------------------------------------------------------------------------
-- last changes:
----------------------------------------------------------------------------------------------------
-- to do: REPLACE THE POLLING BY INTERRUPT FROM THE EMPTY SIGNALS. ADD RESET ACAM COMMAND
-- AND GET STATUS COMMAND
-- to do:
----------------------------------------------------------------------------------------------------
library IEEE;
......@@ -334,8 +337,8 @@ begin
end case;
end process;
config_adr: process -- process to generate the valid addresses for the ACAM registers
begin
config_adr: process -- process to generate the valid addresses
begin -- for the ACAM config registers
if reset ='1' then
config_adr_counter <= x"00";
......@@ -356,7 +359,6 @@ begin
wait until clk ='1';
end process;
data_config_decoding: process(acam_adr, engine_st, acam_config, reset_word)
begin
case acam_adr is
......@@ -393,7 +395,23 @@ begin
data_readback_decoding: process
begin
if acam_cyc ='1' and acam_stb ='1' and acam_ack ='1' and acam_we ='0' then
if reset ='1' then
acam_config_rdbk(0) <= (others =>'0');
acam_config_rdbk(1) <= (others =>'0');
acam_config_rdbk(2) <= (others =>'0');
acam_config_rdbk(3) <= (others =>'0');
acam_config_rdbk(4) <= (others =>'0');
acam_config_rdbk(5) <= (others =>'0');
acam_config_rdbk(6) <= (others =>'0');
acam_config_rdbk(7) <= (others =>'0');
acam_config_rdbk(8) <= (others =>'0');
acam_config_rdbk(9) <= (others =>'0');
acam_config_rdbk(10) <= (others =>'0');
acam_ififo1 <= (others =>'0');
acam_ififo2 <= (others =>'0');
acam_start01 <= (others =>'0');
elsif acam_cyc ='1' and acam_stb ='1' and acam_ack ='1' and acam_we ='0' then
if acam_adr= x"00" then
acam_config_rdbk(0) <= acam_data_rd;
end if;
......
hdl/spec/src/rtl/data_formatting.vhd
View file @ 8250f67c
......@@ -7,7 +7,7 @@
-- date : May 2011
-- version : Revision 1
-- description : formats the timestamp coming from the acam plus the coarse timing
-- plus the UTC time
-- plus the UTC time and writes it to the circular buffer
-- dependencies:
-- references :
-- modified by :
......@@ -27,19 +27,32 @@ use IEEE.numeric_std.all;
----------------------------------------------------------------------------------------------------
entity data_formatting is
generic(
g_width : integer :=32
g_span : integer :=32;
g_width : integer :=32
);
port(
acam_start01_i : in std_logic_vector(16 downto 0);
acam_timestamp_i : in std_logic_vector(28 downto 0);
acam_timestamp_valid_i : in std_logic;
-- wishbone master signals internal to the chip: interface with the circular buffer
ack_i : in std_logic;
dat_i : in std_logic_vector(4*g_width-1 downto 0);
adr_o : out std_logic_vector(g_span-1 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(4*g_width-1 downto 0);
stb_o : out std_logic;
we_o : out std_logic;
-- signals internal to the chip: interface with other modules
acam_timestamp1_i : in std_logic_vector(g_width-1 downto 0);
acam_timestamp1_valid_i : in std_logic;
acam_timestamp2_i : in std_logic_vector(g_width-1 downto 0);
acam_timestamp2_valid_i : in std_logic;
clk_i : in std_logic;
clear_dacapo_flag_i : in std_logic;
reset_i : in std_logic;
start_nb_offset_i : in std_logic_vector(g_width-1 downto 0);
utc_current_time_i : in std_logic_vector(g_width-1 downto 0);
full_timestamp_o : out std_logic_vector(3*g_width-1 downto 0);
full_timestamp_valid_o : out std_logic
wr_pointer_o : out std_logic_vector(g_width-1 downto 0)
);
end data_formatting;
......@@ -49,67 +62,178 @@ end data_formatting;
architecture rtl of data_formatting is
signal acam_channel : std_logic_vector(2 downto 0);
signal acam_fifo_ef : std_logic;
signal acam_fifo_lf : std_logic;
signal acam_fine_timestamp : std_logic_vector(16 downto 0);
signal acam_start01 : std_logic_vector(16 downto 0);
signal acam_timestamp : std_logic_vector(28 downto 0);
signal acam_timestamp_valid : std_logic;
signal acam_slope : std_logic;
signal acam_start_nb : std_logic_vector(7 downto 0);
signal acam_timestamp1 : std_logic_vector(g_width-1 downto 0);
signal acam_timestamp1_valid : std_logic;
signal acam_timestamp2 : std_logic_vector(g_width-1 downto 0);
signal acam_timestamp2_valid : std_logic;
signal clk : std_logic;
signal reset : std_logic;
signal start_nb_offset : std_logic_vector(g_width-1 downto 0);
signal utc_current_time : std_logic_vector(g_width-1 downto 0);
signal full_timestamp : std_logic_vector(3*g_width-1 downto 0);
signal full_timestamp_valid : std_logic;
signal full_timestamp : std_logic_vector(4*g_width-1 downto 0);
signal metadata : std_logic_vector(g_width-1 downto 0);
signal local_utc : std_logic_vector(g_width-1 downto 0);
signal coarse_time : std_logic_vector(g_width-1 downto 0);
signal fine_time : std_logic_vector(g_width-1 downto 0);
signal clear_dacapo_flag : std_logic;
signal dacapo_flag : std_logic;
signal wr_pointer : unsigned(g_width-1 downto 0);
signal reserved : std_logic_vector(2 downto 0):=(others=>'0');
signal u_start_nb_offset : unsigned(g_width-1 downto 0);
signal u_acam_start_nb : unsigned(7 downto 0);
signal start_nb : std_logic_vector(g_width-1 downto 0);
signal mem_ack : std_logic;
signal mem_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal mem_adr : std_logic_vector(g_span-1 downto 0);
signal mem_cyc : std_logic;
signal mem_data_wr : std_logic_vector(4*g_width-1 downto 0);
signal mem_stb : std_logic;
signal mem_we : std_logic;
--signal reserved : std_logic_vector(2 downto 0):=(others=>'0');
--signal u_start_nb_offset : unsigned(g_width-1 downto 0);
--signal u_acam_start_nb : unsigned(7 downto 0);
--signal start_nb : std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
full_timestamp_register: process
pushing_data_to_buffer: process
begin
if reset ='1' then
full_timestamp <= (others=>'0');
elsif acam_timestamp_valid ='1' then
-- mem_adr <= (others =>'0');
mem_cyc <= '0';
-- mem_data_wr <= (others =>'0');
mem_stb <= '0';
mem_we <= '0';
elsif acam_timestamp1_valid ='1' or acam_timestamp2_valid ='1' then
-- mem_adr <= std_logic_vector(wr_pointer);
mem_cyc <= '1';
-- mem_data_wr <= full_timestamp;
mem_stb <= '1';
mem_we <= '1';
elsif mem_ack ='1' then
-- mem_adr <= std_logic_vector(wr_pointer);
mem_cyc <= '0';
-- mem_data_wr <= full_timestamp;
mem_stb <= '0';
mem_we <= '0';
end if;
wait until clk ='1';
end process;
full_timestamp(95 downto 64) <= utc_current_time;
full_timestamp(63 downto 40) <= start_nb(23 downto 0);
full_timestamp(39 downto 23) <= acam_fine_timestamp;
full_timestamp(22 downto 6) <= acam_start01;
full_timestamp(5 downto 3) <= acam_channel;
full_timestamp(2 downto 0) <= reserved;
pointer_update: process
begin
if reset ='1' then
wr_pointer <= (others=>'0');
elsif mem_cyc ='1' and mem_stb ='1' and mem_we ='1' and mem_ack ='1' then
if wr_pointer = 127 then
wr_pointer <= (others=>'0');
else
wr_pointer <= wr_pointer + 1;
end if;
end if;
wait until clk ='1';
end process;
valid_onetick_signal: process
dacapo_flag_update: process
begin
full_timestamp_valid <= acam_timestamp_valid;
if reset ='1' then
dacapo_flag <= '0';
elsif clear_dacapo_flag ='1' then
dacapo_flag <= '0';
elsif wr_pointer = 127 then
dacapo_flag <= '1';
end if;
wait until clk ='1';
end process;
acam_data_slicing: process
begin
if reset ='1' then
acam_channel <= (others =>'0');
acam_fifo_ef <= '0';
acam_fifo_lf <= '0';
acam_fine_timestamp <= (others =>'0');
acam_slope <= '0';
acam_start_nb <= (others =>'0');
elsif acam_timestamp1_valid ='1' then
acam_channel <= "0" & acam_timestamp1(27 downto 26);
acam_fifo_ef <= acam_timestamp1(31);
acam_fifo_lf <= acam_timestamp1(29);
acam_fine_timestamp <= acam_timestamp1(16 downto 0);
acam_slope <= acam_timestamp1(17);
acam_start_nb <= acam_timestamp1(25 downto 18);
elsif acam_timestamp2_valid ='1' then
acam_channel <= "1" & acam_timestamp2(27 downto 26);
acam_fifo_ef <= acam_timestamp2(30);
acam_fifo_lf <= acam_timestamp2(28);
acam_fine_timestamp <= acam_timestamp2(16 downto 0);
acam_slope <= acam_timestamp2(17);
acam_start_nb <= acam_timestamp2(25 downto 18);
end if;
wait until clk ='1';
end process;
acam_start01 <= acam_start01_i;
acam_timestamp <= acam_timestamp_i;
acam_timestamp_valid <= acam_timestamp_valid_i;
metadata <= x"0000"
& "000" & acam_fifo_ef
& "000" & acam_fifo_lf
& "000" & acam_slope
& "0" & acam_channel;
local_utc <= utc_current_time;
coarse_time <= x"000000"
& acam_start_nb;
fine_time <= x"000"
& "000"
& acam_fine_timestamp;
full_timestamp(127 downto 96) <= metadata;
full_timestamp(95 downto 64) <= local_utc;
full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(31 downto 0) <= fine_time;
mem_adr <= std_logic_vector(wr_pointer);
mem_data_wr <= full_timestamp;
-- inputs
acam_timestamp1 <= acam_timestamp1_i;
acam_timestamp1_valid <= acam_timestamp1_valid_i;
acam_timestamp2 <= acam_timestamp2_i;
acam_timestamp2_valid <= acam_timestamp2_valid_i;
clk <= clk_i;
clear_dacapo_flag <= clear_dacapo_flag_i;
reset <= reset_i;
start_nb_offset <= start_nb_offset_i;
utc_current_time <= utc_current_time_i;
mem_ack <= ack_i;
mem_data_rd <= dat_i;
-- outputs
wr_pointer_o <= dacapo_flag & std_logic_vector(wr_pointer(g_width-4 downto 0)) & "00";
adr_o <= mem_adr;
cyc_o <= mem_cyc;
dat_o <= mem_data_wr;
stb_o <= mem_stb;
we_o <= mem_we;
full_timestamp_o <= full_timestamp;
full_timestamp_valid_o <= full_timestamp_valid;
u_start_nb_offset <= unsigned(start_nb_offset);
u_acam_start_nb <= unsigned(acam_timestamp(25 downto 18));
start_nb <= std_logic_vector(u_start_nb_offset + u_acam_start_nb);
-- u_start_nb_offset <= unsigned(start_nb_offset);
-- u_acam_start_nb <= unsigned(acam_timestamp(25 downto 18));
-- start_nb <= std_logic_vector(u_start_nb_offset + u_acam_start_nb);
acam_fine_timestamp <= acam_timestamp(16 downto 0);
acam_channel <= acam_timestamp(28 downto 26);
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/reg_ctrl.vhd
View file @ 8250f67c
......@@ -48,8 +48,6 @@ entity reg_ctrl is
-- control signals for interface with other internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
read_acam_status_o : out std_logic;
......@@ -57,6 +55,9 @@ entity reg_ctrl is
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
clear_dacapo_flag_o : out std_logic;
-- configuration registers from and for the ACAM and the modules of the TDC core
acam_config_rdbk_i : in config_vector;
......@@ -66,6 +67,8 @@ entity reg_ctrl is
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
current_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
core_status_i : in std_logic_vector(g_width-1 downto 0);
wr_pointer_i : in std_logic_vector(g_width-1 downto 0);
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
......@@ -118,6 +121,8 @@ signal acam_ififo2 : std_logic_vector(g_width-1 downto 0);
signal acam_start01 : std_logic_vector(g_width-1 downto 0);
signal current_utc : std_logic_vector(g_width-1 downto 0);
signal irq_code : std_logic_vector(g_width-1 downto 0);
signal core_status : std_logic_vector(g_width-1 downto 0);
signal wr_pointer : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
......@@ -307,6 +312,8 @@ begin
retrig_freq when x"25",
current_utc when x"26",
irq_code when x"27",
core_status when x"28",
wr_pointer when x"29",
x"FFFFFFFF" when others;
-- inputs from other blocks
......@@ -326,6 +333,8 @@ begin
acam_ififo2 <= acam_ififo2_i;
acam_start01 <= acam_start01_i;
irq_code <= irq_code_i;
core_status <= core_status_i;
wr_pointer <= wr_pointer_i;
-- outputs to other blocks
reg_ack_o <= reg_ack;
......@@ -343,6 +352,7 @@ begin
reset_acam_o <= control_register(8);
load_utc_o <= control_register(9);
load_tdc_config_o <= control_register(10);
clear_dacapo_flag_o <= control_register(11);
starting_utc_o <= starting_utc;
clk_freq_o <= clk_freq;
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ 8250f67c
......@@ -162,19 +162,32 @@ architecture rtl of top_tdc is
component data_formatting
generic(
g_span : integer :=32;
g_width : integer :=32
);
port(
acam_start01_i : in std_logic_vector(16 downto 0);
acam_timestamp_i : in std_logic_vector(27 downto 0);
acam_timestamp_valid_i : in std_logic;
-- wishbone master signals internal to the chip: interface with the circular buffer
ack_i : in std_logic;
dat_i : in std_logic_vector(4*g_width-1 downto 0);
adr_o : out std_logic_vector(g_span-1 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(4*g_width-1 downto 0);
stb_o : out std_logic;
we_o : out std_logic;
-- signals internal to the chip: interface with other modules
acam_timestamp1_i : in std_logic_vector(g_width-1 downto 0);
acam_timestamp1_valid_i : in std_logic;
acam_timestamp2_i : in std_logic_vector(g_width-1 downto 0);
acam_timestamp2_valid_i : in std_logic;
clk_i : in std_logic;
clear_dacapo_flag_i : in std_logic;
reset_i : in std_logic;
start_nb_offset_i : in std_logic_vector(g_width-1 downto 0);
utc_current_time_i : in std_logic_vector(g_width-1 downto 0);
full_timestamp_o : out std_logic_vector(3*g_width-1 downto 0);
full_timestamp_valid_o : out std_logic
wr_pointer_o : out std_logic_vector(g_width-1 downto 0)
);
end component;
......@@ -371,15 +384,16 @@ architecture rtl of top_tdc is
-- control signals for interface with other internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
reset_acam_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
clear_dacapo_flag_o : out std_logic;
-- configuration registers from and for the ACAM and the modules of the TDC core
acam_config_rdbk_i : in config_vector;
......@@ -387,8 +401,10 @@ architecture rtl of top_tdc is
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
current_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
current_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
core_status_i : in std_logic_vector(g_width-1 downto 0);
wr_pointer_i : in std_logic_vector(g_width-1 downto 0);
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
......@@ -524,14 +540,15 @@ signal acam_timestamp1 : std_logic_vector(g_width-1 downto 0);
signal acam_timestamp1_valid : std_logic;
signal acam_timestamp2 : std_logic_vector(g_width-1 downto 0);
signal acam_timestamp2_valid : std_logic;
signal full_timestamp : std_logic_vector(3*g_width-1 downto 0);
signal full_timestamp_valid : std_logic;
signal clear_dacapo_flag : std_logic;
signal core_status : std_logic_vector(g_width-1 downto 0);
signal general_reset : std_logic;
signal one_hz_p : std_logic;
signal start_nb_offset : std_logic_vector(g_width-1 downto 0);
signal start_trig : std_logic;
signal start_timer_reg : std_logic_vector(7 downto 0);
signal utc_current_time : std_logic_vector(g_width-1 downto 0);
signal wr_pointer : std_logic_vector(g_width-1 downto 0);
signal acm_adr : std_logic_vector(g_span-1 downto 0);
signal acm_cyc : std_logic;
......@@ -653,22 +670,33 @@ begin
start_trig_o => open
);
-- data_formatting_block: data_formatting
-- generic map(
-- g_width => g_width
-- )
-- port map(
-- acam_start01_i => acam_start01,
-- acam_timestamp_i => acam_timestamp,
-- acam_timestamp_valid_i => acam_timestamp_valid,
-- clk_i => clk,
-- reset_i => general_reset,
-- start_nb_offset_i => start_nb_offset,
-- utc_current_time_i => utc_current_time,
--
-- full_timestamp_o => full_timestamp,
-- full_timestamp_valid_o => full_timestamp_valid
-- );
data_formatting_block: data_formatting
generic map(
g_span => g_span,
g_width => g_width
)
port map(
ack_i => mem_class_ack,
dat_i => mem_class_data_rd,
adr_o => mem_class_adr,
cyc_o => mem_class_cyc,
dat_o => mem_class_data_wr,
stb_o => mem_class_stb,
we_o => mem_class_we,
acam_timestamp1_i => acam_timestamp1,
acam_timestamp1_valid_i => acam_timestamp1_valid,
acam_timestamp2_i => acam_timestamp2,
acam_timestamp2_valid_i => acam_timestamp2_valid,
clk_i => clk,
clear_dacapo_flag_i => clear_dacapo_flag,
reset_i => general_reset,
start_nb_offset_i => start_nb_offset,
utc_current_time_i => utc_current_time,
wr_pointer_o => wr_pointer
);
acam_timing_block: acam_timecontrol_interface
generic map(
......@@ -835,8 +863,6 @@ begin
-- control signals for interface with other application internal modules
activate_acq_o => activate_acq,
deactivate_acq_o => deactivate_acq,
load_utc_o => load_utc,
load_tdc_config_o => load_tdc_config,
load_acam_config_o => load_acam_config,
read_acam_config_o => read_acam_config,
read_acam_status_o => read_acam_status,
......@@ -844,8 +870,11 @@ begin
read_ififo2_o => read_ififo2,
read_start01_o => read_start01,
reset_acam_o => reset_acam,
load_utc_o => load_utc,
load_tdc_config_o => load_tdc_config,
clear_dacapo_flag_o => clear_dacapo_flag,
-- configuration registers for the modules of the TDC core
-- configuration registers for the ACAM and the modules of the TDC core
acam_config_rdbk_i => acam_config_rdbk,
acam_status_i => acam_status,
acam_ififo1_i => acam_ififo1,
......@@ -853,6 +882,8 @@ begin
acam_start01_i => acam_start01,
current_utc_i => current_utc,
irq_code_i => irq_code,
core_status_i => core_status,
wr_pointer_i => wr_pointer,
acam_config_o => acam_config,
starting_utc_o => starting_utc,
......@@ -1081,6 +1112,7 @@ begin
tdc_led_trig5_o <= tdc_led_trig5;
-- these will evolve as we implement all the features
irq_p <= dma_irq(0) or dma_irq(1);
pulse_delay <= x"00000001";
window_delay <= x"00000002";
mute_inputs_o <= '1';
......
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