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FMC TDC 1ns 5cha - Gateware
Commit 84739413 authored by egousiou's avatar egousiou
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changes for new version (v2) of TDC mezz 

git-svn-id: http://svn.ohwr.org/fmc-tdc@77 85dfdc96-de2c-444c-878d-45b388be74a9
parent d34e1405
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Showing with 195 additions and 230 deletions
hdl/spec/src/rtl/acam_databus_interface.vhd
View file @ 84739413
......@@ -24,7 +24,7 @@
-- | |___CSn_______| |___cyc______| | |
-- | ACAM |___OEn_______| acam_ |___we_______| data_ | |
-- | |___EF________| databus_ |___ack______| engine | |
-- | |___LF________| interface |___adr______| | |
-- | | | interface |___adr______| | |
-- | |___ADR_______| |___datI_____| | |
-- | |___DatabusIO_| |___datO_____| | |
-- |___________| |____________| |___________| |
......@@ -85,8 +85,6 @@ entity acam_databus_interface is
-- Signals from the ACAM chip
ef1_i : in std_logic; -- FIFO1 empty flag
ef2_i : in std_logic; -- FIFO1 empty flag
lf1_i : in std_logic; -- load flag, not used
lf2_i : in std_logic; -- load flag, not used
data_bus_io : inout std_logic_vector(27 downto 0);
......@@ -114,7 +112,7 @@ entity acam_databus_interface is
-- Signals to the data_engine unit
ack_o : out std_logic; -- WISHBONE ack
dat_o : out std_logic_vector(31 downto 0)); -- ef1 & ef2 & lf1 & lf2 & 28 bits acam data_bus_io
dat_o : out std_logic_vector(31 downto 0)); -- ef1 & ef2 & 0 & 0 & 28 bits acam data_bus_io
end acam_databus_interface;
......@@ -128,7 +126,7 @@ architecture rtl of acam_databus_interface is
type t_acam_interface is (IDLE, RD_START, RD_FETCH, RD_ACK, WR_START, WR_PUSH, WR_ACK);
signal acam_data_st, nxt_acam_data_st : t_acam_interface;
signal ef1_synch, ef2_synch, lf1_synch, lf2_synch : std_logic_vector(1 downto 0);
signal ef1_synch, ef2_synch : std_logic_vector(1 downto 0);
signal ack, cs, cs_extend, rd, rd_extend, wr, wr_extend, wr_remove : std_logic;
......@@ -148,13 +146,9 @@ begin
if rst_i ='1' then
ef1_synch <= (others =>'1');
ef2_synch <= (others =>'1');
lf1_synch <= (others =>'0');
lf2_synch <= (others =>'0');
else
ef1_synch <= ef1_i & ef1_synch(1);
ef2_synch <= ef2_i & ef2_synch(1);
lf1_synch <= lf1_i & lf1_synch(1);
lf2_synch <= lf2_i & lf2_synch(1);
end if;
end if;
end process;
......@@ -298,8 +292,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ack_o <= ack;
-- to the 28 bits databus output we add the ef and lf flags to arrive to a 32 bits word
dat_o <= ef1_synch(0) & ef2_synch(0) & lf1_synch(0) & lf2_synch(0) & data_bus_io;
-- to the 28 bits databus output we add the ef flags to arrive to a 32 bits word
dat_o <= ef1_synch(0) & ef2_synch(0) & "00" & data_bus_io;
......
hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ 84739413
......@@ -184,7 +184,7 @@ begin
total_delay <= std_logic_vector(unsigned(window_delay_i)+constant_delay);
start_pulse_from_fpga: process (clk_i) -- start pulse in the middle of the
start_pulse_from_fpga: process (clk_i) -- start pulse in the middle of the
begin -- de-assertion window of StartDisable
if rising_edge (clk_i) then
if rst_i ='1' then
......@@ -201,7 +201,7 @@ begin
-- Synchronization of the activate_acq_p with the acam_refclk_i
-- Synchronization of the activate_acq_p with the acam_refclk_p_i
ready_to_trigger: process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -220,7 +220,7 @@ begin
actual_trigger_received: process (clk_i) -- signal needed to exclude the generation of
actual_trigger_received: process (clk_i) -- signal needed to exclude the generation of
begin -- the start_from_fpga_o after a general rst_i
if rising_edge (clk_i) then
if rst_i ='1' then
......
hdl/spec/src/rtl/clks_rsts_manager.vhd
View file @ 84739413
......@@ -27,7 +27,7 @@
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.2 EG Added DFFs to the pll_sdi_o, pll_cs_o outputs |
-- Changed completely the internal reset generation; now it depends |
-- on the pll_ld activation |
-- on the pll_status activation |
-- General revamping, comments added, signals renamed |
-- 05/2012 v0.3 EG Added logic for DAC configuration |
-- |
......@@ -75,14 +75,13 @@ entity clks_rsts_manager is
(spec_clk_i : in std_logic; -- 20 MHz OSC on SPEC board
-- Clock signals from the PLL
acam_refclk_i : in std_logic; -- 31.25 MHz clock generated by the PLL, clock of ACAM
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock generated by the PLL, clock of ACAM
acam_refclk_n_i : in std_logic; -- 31.25 MHz clock generated by the PLL, clock of ACAM
tdc_clk_p_i : in std_logic; -- 125 MHz clock generated by the PLL, clock of all other TDC core logic
tdc_clk_n_i : in std_logic;
-- Other signals from the PLL
pll_ld_i : in std_logic; -- PLL lock detect
pll_refmon_i : in std_logic; -- not used
pll_status_i : in std_logic; -- not used
pll_status_i : in std_logic; -- PLL lock detect
pll_sdo_i : in std_logic; -- not used
-- Signal from the GNUM
......@@ -105,12 +104,12 @@ entity clks_rsts_manager is
pll_sclk_o : out std_logic; -- SPI clock
-- Signal to the one_hz_gen and acam_timecontrol_interface units
acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk_i rising edge
acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk_p_i rising edge
-- Signals to the leds_manager unit
gnum_rst_o : out std_logic; -- GENUM reset synched with 20 MHz clock
spec_clk_o : out std_logic; -- 20 MHz clock
pll_ld_o : out std_logic);-- PLL lock detect synched with 20 MHz clock
pll_status_o : out std_logic);-- PLL lock detect synched with 20 MHz clock
end clks_rsts_manager;
......@@ -142,7 +141,7 @@ architecture rtl of clks_rsts_manager is
constant REG_014 : t_byte := x"09";
constant REG_015 : t_byte := x"00";
constant REG_016 : t_byte := x"04";
constant REG_017 : t_byte := x"00";
constant REG_017 : t_byte := x"B4"; -- PLL_STATUS
constant REG_018 : t_byte := x"07";
constant REG_019 : t_byte := x"00";
constant REG_01A : t_byte := x"00";
......@@ -172,7 +171,7 @@ architecture rtl of clks_rsts_manager is
constant REG_0F4 : t_byte := x"0A";
constant REG_0F5 : t_byte := x"0A";
constant REG_140 : t_byte := x"4A";
constant REG_140 : t_byte := x"42"; -----REF_CLK
constant REG_141 : t_byte := x"5A";
constant REG_142 : t_byte := x"43";
constant REG_143 : t_byte := x"42";
......@@ -225,11 +224,11 @@ architecture rtl of clks_rsts_manager is
signal pll_byte_index : integer range nb_of_reg-1 downto 0;
signal pll_cs_n, dac_cs_n : std_logic;
-- Synchronizers
signal pll_ld_synch, internal_rst_synch, gnum_rst_synch : std_logic_vector (1 downto 0);
signal pll_status_synch, internal_rst_synch, gnum_rst_synch : std_logic_vector (1 downto 0);
signal acam_refclk_synch, send_dac_word_p_synch : std_logic_vector (2 downto 0);
-- Clock buffers
signal spec_clk_buf, tdc_clk_buf : std_logic;
signal sclk, spec_clk, tdc_clk : std_logic;
signal spec_clk_buf, tdc_clk_buf, acam_refclk_buf : std_logic;
signal sclk, spec_clk, tdc_clk, acam_refclk : std_logic;
-- Resets
signal rst, internal_rst, gnum_rst : std_logic;
......@@ -277,6 +276,22 @@ begin
-- -- -- -- -- -- -- --
spec_clk_o <= spec_clk;
---------------------------------------------------------------------------------------------------
acam_refclk31M25_ibuf : IBUFDS
generic map
(DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map
(O => acam_refclk,
I => acam_refclk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => acam_refclk_n_i);-- Diff_n buffer input (connect directly to top-level port)
--acam_refclk31M25_gbuf : BUFG
--port map
-- (O => acam_refclk,
-- I => acam_refclk_buf);
---------------------------------------------------------------------------------------------------
-- General Internal Reset --
......@@ -299,26 +314,26 @@ begin
gnum_rst_o <= gnum_rst_synch(1);
---------------------------------------------------------------------------------------------------
-- Synchronous process PLL_LD_synchronizer: Synchronization of the pll_ld_i input to the spec_clk,
-- using a set of 2 registers.
PLL_LD_synchronizer: process (spec_clk)
-- Synchronous process pll_status_synchronizer: Synchronization of the pll_status_i input to the
-- spec_clk, using a set of 2 registers.
pll_status_synchronizer: process (spec_clk)
begin
if rising_edge (spec_clk) then
if gnum_rst = '1' then
pll_ld_synch <= (others => '0');
pll_status_synch <= (others => '0');
else
pll_ld_synch <= pll_ld_synch(0) & pll_ld_i;
pll_status_synch <= pll_status_synch(0) & pll_status_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- --
pll_ld_o <= pll_ld_synch(1);
pll_status_o <= pll_status_synch(1);
---------------------------------------------------------------------------------------------------
-- Synchronous process Internal_rst_generation: Generation of a reset signal for as long as the PLL
-- is not locked. As soon as the pll_ld is received the internal reset is released.
-- Note that the level of the pll_ld signal rather than its rising edge is used, as in the case of
-- a gnum_rst during operation with the pll already locked the pll_ld will remain active and no
-- is not locked. As soon as the pll_status is received the internal reset is released.
-- Note that the level of the pll_status signal rather than its rising edge is used, as in the case of
-- a gnum_rst during operation with the pll already locked the pll_status will remain active and no
-- edge will appear.
Internal_rst_generator: process (spec_clk)
begin
......@@ -326,7 +341,7 @@ begin
if gnum_rst = '1' then
rst <= '1';
else
if pll_ld_synch(1) = '1' then
if pll_status_synch(1) = '1' then
rst <= '0';
else
rst <= '1';
......@@ -358,7 +373,7 @@ begin
if internal_rst_synch(1) = '1' then
acam_refclk_synch <= (others => '0');
else
acam_refclk_synch <= acam_refclk_synch(1 downto 0) & acam_refclk_i;
acam_refclk_synch <= acam_refclk_synch(1 downto 0) & acam_refclk;
end if;
end if;
end process;
......
hdl/spec/src/rtl/data_engine.vhd
View file @ 84739413
......@@ -108,7 +108,7 @@ entity data_engine is
-- Signals from the acam_databus_interface unit: WISHBONE master
acam_ack_i : in std_logic; -- WISHBONE ack
acam_dat_i : in std_logic_vector(31 downto 0); -- tstamps or rdbk regs
-- includes ef1 & ef2 & lf1 & lf2 & 28 bits acam data_bus_io
-- includes ef1 & ef2 & 0 & 0 & 28 bits acam data_bus_io
-- OUTPUTS
......@@ -127,8 +127,8 @@ entity data_engine is
acam_start01_o : out std_logic_vector(31 downto 0);-- keeps value read from ACAM reg 10
-- Signals to the data_formatting unit:
acam_tstamp1_o : out std_logic_vector(31 downto 0);-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO1
acam_tstamp2_o : out std_logic_vector(31 downto 0);-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO2
acam_tstamp1_o : out std_logic_vector(31 downto 0);-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO1
acam_tstamp2_o : out std_logic_vector(31 downto 0);-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
acam_tstamp1_ok_p_o : out std_logic; -- indication of a valid tstamp1
acam_tstamp2_ok_p_o : out std_logic);-- indication of a valid tstamp2
......
hdl/spec/src/rtl/data_formatting.vhd
View file @ 84739413
......@@ -73,10 +73,10 @@ entity data_formatting is
-- Signals from the data_engine unit
acam_tstamp1_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO1
-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO1
acam_tstamp1_ok_p_i : in std_logic; -- tstamp2 valid indicator
acam_tstamp2_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO2
-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
acam_tstamp2_ok_p_i : in std_logic; -- tstamp2 valid indicator
-- Signals from the reg_ctrl unit
......@@ -122,7 +122,7 @@ architecture rtl of data_formatting is
constant c_MULTIPLY_BY_SIXTEEN : std_logic_vector(3 downto 0) := x"0";
-- ACAM timestamp fields
signal acam_channel : std_logic_vector(2 downto 0);
signal acam_slope, acam_fifo_ef, acam_fifo_lf : std_logic;
signal acam_slope, acam_fifo_ef : std_logic;
signal acam_fine_timestamp : std_logic_vector(16 downto 0);
signal acam_start_nb : std_logic_vector(7 downto 0);
-- timestamp manipulations
......@@ -248,8 +248,8 @@ begin
-- [25:18] Start number /
-- [27:26] Channel Code /
-- [28] lf2 \
-- [29] lf1 \ empty and load flags (added by the acam_databus_interface unit)
-- [28] 0 \
-- [29] 0 \ empty and load flags (added by the acam_databus_interface unit)
-- [30] ef2 /
-- [31] ef1 /
......@@ -265,7 +265,7 @@ begin
-- [95:64] Local UTC time coming from the one_hz_generator;
-- each bit represents 1s
-- [127:96] Metadata for each timestamp: "00..00" & lf & ef & Slope & Channel
-- [127:96] Metadata for each timestamp: "00..00" & 0 & ef & Slope & Channel
tstamp_formatting: process (clk_i)
begin
......@@ -273,7 +273,6 @@ begin
if rst_i ='1' then
acam_channel <= (others => '0');
acam_fifo_ef <= '0';
acam_fifo_lf <= '0';
acam_fine_timestamp <= (others => '0');
acam_slope <= '0';
acam_start_nb <= (others => '0');
......@@ -281,7 +280,6 @@ begin
elsif acam_tstamp1_ok_p_i = '1' then
acam_channel <= "0" & acam_tstamp1_i(27 downto 26);
acam_fifo_ef <= acam_tstamp1_i(31);
acam_fifo_lf <= acam_tstamp1_i(29);
acam_fine_timestamp <= acam_tstamp1_i(16 downto 0);
acam_slope <= acam_tstamp1_i(17);
acam_start_nb <= acam_tstamp1_i(25 downto 18);
......@@ -289,7 +287,6 @@ begin
elsif acam_tstamp2_ok_p_i ='1' then
acam_channel <= "1" & acam_tstamp2_i(27 downto 26);
acam_fifo_ef <= acam_tstamp2_i(30);
acam_fifo_lf <= acam_tstamp2_i(28);
acam_fine_timestamp <= acam_tstamp2_i(16 downto 0);
acam_slope <= acam_tstamp2_i(17);
acam_start_nb <= acam_tstamp2_i(25 downto 18);
......
hdl/spec/src/rtl/leds_manager.vhd
View file @ 84739413
......@@ -33,7 +33,7 @@
-- TDC LED 4 orange: Channel 3 terminatio enable |
-- TDC LED 5 orange: Channel 4 terminatio enable |
-- TDC LED 6 orange: Channel 5 terminatio enable |
-- SPEC LED 1 green : PLL lock detect |
-- SPEC LED 1 green : PLL status (DLD) |
-- SPEC LED 2 red : division of the 20 MHz clock |
-- |
-- There are also 4 LEDs and 2 buttons on the PCB of the SPEC carrier: |
......@@ -98,7 +98,7 @@ entity leds_manager is
internal_rst_i : in std_logic; -- core internal reset, synched with 125 MHz clk
-- Signal from the PLL
pll_ld_i : in std_logic; -- PLL lock detect
pll_status_i : in std_logic; -- PLL lock detect
-- Signals from the buttons on the SPEC PCB
spec_aux_butt_1_i : in std_logic; -- SPEC PCB button 1 (PB1)
......@@ -192,7 +192,7 @@ begin
---------------------------------------------------------------------------------------------------
-- SPEC FRONT PANEL LED 1 --
---------------------------------------------------------------------------------------------------
spec_led_green_o <= pll_ld_i;
spec_led_green_o <= pll_status_i;
---------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/tdc_core_pkg.vhd
View file @ 84739413
......@@ -487,14 +487,13 @@ package tdc_core_pkg is
(nb_of_reg : integer := 68);
port
(spec_clk_i : in std_logic;
acam_refclk_i : in std_logic;
acam_refclk_p_i : in std_logic;
acam_refclk_n_i : in std_logic;
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
rst_n_a_i : in std_logic;
pll_ld_i : in std_logic;
pll_refmon_i : in std_logic;
pll_sdo_i : in std_logic;
pll_status_i : in std_logic;
pll_sdo_i : in std_logic;
send_dac_word_p_i : in std_logic;
dac_word_i : in std_logic_vector(23 downto 0);
----------------------------------------------------------------------
......@@ -507,7 +506,7 @@ package tdc_core_pkg is
pll_dac_sync_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
pll_ld_o : out std_logic);
pll_status_o : out std_logic);
----------------------------------------------------------------------
end component;
......@@ -522,7 +521,7 @@ package tdc_core_pkg is
clk_125mhz_i : in std_logic;
gnum_rst_i : in std_logic;
internal_rst_i : in std_logic;
pll_ld_i : in std_logic;
pll_status_i : in std_logic;
spec_aux_butt_1_i : in std_logic;
spec_aux_butt_2_i : in std_logic;
one_hz_p_i : in std_logic;
......@@ -549,8 +548,6 @@ package tdc_core_pkg is
port
(ef1_i : in std_logic;
ef2_i : in std_logic;
lf1_i : in std_logic; -- not used i think
lf2_i : in std_logic; -- not used i think
data_bus_io : inout std_logic_vector(27 downto 0);
clk_i : in std_logic;
rst_i : in std_logic;
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ 84739413
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