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FMC TDC 1ns 5cha - Gateware
Commit 8d74d3fa authored by penacoba's avatar penacoba
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Top reorganized, and outputs for the Acam properly registered. 


git-svn-id: http://svn.ohwr.org/fmc-tdc@40 85dfdc96-de2c-444c-878d-45b388be74a9
parent 552710a7
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hdl/spec/src/rtl/acam_databus_interface.vhd
View file @ 8d74d3fa
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
-- modified by : -- modified by :
-- --
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- last changes: -- last changes: Added registers for the outputs.
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- to do: -- to do:
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
...@@ -134,8 +134,8 @@ begin ...@@ -134,8 +134,8 @@ begin
when rd_ack => when rd_ack =>
ack <= '1'; ack <= '1';
cs <= '1'; cs <= '0';
rd <= '1'; rd <= '0';
wr <= '0'; wr <= '0';
nxt_acam_data_st <= idle; nxt_acam_data_st <= idle;
...@@ -150,9 +150,9 @@ begin ...@@ -150,9 +150,9 @@ begin
when write => when write =>
ack <= '0'; ack <= '0';
cs <= '1'; cs <= '0';
rd <= '0'; rd <= '0';
wr <= '1'; wr <= '0';
nxt_acam_data_st <= wr_ack; nxt_acam_data_st <= wr_ack;
...@@ -196,10 +196,22 @@ begin ...@@ -196,10 +196,22 @@ begin
-- outputs to the ACAM -- outputs to the ACAM
address_o <= adr(3 downto 0); address_o <= adr(3 downto 0);
cs_n_o <= not(cs);
output_registers: process
begin
if reset ='1' then
cs_n_o <= '1';
rd_n_o <= '1';
wr_n_o <= '1';
else
cs_n_o <= not(cs);
rd_n_o <= not(rd);
wr_n_o <= not(wr);
end if;
wait until clk ='1';
end process;
oe_n_o <= '1'; oe_n_o <= '1';
rd_n_o <= not(rd);
wr_n_o <= not(wr);
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ 8d74d3fa
...@@ -26,24 +26,26 @@ use IEEE.numeric_std.all; ...@@ -26,24 +26,26 @@ use IEEE.numeric_std.all;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
entity acam_timecontrol_interface is entity acam_timecontrol_interface is
generic( generic(
g_width : integer :=32 g_width : integer :=32
); );
port( port(
-- signals external to the chip: interface with acam -- signals external to the chip: interface with acam
err_flag_i : in std_logic; err_flag_i : in std_logic;
int_flag_i : in std_logic; int_flag_i : in std_logic;
start_dis_o : out std_logic; start_dis_o : out std_logic;
start_from_fpga_o : out std_logic; start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic; stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
clk_i : in std_logic; clk_i : in std_logic;
start_trig_i : in std_logic; start_trig_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
acam_errflag_p_o : out std_logic; acam_rise_errflag_p_o : out std_logic;
acam_intflag_p_o : out std_logic acam_fall_errflag_p_o : out std_logic;
acam_rise_intflag_p_o : out std_logic;
acam_fall_intflag_p_o : out std_logic
); );
end acam_timecontrol_interface; end acam_timecontrol_interface;
...@@ -67,17 +69,19 @@ architecture rtl of acam_timecontrol_interface is ...@@ -67,17 +69,19 @@ architecture rtl of acam_timecontrol_interface is
); );
end component; end component;
signal clk : std_logic; signal clk : std_logic;
signal counter_reset : std_logic; signal counter_reset : std_logic;
signal start_trig : std_logic; signal start_trig : std_logic;
signal reset : std_logic; signal reset : std_logic;
signal s_int_flag : unsigned(2 downto 0); signal s_int_flag : unsigned(2 downto 0);
signal s_err_flag : unsigned(2 downto 0); signal s_err_flag : unsigned(2 downto 0);
signal start_dis : std_logic; signal start_dis : std_logic;
signal start_from_fpga : std_logic; signal start_from_fpga : std_logic;
signal start_window : std_logic; signal start_window : std_logic;
signal window_inverted : std_logic; signal start_window_reg : unsigned(2 downto 0);
signal start_window_edge : std_logic;
signal window_inverted : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
...@@ -106,24 +110,17 @@ begin ...@@ -106,24 +110,17 @@ begin
wait until clk ='1'; wait until clk ='1';
end process; end process;
acam_errflag_p_o <= not(s_err_flag(1)) and s_err_flag(0); acam_fall_errflag_p_o <= not(s_err_flag(1)) and s_err_flag(0);
acam_intflag_p_o <= not(s_int_flag(1)) and s_int_flag(0); acam_rise_errflag_p_o <= s_err_flag(1) and not(s_err_flag(0));
acam_fall_intflag_p_o <= not(s_int_flag(1)) and s_int_flag(0);
acam_rise_intflag_p_o <= s_int_flag(1) and not(s_int_flag(0));
-- generation of the window allowing the start: -- generation of the window allowing the start:
-- every second an external start retrigger is generated by the -- every second an external start retrigger is generated by the
-- rising edge of the ref_clk -- rising edge of the ref_clk
start_disable_control: process
begin
if reset ='1' then
start_dis <='1';
else
start_dis <= not(start_window);
end if;
wait until clk ='1';
end process;
window_counter: incr_counter window_counter: incr_counter
generic map( generic map(
width => g_width width => g_width
...@@ -139,18 +136,52 @@ begin ...@@ -139,18 +136,52 @@ begin
); );
start_window <= not(window_inverted); start_window <= not(window_inverted);
start_disable_control: process
begin
if reset ='1' then
start_dis <='1';
else
start_dis <= not(start_window);
end if;
wait until clk ='1';
end process;
start_pulse_fitter: process
begin
if reset ='1' then
start_window_reg <= (others=>'0');
else
start_window_reg <= shift_right(start_window_reg,1);
start_window_reg(2) <= start_window;
end if;
wait until clk ='1';
end process;
start_pulse: process
begin
if reset ='1' then
start_from_fpga <= '0';
elsif start_window_edge ='1' then
start_from_fpga <= '1';
else
start_from_fpga <= '0';
end if;
wait until clk ='1';
end process;
counter_reset <= reset or start_trig; counter_reset <= reset or start_trig;
start_from_fpga <= start_trig; start_window_edge <= start_window_reg(2) and not(start_window_reg(1)) and not(start_window_reg(0));
-- inputs -- inputs
clk <= clk_i; clk <= clk_i;
start_trig <= start_trig_i;
reset <= reset_i; reset <= reset_i;
start_trig <= start_trig_i;
-- outputs -- outputs
start_dis_o <= start_dis; start_dis_o <= start_dis;
stop_dis_o <= '0';
start_from_fpga_o <= start_from_fpga; start_from_fpga_o <= start_from_fpga;
stop_dis_o <= '0';
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/data_engine.vhd
View file @ 8d74d3fa
...@@ -34,10 +34,11 @@ entity data_engine is ...@@ -34,10 +34,11 @@ entity data_engine is
port( port(
-- wishbone master signals internal to the chip: interface with other modules -- wishbone master signals internal to the chip: interface with other modules
ack_i : in std_logic; ack_i : in std_logic;
dat_i : in std_logic_vector(31 downto 0); dat_i : in std_logic_vector(g_width-1 downto 0);
adr_o : out std_logic_vector(19 downto 0);
cyc_o : out std_logic; cyc_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0); dat_o : out std_logic_vector(g_width-1 downto 0);
stb_o : out std_logic; stb_o : out std_logic;
we_o : out std_logic; we_o : out std_logic;
...@@ -59,17 +60,39 @@ end data_engine; ...@@ -59,17 +60,39 @@ end data_engine;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
architecture rtl of data_engine is architecture rtl of data_engine is
type engine_state_ty is (wr_config, rest_wr, rd_timestamp, rest_rd); type engine_state_ty is (idle, wr_config, rest_wr, rd_timestamp, rest_rd);
signal engine_st, nxt_engine_st : engine_state_ty; signal engine_st, nxt_engine_st : engine_state_ty;
signal ef1 : std_logic; signal ef1 : std_logic;
signal ef2 : std_logic; signal ef2 : std_logic;
signal clk : std_logic;
signal reset : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
begin begin
data_engine_seq_fsm: process
begin
if reset ='1' then
engine_st <= idle;
else
engine_st <= nxt_engine_st;
end if;
wait until clk ='1';
end process;
-- data_engine_comb_fsm: process
-- begin
-- case engine_st is
-- when waiting =>
--
-- inputs
clk <= clk_i;
reset <= reset_i;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/start_retrigger_control.vhd
View file @ 8d74d3fa
...@@ -30,16 +30,17 @@ use IEEE.numeric_std.all; ...@@ -30,16 +30,17 @@ use IEEE.numeric_std.all;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
entity start_retrigger_control is entity start_retrigger_control is
generic( generic(
g_width : integer :=32 g_width : integer :=32
); );
port( port(
acam_intflag_p_i : in std_logic; acam_rise_intflag_p_i : in std_logic;
clk_i : in std_logic; acam_fall_intflag_p_i : in std_logic;
one_hz_p_i : in std_logic; clk_i : in std_logic;
reset_i : in std_logic; one_hz_p_i : in std_logic;
reset_i : in std_logic;
start_nb_offset_o : out std_logic_vector(g_width-1 downto 0); start_nb_offset_o : out std_logic_vector(g_width-1 downto 0);
start_trig_o : out std_logic start_trig_o : out std_logic
); );
end start_retrigger_control; end start_retrigger_control;
...@@ -63,15 +64,18 @@ architecture rtl of start_retrigger_control is ...@@ -63,15 +64,18 @@ architecture rtl of start_retrigger_control is
); );
end component; end component;
signal acam_intflag_p : std_logic; signal acam_fall_intflag_p : std_logic;
signal clk : std_logic; signal acam_rise_intflag_p : std_logic;
signal counter_reset : std_logic; signal acam_halfcounter_gone : std_logic;
signal offset_value : std_logic_vector(g_width-1 downto 0); signal add_offset : std_logic;
signal offset_to_shift : unsigned(g_width-1 downto 0); signal clk : std_logic;
signal one_hz_p : std_logic; signal counter_reset : std_logic;
signal reset : std_logic; signal offset_value : std_logic_vector(g_width-1 downto 0);
signal start_nb_offset : std_logic_vector(g_width-1 downto 0); signal offset_to_shift : unsigned(g_width-1 downto 0);
signal start_trig : std_logic; signal one_hz_p : std_logic;
signal reset : std_logic;
signal start_nb_offset : std_logic_vector(g_width-1 downto 0);
signal start_trig : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
...@@ -85,20 +89,34 @@ begin ...@@ -85,20 +89,34 @@ begin
port map( port map(
clk => clk, clk => clk,
end_value => x"FFFFFFFF", end_value => x"FFFFFFFF",
incr => acam_intflag_p, incr => add_offset,
reset => counter_reset, reset => counter_reset,
count_done => open, count_done => open,
current_value => offset_value current_value => offset_value
); );
halfcounter_monitor: process -- The halfcounter monitor is needed to make
begin -- sure that the falling edge pulse received
if reset ='1' or one_hz_p ='1' then -- corresponds to a real overflow of the ACAM
acam_halfcounter_gone <= '0'; -- counter and not to a different reason,
elsif acam_rise_intflag_p ='1' then -- for example a reset.
acam_halfcounter_gone <= '1'; -- This way the start_nb_offset will really
elsif acam_fall_intflag_p ='1' then -- track the number of internal start retriggers
acam_halfcounter_gone <= '0'; -- inside the ACAM.
end if;
wait until clk ='1';
end process;
add_offset <= acam_fall_intflag_p and acam_halfcounter_gone;
counter_reset <= reset or one_hz_p; counter_reset <= reset or one_hz_p;
offset_to_shift <= unsigned(offset_value); offset_to_shift <= unsigned(offset_value);
start_nb_offset <= std_logic_vector(shift_left(offset_to_shift,8)); start_nb_offset <= std_logic_vector(shift_left(offset_to_shift,8));
start_trig <= one_hz_p; start_trig <= one_hz_p;
-- inputs -- inputs
acam_intflag_p <= acam_intflag_p_i; acam_fall_intflag_p <= acam_fall_intflag_p_i;
acam_rise_intflag_p <= acam_rise_intflag_p_i;
clk <= clk_i; clk <= clk_i;
one_hz_p <= one_hz_p_i; one_hz_p <= one_hz_p_i;
reset <= reset_i; reset <= reset_i;
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ 8d74d3fa
...@@ -143,16 +143,17 @@ architecture rtl of top_tdc is ...@@ -143,16 +143,17 @@ architecture rtl of top_tdc is
component start_retrigger_control is component start_retrigger_control is
generic( generic(
g_width : integer :=32 g_width : integer :=32
); );
port( port(
acam_intflag_p_i : in std_logic; acam_rise_intflag_p_i : in std_logic;
clk_i : in std_logic; acam_fall_intflag_p_i : in std_logic;
one_hz_p_i : in std_logic; clk_i : in std_logic;
reset_i : in std_logic; one_hz_p_i : in std_logic;
reset_i : in std_logic;
start_nb_offset_o : out std_logic_vector(g_width-1 downto 0); start_nb_offset_o : out std_logic_vector(g_width-1 downto 0);
start_trig_o : out std_logic start_trig_o : out std_logic
); );
end component; end component;
...@@ -176,24 +177,26 @@ architecture rtl of top_tdc is ...@@ -176,24 +177,26 @@ architecture rtl of top_tdc is
component acam_timecontrol_interface component acam_timecontrol_interface
generic( generic(
g_width : integer :=32 g_width : integer :=32
); );
port( port(
-- signals external to the chip: interface with acam -- signals external to the chip: interface with acam
err_flag_i : in std_logic; err_flag_i : in std_logic;
int_flag_i : in std_logic; int_flag_i : in std_logic;
start_dis_o : out std_logic; start_dis_o : out std_logic;
start_from_fpga_o : out std_logic; start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic; stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
clk_i : in std_logic; clk_i : in std_logic;
start_trig_i : in std_logic; start_trig_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
acam_errflag_p_o : out std_logic; acam_rise_errflag_p_o : out std_logic;
acam_intflag_p_o : out std_logic acam_fall_errflag_p_o : out std_logic;
acam_rise_intflag_p_o : out std_logic;
acam_fall_intflag_p_o : out std_logic
); );
end component; end component;
...@@ -366,8 +369,10 @@ signal tdc_led_trig3 : std_logic:='0'; ...@@ -366,8 +369,10 @@ signal tdc_led_trig3 : std_logic:='0';
signal tdc_led_trig4 : std_logic:='0'; signal tdc_led_trig4 : std_logic:='0';
signal tdc_led_trig5 : std_logic:='0'; signal tdc_led_trig5 : std_logic:='0';
signal acam_errflag_p : std_logic; signal acam_fall_errflag_p : std_logic;
signal acam_intflag_p : std_logic; signal acam_rise_errflag_p : std_logic;
signal acam_fall_intflag_p : std_logic;
signal acam_rise_intflag_p : std_logic;
signal acam_start01 : std_logic_vector(16 downto 0); signal acam_start01 : std_logic_vector(16 downto 0);
signal acam_timestamp : std_logic_vector(28 downto 0); signal acam_timestamp : std_logic_vector(28 downto 0);
signal acam_timestamp_valid : std_logic; signal acam_timestamp_valid : std_logic;
...@@ -435,16 +440,17 @@ begin ...@@ -435,16 +440,17 @@ begin
start_retrigger_block: start_retrigger_control start_retrigger_block: start_retrigger_control
generic map( generic map(
g_width => g_width g_width => g_width
) )
port map( port map(
acam_intflag_p_i => acam_intflag_p, acam_fall_intflag_p_i => acam_fall_intflag_p,
clk_i => clk, acam_rise_intflag_p_i => acam_rise_intflag_p,
one_hz_p_i => one_hz_p, clk_i => clk,
reset_i => general_reset, one_hz_p_i => one_hz_p,
reset_i => general_reset,
start_nb_offset_o => start_nb_offset, start_nb_offset_o => start_nb_offset,
start_trig_o => start_trig start_trig_o => start_trig
); );
data_formatting_block: data_formatting data_formatting_block: data_formatting
...@@ -483,8 +489,10 @@ begin ...@@ -483,8 +489,10 @@ begin
start_trig_i => start_trig, start_trig_i => start_trig,
reset_i => general_reset, reset_i => general_reset,
acam_errflag_p_o => acam_errflag_p, acam_fall_errflag_p_o => acam_fall_errflag_p,
acam_intflag_p_o => acam_intflag_p acam_rise_errflag_p_o => acam_rise_errflag_p,
acam_fall_intflag_p_o => acam_fall_intflag_p,
acam_rise_intflag_p_o => acam_rise_intflag_p
); );
acam_data_block: acam_databus_interface acam_data_block: acam_databus_interface
...@@ -686,13 +694,14 @@ begin ...@@ -686,13 +694,14 @@ begin
spec_led_red_o <= spec_led_red; spec_led_red_o <= spec_led_red;
tdc_led_status_o <= tdc_led_status; tdc_led_status_o <= tdc_led_status;
tdc_led_trig1_o <= tdc_led_trig1; tdc_led_trig1_o <= ef2_i;
tdc_led_trig2_o <= tdc_led_trig2; tdc_led_trig2_o <= ef1_i;
tdc_led_trig3_o <= tdc_led_trig3; tdc_led_trig3_o <= lf2_i;
tdc_led_trig4_o <= tdc_led_trig4; tdc_led_trig4_o <= lf1_i;
tdc_led_trig5_o <= tdc_led_trig5; tdc_led_trig5_o <= tdc_led_trig5;
-- these will evolve as we implement all the features -- these will evolve as we implement all the features
pulse_delay <= x"00000001";
mute_inputs_o <= '1'; mute_inputs_o <= '1';
term_en_1_o <= '1'; term_en_1_o <= '1';
term_en_2_o <= '1'; term_en_2_o <= '1';
......
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