Commit 96f9d92a authored by egousiou's avatar egousiou

added short .txt with instructions on how to synthesize (with synplify) and PaR

git-svn-id: http://svn.ohwr.org/fmc-tdc@89 85dfdc96-de2c-444c-878d-45b388be74a9
parent 02f2639a
To Synthesize the TDC design
--------------------------------
Open Synplify Premier with DP & Run the tdc_syn.prj
The constraints file is the tdc_syn_constraints.sdc
To PaR the TDC design
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Open Xilinx ISE & Run the following tcl commands:
(cd ../syn)
ngdbuild -uc synplicity.ucf syn_tdc.edf
map -detail -w -timing -ol high syn_tdc.ngd
par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
bitgen -w -g Binary:Yes par_tdc.ncd tdc
\ No newline at end of file
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