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FMC TDC 1ns 5cha - Gateware
Commit 97684cd3 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] isolate sequence counter in separate process and move it after the offset adjustment

parent 6409e0ef
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Showing with 29 additions and 32 deletions
hdl/rtl/tdc_ts_addsub.vhd
View file @ 97684cd3
......@@ -73,7 +73,6 @@ architecture rtl of tdc_ts_addsub is
tai : signed(32 downto 0);
coarse : signed(31 downto 0);
frac : signed(15 downto 0);
seq : std_logic_vector(31 downto 0);
meta : std_logic_vector(31 downto 0);
slope : std_logic;
end record;
......@@ -99,7 +98,6 @@ begin -- rtl
elsif(enable_i = '1') then
pipe(0) <= valid_i;
sums(0).seq <= a_i.seq;
sums(0).slope <= a_i.slope;
sums(0).meta <= a_i.meta;
......@@ -127,7 +125,6 @@ begin -- rtl
else
pipe(1) <= pipe(0);
sums(1).seq <= sums(0).seq;
sums(1).meta <= sums(0).meta;
sums(1).slope <= sums(0).slope;
......@@ -190,7 +187,6 @@ begin -- rtl
else
pipe(3) <= pipe(2);
sums(3).seq <= sums(2).seq;
sums(3).slope <= sums(2).slope;
sums(3).meta <= sums(2).meta;
......@@ -222,7 +218,6 @@ begin -- rtl
q_o.tai <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).tai(31 downto 0));
q_o.coarse <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).coarse(31 downto 0));
q_o.frac <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).frac(11 downto 0));
q_o.seq <= sums(c_NUM_PIPELINE_STAGES-1).seq;
q_o.slope <= sums(c_NUM_PIPELINE_STAGES-1).slope;
q_o.meta <= sums(c_NUM_PIPELINE_STAGES-1).meta;
end rtl;
hdl/rtl/timestamp_convert_filter.vhd
View file @ 97684cd3
......@@ -74,12 +74,14 @@ architecture rtl of timestamp_convert_filter is
signal fifo_we, fifo_rd, fifo_empty, fifo_full, fifo_rd_d : std_logic;
signal fifo_d, fifo_q : std_logic_vector(127 downto 0);
signal ts_fifo_out : t_acam_timestamp;
signal ts_valid_preoffset, ts_ready_preoffset, ts_valid_postoffset : std_logic_vector(4 downto 0);
signal ts_preoffset, ts_postoffset : t_tdc_timestamp_array(4 downto 0);
signal s1_meta, s2_meta, s3_meta : std_logic_vector(31 downto 0);
signal ts_valid_preoffset, ts_ready_preoffset : std_logic_vector(4 downto 0);
signal ts_valid_postoffset, ts_valid_postoffset_with_seq : std_logic_vector(4 downto 0);
signal ts_preoffset, ts_postoffset : t_tdc_timestamp_array(4 downto 0);
signal ts_postoffset_with_seq : t_tdc_timestamp_array(4 downto 0);
signal s1_meta, s2_meta, s3_meta : std_logic_vector(31 downto 0);
function f_pack_acam_timestamp (ts : t_acam_timestamp) return std_logic_vector is
variable rv : std_logic_vector(127 downto 0);
......@@ -105,7 +107,6 @@ architecture rtl of timestamp_convert_filter is
return ts;
end f_unpack_acam_timestamp;
begin
fifo_d <= f_pack_acam_timestamp(ts_i);
......@@ -125,7 +126,7 @@ architecture rtl of timestamp_convert_filter is
q_o => fifo_q,
rd_i => fifo_rd,
rd_empty_o => fifo_empty);
ts_fifo_out <= f_unpack_acam_timestamp(fifo_q);
fifo_rd <= not fifo_empty;
......@@ -141,7 +142,7 @@ architecture rtl of timestamp_convert_filter is
fifo_rd_d <= fifo_rd;
-- 64/125 = 4096/8000: reduce fraction to avoid 64-bit division
-- 64/125 = 4096/8000: reduce fraction to avoid 64-bit division
-- frac = hwts->bins * 81 * 64 / 125;
-- stage 1: scale frac
......@@ -219,14 +220,9 @@ architecture rtl of timestamp_convert_filter is
channels(i).s1_valid <= '0';
channels(i).s2_valid <= '0';
channels(i).last_valid <= '0';
channels(i).seq <= (others => '0');
else
channels(i).s1_valid <= '0';
if(reset_seq_i(i) = '1') then
channels(i).seq <= (others => '0');
end if;
if s3_valid = '1' and unsigned(s3_channel) = i then
if (s3_ts.slope = '1') then -- rising edge
......@@ -264,14 +260,6 @@ architecture rtl of timestamp_convert_filter is
ts_preoffset(i).meta <= channels(i).last_ts.meta;
ts_valid_preoffset(i) <= '1';
if(reset_seq_i(i) = '1') then
channels(i).seq <= (others => '0');
ts_preoffset(i).seq <= (others => '0');
else
channels(i).seq <= channels(i).seq + 1;
ts_preoffset(i).seq <= std_logic_vector(channels(i).seq);
end if;
else
ts_valid_preoffset(i) <= '0';
end if;
......@@ -288,12 +276,30 @@ architecture rtl of timestamp_convert_filter is
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
valid_i => ts_valid_preoffset(i),
enable_i => '1',
enable_i => enable_i(i),
a_i => ts_preoffset(i),
b_i => ts_offset_i(i),
valid_o => ts_valid_postoffset(i),
q_o => ts_postoffset(i));
p_seq_count : process(clk_sys_i) is
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i(i) = '0' or reset_seq_i(i) = '1' then
channels(i).seq <= (others => '0');
else
if ts_valid_postoffset(i) = '1' then
channels(i).seq <= channels(i).seq + 1;
ts_valid_postoffset_with_seq(i) <= '1';
ts_postoffset_with_seq(i) <= ts_postoffset(i);
ts_postoffset_with_seq(i).seq <= std_logic_vector(channels(i).seq);
else
ts_valid_postoffset_with_seq(i) <= '0';
end if;
end if;
end if;
end process p_seq_count;
p_output : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -314,9 +320,9 @@ architecture rtl of timestamp_convert_filter is
else
if ts_valid_postoffset(i) = '1' then
if ts_valid_postoffset_with_seq(i) = '1' then
ts_valid_o(i) <= '1';
ts_o(i) <= ts_postoffset(i);
ts_o(i) <= ts_postoffset_with_seq(i);
end if;
end if;
......@@ -330,7 +336,3 @@ architecture rtl of timestamp_convert_filter is
end rtl;
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