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FMC TDC 1ns 5cha - Gateware
Commit a8f3d745 authored by egousiou's avatar egousiou
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small modif on irq_generator: registers for the thresholds set to zero -> interrupts deactivated 

git-svn-id: http://svn.ohwr.org/fmc-tdc@94 85dfdc96-de2c-444c-878d-45b388be74a9
parent bd4a91e2
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hdl/spec/src/ip_cores/sdb_meta_pkg.vhd
View file @ a8f3d745
......@@ -72,9 +72,9 @@ package sdb_meta_pkg is
constant c_SDB_INTEGRATION : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
device_id => x"593b56e5", -- echo "spec_fmc-tdc-1ns5cha" | md5sum | cut -c1-8
version => x"00010001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130410", -- yyyymmdd
date => x"20130429", -- yyyymmdd
name => "spec_fmctdc1ns5cha "));
......
hdl/spec/src/rtl/data_formatting.vhd
View file @ a8f3d745
......@@ -354,33 +354,30 @@ begin
else local_utc_i;
belongs_to_previous_sec <= '1' when tstamp_on_first_retrig_case1 or tstamp_on_first_retrig_case2 else '0';
belongs_to_previous_sec <= '1' when tstamp_on_first_retrig_case1 = '1' or tstamp_on_first_retrig_case2 = '1' else '0';
-- the equation below describes the case where: a timestamp came on the same retgigger after a new second
-- (un_current_retrig_from_roll_over in principle is 0):
tstamp_on_first_retrig_case1 <= un_current_retrig_from_roll_over + un_acam_start_nb = un_current_retrig_nb_offset
tstamp_on_first_retrig_case1 <= '1' when (un_current_retrig_from_roll_over + un_acam_start_nb = un_current_retrig_nb_offset) else '0';
-- according to the Acam documentation there is an indeterminacy to whether the fine time refers to the previous retrigger or the current one.
-- the equation below describes the case where: a timestamp came on the same retgigger after a new second but the acam assigned
-- it to the previous retrigger.
-- the "un_current_retrig_from_roll_over = 0" describes that a new second has arrived;
-- the "fine_time > 6318" desribes a fine time that is referred to the previous retrigger; in principle in a retrigger is 512 ns,
-- so a fine time > 512 ns means that it is referred to a previous second.
tstamp_on_first_retrig_case2 <= (un_current_retrig_nb_offset = un_acam_start_nb+1) and (unsigned(fine_time) > 6318) and (un_current_retrig_from_roll_over = 0)
-- the number of roll-overs of the ACAM internal start retrigger counter is converted to a number
-- of internal start retriggers.
-- shifted left to multiply by 256
-- If a new tstamp has arrived from the ACAM when the roll_over has just been increased,
-- there are chances the tstamp belongs to the previous roll-over value. This is because the
-- moment the IrFlag is taken into account in the FPGA is different from the moment the tstamp
-- has arrived to the ACAM. So if in a timestamp the start_nb from the ACAM is close to the
-- upper end (close to 255) and on the moment the timestamp is being treated in the FPGA the IrFlag
-- has recently been tripped it means that for the formatting of the tstamp the previous value of
-- the roll_over_c should be considered (before the IrFlag tripping).
-- Have to calculate the amount of tstamps that could have been accumulated before the rollover
-- changes; the current value we put "192" is not well studied for all cases!!
-- the "fine_time > 6318" desribes a fine time that is referred to the previous retrigger; 6318 * 81ps = 512ns which is a complete Acam retrigger
tstamp_on_first_retrig_case2 <= '1' when (un_current_retrig_nb_offset = un_acam_start_nb+1) and (unsigned(fine_time) > 6318) and (un_current_retrig_from_roll_over = 0) else '0';
-- the number of roll-overs of the ACAM-internal-start-retrigger-counter is converted to a number of internal start retriggers,
-- multiplying by 256 i.e. shifting left
-- Note that if a new tstamp has arrived from the ACAM when the roll_over has just been increased, there are chances the tstamp
-- belongs to the previous roll-over value. This is because the moment the IrFlag is taken into account in the FPGA is different
-- from the moment the tstamp has arrived to the ACAM (several clk_i cycles to empty Acam fifo). So if in a timestamp the
-- start_nb from the ACAM is close to the upper end (close to 255) and on the moment the timestamp is being treated in the FPGA
-- the IrFlag has recently been tripped it means that for the formatting of the tstamp the previous value of the roll_over_c
-- should be considered (before the IrFlag tripping).
-- Eva: have to calculate better the amount of tstamps that could have been accumulated before the rollover changes;
-- the current value we put "192" is not well studied for all cases!!
un_retrig_from_roll_over <= shift_left(un_roll_over-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192
else shift_left(un_roll_over, 8);
......@@ -410,16 +407,9 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- metadata: information about the timestamp
metadata <= acam_start_nb & -- for debugging
retrig_nb_offset_i(15 downto 0) & -- for debugging
belongs_to_previous_sec & roll_over_incr_recent_i & "0" & acam_slope & --for debugging
"0" & acam_channel;
--"0" & acam_channel; -- 4 bits in total (LSB)
--metadata <= x"0000" & -- 16 bits (MSB)
-- "000" & acam_fifo_ef & -- 4 bits in total
-- "000" & acam_fifo_lf & -- 4 bits in total
-- "000" & acam_slope & -- 4 bits in total
-- "0" & acam_channel; -- 4 bits in total (LSB)
metadata <= acam_start_nb & retrig_nb_offset_i(15 downto 0) & -- for debugging (24 MSbits)
belongs_to_previous_sec & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
acam_slope & "0" & acam_channel; -- 5 LSbits
---------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/irq_generator.vhd
View file @ a8f3d745
......@@ -29,7 +29,10 @@
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 EG First version |
-- 05/2012 v0.1 EG First version |
-- 04/2013 v0.2 EG line 170 added "irq_time_threshold_i > 0"; if the user doesn t want the |
-- time interrupts he sets the irq_time_threshold reg to zero; same goes |
-- for number-of-tstamps interrupts, users sets to zero to disable them |
-- |
---------------------------------------------------------------------------------------------------
......@@ -166,7 +169,7 @@ begin
nxt_irq_st <= IDLE;
elsif tstamps_c > ZERO and tstamps_c >= irq_tstamp_threshold_i(8 downto 0) then -- not >= ZERO!!
nxt_irq_st <= RAISE_IRQ_TSTAMP;
elsif time_c >= irq_time_threshold_i and tstamps_c > ZERO then
elsif unsigned(irq_time_threshold_i) > 0 and time_c >= irq_time_threshold_i and tstamps_c > ZERO then
nxt_irq_st <= RAISE_IRQ_TIME;
else
nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
......@@ -263,4 +266,4 @@ begin
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/spec/src/rtl/tdc_core_pkg.vhd
View file @ a8f3d745
......@@ -139,7 +139,7 @@ package tdc_core_pkg is
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_TDC_SDB_DEVICE : t_sdb_device :=-----------------------------------------
constant c_TDC_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
......@@ -152,7 +152,7 @@ package tdc_core_pkg is
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604",
version => x"00000001",
date => x"20121116",
date => x"20130429",
name => "WB-TDC-Core ")));
constant c_INT_SDB_DEVICE : t_sdb_device :=
......
hdl/spec/syn/TDC_HowToPaR.txt deleted 100644 → 0
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To Synthesize the TDC design
--------------------------------
Open Synplify Premier with DP & Run the tdc_syn.prj
The constraints file is the tdc_syn_constraints.sdc
To PaR the TDC design
--------------------------------
Open Xilinx ISE & Run the following tcl commands:
(cd ../syn)
ngdbuild -uc synplicity.ucf syn_tdc.edf
map -detail -w -timing -ol high syn_tdc.ngd
par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
bitgen -w -g Binary:Yes par_tdc.ncd tdc
\ No newline at end of file
hdl/spec/syn/cleanup deleted 100755 → 0
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rm -r backup
rm -r coreip
rm identify.log
rm rpt_top_tdc.areasrr rpt_top_tdc_areasrr.htm
rm run_ise.tcl
rm run_options.txt scratchproject.prs
rm synplicity.ucf
rm fifo_32x512.ngc
rm fifo_64x512.ngc
rm syn_tdc.edf
rm syn_tdc.fse
rm syn_tdc.htm
rm syn_tdc.map
rm syn_tdc.ncf
rm syn_tdc_prepass.srd
rm syn_tdc.sap
rm syn_tdc.srd
rm syn_tdc.srl
rm syn_tdc.srm
rm syn_tdc.srr
rm syn_tdc.srs
rm syn_tdc.szr
rm syn_tdc.tlg
rm -r syntmp
rm -r xplace
rm syn_tdc.bld
rm syn_tdc.mrp
rm syn_tdc.ncd
rm syn_tdc.ngd
rm syn_tdc_ngdbuild.xrpt
rm syn_tdc.ngm
rm syn_tdc.ngo
rm syn_tdc.pcf
rm syn_tdc_summary.xml
rm syn_tdc_usage.xml
rm top_tdc_map.xrpt
rm top_tdc_par.xrpt
rm -r xlnx_auto_0_xdb
rm -r _xmsgs
rm netlist.lst
rm par_tdc.ncd
rm par_tdc.pad
rm par_tdc_pad.csv
rm par_tdc_pad.txt
rm par_tdc.par
rm par_tdc.ptwx
rm par_tdc.unroutes
rm par_tdc.xpi
rm par_usage_statistics.html
rm timing_report.twr
rm timing_report.twx
rm tdc.bgn
rm tdc.bit
rm tdc_bitgen.xwbt
rm tdc.drc
rm webtalk.log
hdl/spec/syn/netlist.lst deleted 100644 → 0
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C:\FMC_TDC\evas_fmc_tdc\syn\syn_tdc.edf 1339520207
OK
hdl/spec/syn/par_tdc.ncd
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Release 13.4 - par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Tue Jun 12 19:10:49 2012
All signals are completely routed.
hdl/spec/syn/par_tdc.xpi deleted 100644 → 0
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PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
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hdl/spec/syn/par_usage_statistics.html deleted 100644 → 0
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>8373</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>26192</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>26192</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>25129</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>15.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>18.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>35.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>44.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>66.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>68.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>129.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>129.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>130.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>132.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>6.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>6.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>12.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>4.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>3.2105</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
hdl/spec/syn/rpt_top_tdc.areasrr deleted 100644 → 0
View file @ bd4a91e2
#### START OF AREA REPORT #####[
Part: XC6SLX45TFGG484-3 (Xilinx)
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 5527 100 %
LATCHES 0 0.0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 5527 (42.47 % Utilization)
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 4509 100 %
MUXCY 1278 100 %
XORCY 1090 100 %
MULT18x18/MULT18x18S 1 100 %
SRL16 0 0.0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 6878 (52.85 % Utilization)
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 12 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 12 (0.09 % Utilization)
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0.0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0.0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 132 100 %
=================================================
Total IO PADS in the block top_tdc: 132 (1.01 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 12
clks_rsts_mgment.un6_pll_word_being_sent_0_0
----------------------------
----------------------------
circular_buffer_block.memory_block.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.TRUE_DP.PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 1
----------------------------
circular_buffer_block.memory_block.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[1].ram.r.s6_noinit.ram.TRUE_DP.PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 1
----------------------------
circular_buffer_block.memory_block.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[2].ram.r.s6_noinit.ram.TRUE_DP.PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 1
----------------------------
circular_buffer_block.memory_block.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[3].ram.r.s6_noinit.ram.TRUE_DP.PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 1
----------------------------
gnum_interface_block.cmp_p2l_dma_master.cmp_to_wb_fifo.gen_fifo_64bit.cmp_fifo_64x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_p2l_dma_master.cmp_to_wb_fifo.gen_fifo_64bit.cmp_fifo_64x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[1].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_l2p_dma_master.cmp_data_fifo.gen_fifo_32bit.cmp_fifo_32x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_l2p_dma_master.cmp_addr_fifo.gen_fifo_32bit.cmp_fifo_32x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_wbmaster32.cmp_from_wb_fifo.gen_fifo_32bit.cmp_fifo_32x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_wbmaster32.cmp_fifo_to_wb.gen_fifo_64bit.cmp_fifo_64x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_wbmaster32.cmp_fifo_to_wb.gen_fifo_64bit.cmp_fifo_64x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[1].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
hdl/spec/syn/rpt_top_tdc_areasrr.htm deleted 100644 → 0
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<html><head><title></title></head><body><a name=TopSummary>
#### START OF AREA REPORT #####[<pre>
Part: XC6SLX45TFGG484-3 (Xilinx)
Click here to go to specific block report:
<a href="rpt_top_tdc_areasrr.htm#top_tdc"><h5 align="center">top_tdc</h5></a><br><a name=top_tdc>
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 5527 100 %
LATCHES 0 0.0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 5527 (42.47 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 4509 100 %
MUXCY 1278 100 %
XORCY 1090 100 %
MULT18x18/MULT18x18S 1 100 %
SRL16 0 0.0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 6878 (52.85 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 12 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 12 (0.09 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0.0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0.0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 132 100 %
=================================================
Total IO PADS in the block top_tdc: 132 (1.01 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 12
clks_rsts_mgment.un6_pll_word_being_sent_0_0
----------------------------
----------------------------
circular_buffer_block.memory_block.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.TRUE_DP.PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 1
----------------------------
circular_buffer_block.memory_block.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[1].ram.r.s6_noinit.ram.TRUE_DP.PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 1
----------------------------
circular_buffer_block.memory_block.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[2].ram.r.s6_noinit.ram.TRUE_DP.PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 1
----------------------------
circular_buffer_block.memory_block.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[3].ram.r.s6_noinit.ram.TRUE_DP.PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 1
----------------------------
gnum_interface_block.cmp_p2l_dma_master.cmp_to_wb_fifo.gen_fifo_64bit.cmp_fifo_64x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_p2l_dma_master.cmp_to_wb_fifo.gen_fifo_64bit.cmp_fifo_64x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[1].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_l2p_dma_master.cmp_data_fifo.gen_fifo_32bit.cmp_fifo_32x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_l2p_dma_master.cmp_addr_fifo.gen_fifo_32bit.cmp_fifo_32x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_wbmaster32.cmp_from_wb_fifo.gen_fifo_32bit.cmp_fifo_32x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_wbmaster32.cmp_fifo_to_wb.gen_fifo_64bit.cmp_fifo_64x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[0].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
gnum_interface_block.cmp_wbmaster32.cmp_fifo_to_wb.gen_fifo_64bit.cmp_fifo_64x512.BU2.U0.grf.rf.mem.gbm.gbmg.gbmga.ngecc.bmg.blk_mem_generator.valid.cstr.ramloop[1].ram.r.s6_noinit.ram.SDP.SIMPLE_PRIM18.ram
----------------------------
WRITE_MODE_A WRITE_FIRST
WRITE_MODE_B WRITE_FIRST
SRVAL_A 000000000
SRVAL_B 000000000
DOA_REG 0
DOB_REG 0
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
</a></body></html>
hdl/spec/syn/run_ise.tcl deleted 100644 → 0
View file @ bd4a91e2
#################################################
### SET DESIGN VARIABLES ###
#################################################
set DesignName "syn_tdc"
set FamilyName "SPARTAN6"
set DeviceName "XC6SLX45T"
set PackageName "FGG484"
set SpeedGrade "-3"
set TopModule "top_tdc"
set EdifFile "C:/FMC_TDC/evas_fmc_tdc/syn/syn_tdc.edf"
#################################################
### SET FLOW ###
#################################################
set Flow "Standard"
#################################################
### SET POWER OPTION ###
#################################################
set Power "0"
#################################################
### PROJECT SETUP ###
#################################################
if {![file exists $DesignName.xise]} {
project new $DesignName.xise
project set family $FamilyName
project set device $DeviceName
project set package $PackageName
project set speed $SpeedGrade
xfile add $EdifFile
if {[file exists synplicity.ucf]} { xfile add synplicity.ucf }
} else {
project open $DesignName.xise
}
#################################################
### STANDARD ###
#################################################
if { $Flow == "Standard" } {
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project set {Place & Route Effort Level (Overall)} "High"
}
#################################################
### FAST ###
#################################################
if { $Flow == "Fast" } {
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project set {Place & Route Effort Level (Overall)} "Standard"
}
#################################################
### SMARTGUIDE ###
#################################################
if { $Flow == "SmartGuide" } {
project set "Use Smartguide" TRUE
project set "SmartGuide Filename" $DesignName\_guide.ncd
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project set {Place & Route Effort Level (Overall)} "High"
}
#################################################
### SMARTGUIDE FAST ###
#################################################
if { $Flow == "SmartGuideFast" } {
project set "Use Smartguide" TRUE
project set "SmartGuide Filename" $DesignName\_guide.ncd
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project set {Place & Route Effort Level (Overall)} "Standard"
}
#################################################
### EXECUTE ISE PLACE & ROUTE ###
#################################################
file delete -force $DesignName\_xdb
project open $DesignName.xise
process run "Implement Design" -force rerun_all
## process run "Generate Programming File"
#################################################
### EXECUTE POWER OPTION ###
#################################################
if { $Power == "1" } {
exec xpwr -v $DesignName.ncd $DesignName.pcf
}
project close
hdl/spec/syn/run_options.txt deleted 100644 → 0
View file @ bd4a91e2
#-- Synopsys, Inc.
#-- Version F-2012.03
#-- Project file C:\FMC_TDC\evas_fmc_tdc\syn\run_options.txt
#project files
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/genram_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/wishbone_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gencores_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/pulse_sync_rtl.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core.vhd"
add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/decr_counter.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_slave_adapter/wb_slave_adapter.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_bit_ctrl.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_byte_ctrl.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_top.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/wb_i2c_master.vhd"
add_file -verilog "../src/ip_cores/wb_onewire_master/sockit_owm.v"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/xwb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/wb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller_regs.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller.vhd"
add_file -vhdl -lib work "../src/rtl/clks_rsts_manager.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrig_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/wb_addr_decoder.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../src/rtl/irq_generator.vhd"
add_file -vhdl -lib work "../src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/leds_manager.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -constraint "./tdc_syn_constraints.sdc"
#implementation: "syn"
impl -add syn -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
set_option -enable_nfilter 1
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
#design plan options
impl -active "syn"
hdl/spec/syn/scratchproject.prs deleted 100644 → 0
View file @ bd4a91e2
#-- Synopsys, Inc.
#-- Version F-2012.03
#-- Project file C:\FMC_TDC\evas_fmc_tdc\syn\scratchproject.prs
#project files
add_file -include "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/gn4124_core_pkg.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/genram_pkg.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wishbone_pkg.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gencores_pkg.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/l2p_ser.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/p2l_des.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/pulse_sync_rtl.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/gnum_core/gn4124_core.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/free_counter.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/decr_counter.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_slave_adapter/wb_slave_adapter.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_i2c_master/i2c_master_bit_ctrl.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_i2c_master/i2c_master_byte_ctrl.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_i2c_master/i2c_master_top.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_i2c_master/wb_i2c_master.vhd"
add_file -verilog "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_onewire_master/sockit_owm.v"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_onewire_master/xwb_onewire_master.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_onewire_master/wb_onewire_master.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_irq_controller/irq_controller_regs.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/ip_cores/wb_irq_controller/irq_controller.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/clks_rsts_manager.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/start_retrig_ctrl.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/wb_addr_decoder.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/data_engine.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/irq_generator.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/leds_manager.vhd"
add_file -vhdl -lib work "C:/FMC_TDC/evas_fmc_tdc/src/rtl/top_tdc.vhd"
add_file -constraint "C:/FMC_TDC/evas_fmc_tdc/syn/tdc_syn_constraints.sdc"
#implementation: "syn"
impl -add C:\FMC_TDC\evas_fmc_tdc\syn -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
set_option -enable_nfilter 1
set_option -include_path {C:/FMC_TDC/evas_fmc_tdc/syn/}
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "C:/FMC_TDC/evas_fmc_tdc/syn/syn_tdc.edf"
#design plan options
impl -active "syn"
hdl/spec/syn/syn_tdc.bld deleted 100644 → 0
View file @ bd4a91e2
Release 13.4 ngdbuild O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line: C:\EDA\Xilinx\v13_4\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -uc
synplicity.ucf syn_tdc.edf
Executing edif2ngd "syn_tdc.edf" "syn_tdc.ngo"
Release 13.4 - edif2ngd O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 13.4 edif2ngd O.87xd (nt)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Applying constraints in "syn_tdc.ncf" to module "top_tdc"...
Checking Constraint Associations...
Writing module to "syn_tdc.ngo"...
Reading NGO file "C:/FMC_TDC/evas_fmc_tdc/syn/syn_tdc.ngo" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "synplicity.ucf" ...
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
'gnum_interface_block.cmp_clk_in.rx_pll_adv_inst' of type PLL_ADV has been
changed from 'VIRTEX5' to 'SPARTAN6' to correct post-ngdbuild and timing
simulation for this primitive. In order for functional simulation to be
correct, the value of SIM_DEVICE should be changed in this same manner in the
source netlist or constraint file.
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "iodelay_1005_0"
OFFSET = IN 6.000 ns BEFORE "tdc_clk_p_i" RISING;> [synplicity.ucf(42)], is
specified without a duration. This will result in a lack of hold time checks
in timing reports. If hold time checks are desired a duration value should
be specified following the 'VALID' keyword.
WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "iodelay_1005_1"
OFFSET = IN 22.000 ns BEFORE "tdc_clk_p_i" RISING;> [synplicity.ucf(44)], is
specified without a duration. This will result in a lack of hold time checks
in timing reports. If hold time checks are desired a duration value should
be specified following the 'VALID' keyword.
WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "iodelay_1031_0"
OFFSET = IN 48.000 ns BEFORE "spec_clk_i" RISING;> [synplicity.ucf(112)], is
specified without a duration. This will result in a lack of hold time checks
in timing reports. If hold time checks are desired a duration value should
be specified following the 'VALID' keyword.
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 4
Total memory usage is 125992 kilobytes
Writing NGD file "syn_tdc.ngd" ...
Total REAL time to NGDBUILD completion: 26 sec
Total CPU time to NGDBUILD completion: 10 sec
Writing NGDBUILD log file "syn_tdc.bld"...
hdl/spec/syn/syn_tdc.edf
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hdl/spec/syn/syn_tdc.fse deleted 100644 → 0
View file @ bd4a91e2
fsm_encoding {52176417612} onehot
fsm_state_encoding {52176417612} active {00000000001}
fsm_state_encoding {52176417612} inactive {00000000010}
fsm_state_encoding {52176417612} get_stamp1 {00000000100}
fsm_state_encoding {52176417612} get_stamp2 {00000001000}
fsm_state_encoding {52176417612} wr_config {00000010000}
fsm_state_encoding {52176417612} rdbk_config {00000100000}
fsm_state_encoding {52176417612} rd_status {00001000000}
fsm_state_encoding {52176417612} rd_ififo1 {00010000000}
fsm_state_encoding {52176417612} rd_ififo2 {00100000000}
fsm_state_encoding {52176417612} rd_start01 {01000000000}
fsm_state_encoding {52176417612} wr_reset {10000000000}
fsm_registers {52176417612} {engine_st[0]} {engine_st[1]} {engine_st[2]} {engine_st[3]} {engine_st[4]} {engine_st[5]} {engine_st[6]} {engine_st[7]} {engine_st[8]} {engine_st[9]} {engine_st[10]}
fsm_encoding {4024092402} onehot
fsm_state_encoding {4024092402} st_idle {000001}
fsm_state_encoding {4024092402} st_start {000010}
fsm_state_encoding {4024092402} st_read {000100}
fsm_state_encoding {4024092402} st_write {001000}
fsm_state_encoding {4024092402} st_ack {010000}
fsm_state_encoding {4024092402} st_stop {100000}
fsm_registers {4024092402} {c_state[0]} {c_state[1]} {c_state[2]} {c_state[3]} {c_state[4]} {c_state[5]}
fsm_encoding {3941884181} onehot
fsm_state_encoding {3941884181} idle {000000000000000001}
fsm_state_encoding {3941884181} start_a {000000000000000010}
fsm_state_encoding {3941884181} start_b {000000000000000100}
fsm_state_encoding {3941884181} start_c {000000000000001000}
fsm_state_encoding {3941884181} start_d {000000000000010000}
fsm_state_encoding {3941884181} start_e {000000000000100000}
fsm_state_encoding {3941884181} stop_a {000000000001000000}
fsm_state_encoding {3941884181} stop_b {000000000010000000}
fsm_state_encoding {3941884181} stop_c {000000000100000000}
fsm_state_encoding {3941884181} stop_d {000000001000000000}
fsm_state_encoding {3941884181} rd_a {000000010000000000}
fsm_state_encoding {3941884181} rd_b {000000100000000000}
fsm_state_encoding {3941884181} rd_c {000001000000000000}
fsm_state_encoding {3941884181} rd_d {000010000000000000}
fsm_state_encoding {3941884181} wr_a {000100000000000000}
fsm_state_encoding {3941884181} wr_b {001000000000000000}
fsm_state_encoding {3941884181} wr_c {010000000000000000}
fsm_state_encoding {3941884181} wr_d {100000000000000000}
fsm_registers {3941884181} {c_state[0]} {c_state[1]} {c_state[2]} {c_state[3]} {c_state[4]} {c_state[5]} {c_state[6]} {c_state[7]} {c_state[8]} {c_state[9]} {c_state[10]} {c_state[11]} {c_state[12]} {c_state[13]} {c_state[14]} {c_state[15]} {c_state[16]} {c_state[17]}
fsm_encoding {2315541553} onehot
fsm_state_encoding {2315541553} 0000 {000000001}
fsm_state_encoding {2315541553} 0001 {000000010}
fsm_state_encoding {2315541553} 0010 {000000100}
fsm_state_encoding {2315541553} 0011 {000001000}
fsm_state_encoding {2315541553} 0100 {000010000}
fsm_state_encoding {2315541553} 0101 {000100000}
fsm_state_encoding {2315541553} 0110 {001000000}
fsm_state_encoding {2315541553} 0111 {010000000}
fsm_state_encoding {2315541553} 1001 {100000000}
fsm_registers {2315541553} {state[0]} {state[1]} {state[2]} {state[3]} {state[4]} {state[5]} {state[6]} {state[7]} {state[8]}
fsm_encoding {2114141414} sequential
fsm_state_encoding {2114141414} 0000 {0}
fsm_state_encoding {2114141414} 0001 {1}
fsm_registers {2114141414} {state[0]}
fsm_encoding {2114141415} sequential
fsm_state_encoding {2114141415} 0000 {0}
fsm_state_encoding {2114141415} 0001 {1}
fsm_registers {2114141415} {state[0]}
fsm_encoding {2525242527} sequential
fsm_state_encoding {2525242527} l2p_idle {00}
fsm_state_encoding {2525242527} l2p_header {01}
fsm_state_encoding {2525242527} l2p_data {10}
fsm_registers {2525242527} {l2p_read_cpl_current_state[1]} {l2p_read_cpl_current_state[0]}
fsm_encoding {2538843886} sequential
fsm_state_encoding {2538843886} wb_idle {00}
fsm_state_encoding {2538843886} wb_read_fifo {01}
fsm_state_encoding {2538843886} wb_cycle {10}
fsm_state_encoding {2538843886} wb_wait_ack {11}
fsm_registers {2538843886} {wishbone_current_state[1]} {wishbone_current_state[0]}
fsm_encoding {2733943398} onehot
fsm_state_encoding {2733943398} dma_idle {0000001}
fsm_state_encoding {2733943398} dma_start_transfer {0000010}
fsm_state_encoding {2733943398} dma_transfer {0000100}
fsm_state_encoding {2733943398} dma_start_chain {0001000}
fsm_state_encoding {2733943398} dma_chain {0010000}
fsm_state_encoding {2733943398} dma_error {0100000}
fsm_state_encoding {2733943398} dma_abort {1000000}
fsm_registers {2733943398} {dma_ctrl_current_state[0]} {dma_ctrl_current_state[1]} {dma_ctrl_current_state[2]} {dma_ctrl_current_state[3]} {dma_ctrl_current_state[4]} {dma_ctrl_current_state[5]} {dma_ctrl_current_state[6]}
fsm_encoding {2832643269} onehot
fsm_state_encoding {2832643269} l2p_idle {00000001}
fsm_state_encoding {2832643269} l2p_wait_data {00000010}
fsm_state_encoding {2832643269} l2p_header {00000100}
fsm_state_encoding {2832643269} l2p_addr_h {00001000}
fsm_state_encoding {2832643269} l2p_addr_l {00010000}
fsm_state_encoding {2832643269} l2p_data {00100000}
fsm_state_encoding {2832643269} l2p_last_data {01000000}
fsm_state_encoding {2832643269} l2p_wait_rdy {10000000}
fsm_registers {2832643269} {l2p_dma_current_state[0]} {l2p_dma_current_state[1]} {l2p_dma_current_state[2]} {l2p_dma_current_state[3]} {l2p_dma_current_state[4]} {l2p_dma_current_state[5]} {l2p_dma_current_state[6]} {l2p_dma_current_state[7]}
fsm_encoding {29290429010} onehot
fsm_state_encoding {29290429010} p2l_idle {00001}
fsm_state_encoding {29290429010} p2l_header {00010}
fsm_state_encoding {29290429010} p2l_addr_h {00100}
fsm_state_encoding {29290429010} p2l_addr_l {01000}
fsm_state_encoding {29290429010} p2l_wait_read_completion {10000}
fsm_registers {29290429010} {p2l_dma_current_state[0]} {p2l_dma_current_state[1]} {p2l_dma_current_state[2]} {p2l_dma_current_state[3]} {p2l_dma_current_state[4]}
fsm_encoding {54167416711} onehot
fsm_state_encoding {54167416711} idle {0000001}
fsm_state_encoding {54167416711} rd_start {0000010}
fsm_state_encoding {54167416711} rd_fetch {0000100}
fsm_state_encoding {54167416711} rd_ack {0001000}
fsm_state_encoding {54167416711} wr_start {0010000}
fsm_state_encoding {54167416711} wr_push {0100000}
fsm_state_encoding {54167416711} wr_ack {1000000}
fsm_registers {54167416711} {acam_data_st[0]} {acam_data_st[1]} {acam_data_st[2]} {acam_data_st[3]} {acam_data_st[4]} {acam_data_st[5]} {acam_data_st[6]}
fsm_encoding {56124412413} sequential
fsm_state_encoding {56124412413} idle {00}
fsm_state_encoding {56124412413} tstamp_and_time_counting {01}
fsm_state_encoding {56124412413} raise_irq_tstamp {10}
fsm_state_encoding {56124412413} raise_irq_time {11}
fsm_registers {56124412413} {irq_st[1]} {irq_st[0]}
fsm_encoding {55193419314} sequential
fsm_state_encoding {55193419314} idle {00}
fsm_state_encoding {55193419314} mem_access {01}
fsm_state_encoding {55193419314} mem_access_and_acknowledge {10}
fsm_state_encoding {55193419314} acknowledge {11}
fsm_registers {55193419314} {tstamp_rd_wb_st[1]} {tstamp_rd_wb_st[0]}
fsm_encoding {47427442715} onehot
fsm_state_encoding {47427442715} config_start {000001}
fsm_state_encoding {47427442715} sending_dac_word {000010}
fsm_state_encoding {47427442715} sending_pll_instruction {000100}
fsm_state_encoding {47427442715} sending_pll_data {001000}
fsm_state_encoding {47427442715} rest {010000}
fsm_state_encoding {47427442715} done {100000}
fsm_registers {47427442715} {config_st[0]} {config_st[1]} {config_st[2]} {config_st[3]} {config_st[4]} {config_st[5]}
hdl/spec/syn/syn_tdc.htm deleted 100644 → 0
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<html>
<head>
<title>syntmp/syn_tdc_srr.htm log file</title>
</head>
<frameset cols="20%, 80%">
<frameset rows="70%, 30%">
<frame src="syntmp/syn_tdc_toc.htm" name="tocFrame" />
<frame src="syntmp/syn_tdc_flink.htm" name="linkFrame" />
</frameset>
<frame src="syntmp/syn_tdc_srr.htm" name="srrFrame"/>
</frameset>
</html>
hdl/spec/syn/syn_tdc.map deleted 100644 → 0
View file @ bd4a91e2
Release 13.4 Map O.87xd (nt)
Xilinx Map Application Log File for Design 'top_tdc'
Design Information
------------------
Command Line : map -detail -w -timing -ol high syn_tdc.ngd
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 12 18:58:02 2012
Mapping design into LUTs...
WARNING:MapLib:701 - Signal p_wr_req_i(0) connected to top level port
p_wr_req_i(0) has been removed.
WARNING:MapLib:701 - Signal p_wr_req_i(1) connected to top level port
p_wr_req_i(1) has been removed.
WARNING:MapLib:701 - Signal vc_rdy_i(0) connected to top level port vc_rdy_i(0)
has been removed.
WARNING:MapLib:701 - Signal vc_rdy_i(1) connected to top level port vc_rdy_i(1)
has been removed.
WARNING:MapLib:701 - Signal tx_error_i connected to top level port tx_error_i
has been removed.
WARNING:MapLib:701 - Signal pll_sdo_i connected to top level port pll_sdo_i has
been removed.
WARNING:MapLib:701 - Signal err_flag_i connected to top level port err_flag_i
has been removed.
Writing file syn_tdc.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3223 - Timing constraint TS_1047_1 = MAXDELAY FROM TIMEGRP "from_1047_1" TO TIMEGRP "to_1047_0" 20 ns ignored during timing
analysis.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 28 secs
Total CPU time at the beginning of Placer: 23 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:d44ee5c1) REAL time: 32 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:d44ee5c1) REAL time: 33 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:d44ee5c1) REAL time: 33 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:db4ab45c) REAL time: 1 mins 8 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:db4ab45c) REAL time: 1 mins 8 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:db4ab45c) REAL time: 1 mins 8 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:db4ab45c) REAL time: 1 mins 8 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:db4ab45c) REAL time: 1 mins 9 secs
Phase 9.8 Global Placement
....................................................
......................................................
..........................................................................................................................................................................................
...............................
Phase 9.8 Global Placement (Checksum:b94231a2) REAL time: 1 mins 52 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:b94231a2) REAL time: 1 mins 52 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:f965be3) REAL time: 3 mins
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:f965be3) REAL time: 3 mins
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:1d377335) REAL time: 3 mins 1 secs
Total REAL time to Placer completion: 3 mins 12 secs
Total CPU time to Placer completion: 3 mins 4 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 9
Slice Logic Utilization:
Number of Slice Registers: 5,497 out of 54,576 10%
Number used as Flip Flops: 5,485
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 12
Number of Slice LUTs: 4,156 out of 27,288 15%
Number used as logic: 3,945 out of 27,288 14%
Number using O6 output only: 2,583
Number using O5 output only: 321
Number using O5 and O6: 1,041
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 211
Number with same-slice register load: 198
Number with same-slice carry load: 13
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,185 out of 6,822 32%
Nummber of MUXCYs used: 1,492 out of 13,644 10%
Number of LUT Flip Flop pairs used: 6,836
Number with an unused Flip Flop: 1,760 out of 6,836 25%
Number with an unused LUT: 2,680 out of 6,836 39%
Number of fully used LUT-FF pairs: 2,396 out of 6,836 35%
Number of unique control sets: 213
Number of slice register sites lost
to control set restrictions: 563 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 129 out of 296 43%
Number of LOCed IOBs: 129 out of 129 100%
IOB Flip Flops: 42
Specific Feature Utilization:
Number of RAMB16BWERs: 11 out of 116 9%
Number of RAMB8BWERs: 1 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 34 out of 376 9%
Number used as ILOGIC2s: 14
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 9 out of 376 2%
Number used as IODELAY2s: 9
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 48 out of 376 12%
Number used as OLOGIC2s: 28
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 1 out of 58 1%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.71
Peak Memory Usage: 378 MB
Total REAL time to MAP completion: 3 mins 19 secs
Total CPU time to MAP completion: 3 mins 9 secs
Mapping completed.
See MAP report file "syn_tdc.mrp" for details.
hdl/spec/syn/syn_tdc.mrp deleted 100644 → 0
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This diff is collapsed.
hdl/spec/syn/syn_tdc.ncd
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This diff is collapsed.
hdl/spec/syn/syn_tdc.ncf
View file @ a8f3d745
......@@ -62,8 +62,7 @@ NET "p_rd_d_rdy_i(0)" LOC="N16" ;
NET "p_rd_d_rdy_i(1)" LOC="P19" ;
NET "tx_error_i" LOC="M17" ;
NET "irq_p_o" LOC="U16" ;
NET "spare_o" LOC="AB19" ;
NET "spec_clk_i" LOC="H12" ;
NET "irq_aux_p_o" LOC="AB19" ;
NET "pll_sclk_o" LOC="AA16" ;
NET "pll_sdi_o" LOC="AA18" ;
NET "pll_cs_o" LOC="Y17" ;
......@@ -74,10 +73,10 @@ NET "tdc_clk_p_i" LOC="L20" ;
NET "tdc_clk_n_i" LOC="L22" ;
NET "acam_refclk_p_i" LOC="E16" ;
NET "acam_refclk_n_i" LOC="F16" ;
NET "start_from_fpga_o" LOC="W17" ;
NET "err_flag_i" LOC="V11" ;
NET "int_flag_i" LOC="W11" ;
NET "start_dis_o" LOC="T15" ;
NET "start_from_fpga_o" LOC="W17" ;
NET "stop_dis_o" LOC="U15" ;
NET "data_bus_io(0)" LOC="W6" ;
NET "data_bus_io(1)" LOC="Y6" ;
......@@ -129,10 +128,16 @@ NET "tdc_led_trig2_o" LOC="B20" ;
NET "tdc_led_trig3_o" LOC="A20" ;
NET "tdc_led_trig4_o" LOC="D17" ;
NET "tdc_led_trig5_o" LOC="C18" ;
NET "spec_clk_i" LOC="H12" ;
NET "carrier_one_wire_b" LOC="D4" ;
NET "sys_scl_b" LOC="F7" ;
NET "sys_sda_b" LOC="F8" ;
NET "mezz_one_wire_b" LOC="A19" ;
NET "pcb_ver_i(0)" LOC="P5" ;
NET "pcb_ver_i(1)" LOC="P4" ;
NET "pcb_ver_i(2)" LOC="AA2" ;
NET "pcb_ver_i(3)" LOC="AA1" ;
NET "prsnt_m2c_n_i" LOC="AB14" ;
NET "spec_led_green_o" LOC="E5" ;
NET "spec_led_red_o" LOC="D5" ;
NET "spec_aux0_i" LOC="C22" ;
......
hdl/spec/syn/syn_tdc.ngd
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hdl/spec/syn/syn_tdc.pcf
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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="13.4">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Tue Jun 12 18:57:31 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\EDA\Xilinx\v13_4\ISE_DS\ISE\\lib\nt;C:\EDA\Xilinx\v13_4\ISE_DS\ISE\\bin\nt;C:\EDA\Xilinx\v13_4\ISE_DS\PlanAhead\bin;C:\EDA\Xilinx\v13_4\ISE_DS\ISE\bin\nt;C:\EDA\Xilinx\v13_4\ISE_DS\ISE\lib\nt;C:\EDA\Xilinx\v13_4\ISE_DS\EDK\bin\nt;C:\EDA\Xilinx\v13_4\ISE_DS\EDK\lib\nt;C:\EDA\Xilinx\v13_4\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\EDA\Xilinx\v13_4\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\EDA\Xilinx\v13_4\ISE_DS\EDK\gnuwin\bin;C:\EDA\Xilinx\v13_4\ISE_DS\common\bin\nt;C:\EDA\Xilinx\v13_4\ISE_DS\common\lib\nt;C:\Actel\Libero_v8.6\Model\win32acoem;C:\SST;C:\Actel\Libero_v8.6\Designer\bin;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Actel\Libero_v8.6\WFL/bin;C:\Program Files\Subversion\bin;C:\Program Files\TortoiseSVN\bin;C:\Program Files\doxygen\bin;C:\Program Files\QuickTime\QTSystem\;C:\strawberry\c\bin;C:\strawberry\perl\site\bin;C:\strawberry\perl\bin;C:\Actel_8_5\Libero_v8.5\WFL/bin;C:\Program Files\TortoiseGit\bin;C:\modeltech_10.0\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\EDA\Xilinx\v13_4\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="2112@lxlic01,2112@lxlic02,2112@lxlic03"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\EDA\Xilinx\v13_4\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\EDA\Xilinx\v13_4\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\EDA\Xilinx\v13_4\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
</item>
<item stringID="User_EnvHost" value="pcbe13136"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
<task stringID="NGDBUILD_OPTION_SUMMARY">
<section stringID="NGDBUILD_OPTION_SUMMARY">
<item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="synplicity.ucf"/>
</section>
</task>
<task stringID="NGDBUILD_REPORT">
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="4"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY"/>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFIO2" value="1"/>
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<item dataType="int" stringID="NGDBUILD_NUM_DSP48A1" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="98"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="914"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="2679"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="93"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="116"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="25"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="219"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="1336"/>
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<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
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<item dataType="int" stringID="NGDBUILD_NUM_ISERDES2" value="20"/>
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<item dataType="int" stringID="NGDBUILD_NUM_LUT1_L" value="174"/>
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<item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="801"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="88"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="390"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="166"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="410"/>
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<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="648"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6_2" value="6"/>
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<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="180"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY_L" value="1098"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="101"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF8" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="58"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_OSERDES2" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_PLL_ADV" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="11"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="1090"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
</section>
</task>
</application>
</document>
hdl/spec/syn/syn_tdc_summary.xml deleted 100644 → 0
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="63">
<CmdHistory>
</CmdHistory>
</DesignSummary>
hdl/spec/syn/syn_tdc_synplify.sdc 0 → 100644
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hdl/spec/syn/synplicity.ucf
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Release 13.4 - Bitgen O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
C:\EDA\Xilinx\v13_4\ISE_DS\ISE\.
"top_tdc" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
Tue Jun 12 19:12:24 2012
C:\EDA\Xilinx\v13_4\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -w par_tdc.ncd tdc
INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER).
9K Block RAM initialization data, both user defined and default, requires a
special bit stream format. For more information, please reference Xilinx
Answer Record 39999.
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable* |
+----------------------+----------------------+
| DebugBitstream | No* |
+----------------------+----------------------+
| ConfigRate | 2* |
+----------------------+----------------------+
| StartupClk | Cclk* |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup* |
+----------------------+----------------------+
| TckPin | Pullup* |
+----------------------+----------------------+
| TdiPin | Pullup* |
+----------------------+----------------------+
| TdoPin | Pullup* |
+----------------------+----------------------+
| TmsPin | Pullup* |
+----------------------+----------------------+
| UnusedPin | Pulldown* |
+----------------------+----------------------+
| GWE_cycle | 6* |
+----------------------+----------------------+
| GTS_cycle | 5* |
+----------------------+----------------------+
| LCK_cycle | NoWait* |
+----------------------+----------------------+
| DONE_cycle | 4* |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No* |
+----------------------+----------------------+
| DonePipe | No* |
+----------------------+----------------------+
| Security | None* |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No* |
+----------------------+----------------------+
| Reset_on_err | No* |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No* |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk* |
+----------------------+----------------------+
| sw_gwe_cycle | 5* |
+----------------------+----------------------+
| sw_gts_cycle | 4* |
+----------------------+----------------------+
| multipin_wakeup | No* |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No* |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| MaskVectorFile | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| next_config_reboot | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | None* |
+----------------------+----------------------+
| spi_buswidth | 1* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No* |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
No constraints file was processed.
Running DRC.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
DRC detected 0 errors and 1 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "tdc.bit".
Bitstream generation is complete.
hdl/spec/syn/tdc.bit
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hdl/spec/syn/tdc.drc deleted 100644 → 0
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Release 13.4 Drc O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Tue Jun 12 19:12:24 2012
drc -z par_tdc.ncd
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
DRC detected 0 errors and 1 warnings. Please see the previously displayed
individual error or warning messages for more details.
hdl/spec/syn/tdc_bitgen.xwbt deleted 100644 → 0
View file @ bd4a91e2
INFILE=C:\FMC_TDC\evas_fmc_tdc\syn\par_tdc.ncd
OUTFILE=C:\FMC_TDC\evas_fmc_tdc\syn\tdc.bit
FAMILY=Spartan6
PART=xc6slx45t-3fgg484
WORKINGDIR=C:\FMC_TDC\evas_fmc_tdc\syn
LICENSE=ISE
USER_INFO=No user information available.
hdl/spec/syn/tdc_par_script.tcl
View file @ a8f3d745
......@@ -4,3 +4,7 @@ map -detail -w -timing -ol high syn_tdc.ngd
par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
bitgen -w par_tdc.ncd tdc
#bitgen -w -g Binary:Yes par_tdc.ncd tdc
cd C:/FMC_TDC/evas_fmc_tdc/syn;ngdbuild -uc synplicity.ucf syn_tdc.edf;map -detail -w -timing -ol high syn_tdc.ngd;par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf;bitgen -w par_tdc.ncd tdc
\ No newline at end of file
hdl/spec/syn/tdc_syn.prj
View file @ a8f3d745
......@@ -21,6 +21,8 @@ add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd
add_file -vhdl -lib work "../src/ip_cores/genram_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/wishbone_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gencores_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/sdb_meta_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd"
......@@ -41,10 +43,9 @@ add_file -vhdl -lib work "../src/ip_cores/gnum_core/pulse_sync_rtl.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core.vhd"
add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/decr_counter.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/sdb_rom.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/xwb_crossbar.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_crossbar/xwb_sdb_crossbar.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_slave_adapter/wb_slave_adapter.vhd"
......@@ -52,18 +53,24 @@ add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_bit_ctrl.vhd
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_byte_ctrl.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/i2c_master_top.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/wb_i2c_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_i2c_master/xwb_i2c_master.vhd"
add_file -verilog -lib work "../src/ip_cores/wb_onewire_master/sockit_owm.v"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/xwb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/wb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/wb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_onewire_master/xwb_onewire_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller_regs.vhd"
add_file -vhdl -lib work "../src/ip_cores/wb_irq_controller/irq_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/carrier_csr.vhd"
add_file -vhdl -lib work "../src/rtl/fmc_tdc_core.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/decr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clks_rsts_manager.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrig_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/wb_addr_decoder.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
......
hdl/spec/syn/tdc_syn_constraints.sdc
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@N: CD630 :".\gentmp0a02328":4:7:4:9|Synthesizing work.top.gen
@N: CD630 :"syng0a02328":106:7:106:12|Synthesizing work.cmp_eq.cell_level
@W: CD796 :"syng0a02328":129:11:129:18|Bit 10 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 11 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 12 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 13 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 14 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 15 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 16 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 17 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 18 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 19 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 20 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 21 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 22 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 23 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 24 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 25 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 26 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 27 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 28 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 29 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 30 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a02328":129:11:129:18|Bit 31 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@N: CD630 :"syng0a02328":41:7:41:24|Synthesizing work.eq_element_twobits.eqn
@N: CD630 :"C:\Synopsys\fpga_F201203\lib\xilinx\unisim.vhd":12719:10:12719:16|Synthesizing unisim.muxcy_l.syn_black_box
Post processing for unisim.muxcy_l.syn_black_box
Post processing for work.eq_element_twobits.eqn
@N: CD630 :"syng0a02328":8:7:8:16|Synthesizing work.eq_element.eqn
Post processing for work.eq_element.eqn
Post processing for work.cmp_eq.cell_level
Post processing for work.top.gen
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