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FMC TDC 1ns 5cha - Gateware
Commits
abad9a6f
Commit
abad9a6f
authored
Sep 17, 2018
by
Tomasz Wlostowski
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hdl: post-merge fixes, brought back direct readout interface
parent
8cb00631
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7 changed files
with
39 additions
and
9 deletions
+39
-9
clks_rsts_manager.vhd
hdl/rtl/clks_rsts_manager.vhd
+4
-3
data_engine.vhd
hdl/rtl/data_engine.vhd
+1
-1
fmc_tdc_core.vhd
hdl/rtl/fmc_tdc_core.vhd
+8
-1
fmc_tdc_mezzanine.vhd
hdl/rtl/fmc_tdc_mezzanine.vhd
+3
-1
fmc_tdc_wrapper.vhd
hdl/rtl/fmc_tdc_wrapper.vhd
+1
-1
timestamp_convert_filter.vhd
hdl/rtl/timestamp_convert_filter.vhd
+21
-1
wr_spec_tdc.vhd
hdl/top/spec/wr_spec_tdc.vhd
+1
-1
No files found.
hdl/rtl/clks_rsts_manager.vhd
View file @
abad9a6f
...
...
@@ -77,6 +77,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific libraries
library
work
;
use
work
.
tdc_core_pkg
.
all
;
-- definitions of types, constants, entities
use
work
.
gencores_pkg
.
all
;
library
UNISIM
;
use
UNISIM
.
vcomponents
.
all
;
...
...
@@ -162,9 +163,9 @@ architecture rtl of clks_rsts_manager is
signal
send_dac_word_r_edge_p
,
dac_only
:
std_logic
;
signal
pll_cs_n
,
dac_cs_n
:
std_logic
;
-- Synchronizers
signal
pll_status_synch
,
internal_rst_synch
:
std_logic
_vector
(
1
downto
0
)
;
signal
rst_in_synch
:
std_logic
_vector
(
1
downto
0
)
:
=
"11"
;
signal
acam_refclk_synch
,
send_dac_word_p_synch
:
std_logic
_vector
(
2
downto
0
)
;
signal
pll_status_synch
,
internal_rst_synch
:
std_logic
;
signal
rst_in_synch
:
std_logic
;
signal
acam_refclk_synch
,
send_dac_word_p_synch
:
std_logic
;
-- Clock buffers
signal
tdc_clk_buf
:
std_logic
;
signal
tdc_clk
,
acam_refclk
:
std_logic
;
...
...
hdl/rtl/data_engine.vhd
View file @
abad9a6f
...
...
@@ -804,7 +804,7 @@ begin
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
time_c_rst
,
counter_top_i
=>
f_pick
(
g_simulation
,
x"00005000"
,
x"0EE6B280"
),
counter_top_i
=>
work
.
tdc_core_pkg
.
f_pick
(
g_simulation
,
x"00005000"
,
x"0EE6B280"
),
counter_incr_en_i
=>
time_c_en
,
counter_is_full_o
=>
time_c_full_p
,
counter_o
=>
time_c
);
...
...
hdl/rtl/fmc_tdc_core.vhd
View file @
abad9a6f
...
...
@@ -214,10 +214,15 @@ entity fmc_tdc_core is
ts_offset_i
:
in
t_tdc_timestamp_array
(
4
downto
0
);
reset_seq_i
:
in
std_logic_vector
(
4
downto
0
);
raw_enable_i
:
in
std_logic_vector
(
4
downto
0
);
timestamp_o
:
out
t_tdc_timestamp_array
(
4
downto
0
);
timestamp_valid_o
:
out
std_logic_vector
(
4
downto
0
);
timestamp_ready_i
:
in
std_logic_vector
(
4
downto
0
);
-- direct interface, for compatibility with LIST/WRTD
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_valid_o
:
out
std_logic
;
channel_enable_o
:
out
std_logic_vector
(
4
downto
0
);
irq_threshold_o
:
out
std_logic_vector
(
9
downto
0
);
irq_timeout_o
:
out
std_logic_vector
(
9
downto
0
)
...
...
@@ -551,7 +556,9 @@ begin
ts_ready_i
=>
final_timestamp_ready
,
ts_offset_i
=>
ts_offset_i
,
reset_seq_i
=>
reset_seq_i
,
raw_enable_i
=>
raw_enable_i
raw_enable_i
=>
raw_enable_i
,
direct_timestamp_o
=>
direct_timestamp_o
,
direct_timestamp_valid_o
=>
direct_timestamp_valid_o
);
...
...
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @
abad9a6f
...
...
@@ -186,7 +186,7 @@ entity fmc_tdc_mezzanine is
-- 1-Wire interface
onewire_b
:
inout
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_
stb
_o
:
out
std_logic
;
direct_timestamp_
valid
_o
:
out
std_logic
;
sim_timestamp_i
:
in
t_tdc_timestamp
:
=
c_dummy_timestamp
;
sim_timestamp_valid_i
:
in
std_logic
:
=
'0'
;
...
...
@@ -386,6 +386,8 @@ begin
ts_offset_i
=>
ts_offset
,
reset_seq_i
=>
reset_seq
,
direct_timestamp_valid_o
=>
direct_timestamp_valid_o
,
direct_timestamp_o
=>
direct_timestamp_o
,
irq_threshold_o
=>
irq_threshold
,
irq_timeout_o
=>
irq_timeout
,
...
...
hdl/rtl/fmc_tdc_wrapper.vhd
View file @
abad9a6f
...
...
@@ -480,7 +480,7 @@ begin
-- 1-Wire on TDC mezzanine
onewire_b
=>
mezz_one_wire_b
,
direct_timestamp_o
=>
direct_timestamp
,
direct_timestamp_
stb
_o
=>
direct_timestamp_wr
,
direct_timestamp_
valid
_o
=>
direct_timestamp_wr
,
sim_timestamp_ready_o
=>
sim_timestamp_ready_o
,
sim_timestamp_valid_i
=>
sim_timestamp_valid_i
,
...
...
hdl/rtl/timestamp_convert_filter.vhd
View file @
abad9a6f
...
...
@@ -26,7 +26,10 @@ entity timestamp_convert_filter is
ts_offset_i
:
in
t_tdc_timestamp_array
(
4
downto
0
);
ts_o
:
out
t_tdc_timestamp_array
(
4
downto
0
);
ts_valid_o
:
buffer
std_logic_vector
(
4
downto
0
);
ts_ready_i
:
in
std_logic_vector
(
4
downto
0
)
ts_ready_i
:
in
std_logic_vector
(
4
downto
0
);
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_valid_o
:
out
std_logic
);
...
...
@@ -188,6 +191,23 @@ architecture rtl of timestamp_convert_filter is
s3_ts
.
meta
<=
s3_meta
;
p_direct_output
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_sys_n_i
=
'0'
then
direct_timestamp_valid_o
<=
'0'
;
else
direct_timestamp_o
(
31
downto
0
)
<=
s3_ts
.
tai
;
direct_timestamp_o
(
63
downto
32
)
<=
s3_ts
.
coarse
;
direct_timestamp_o
(
95
downto
64
)
<=
x"00000"
&
s3_ts
.
frac
;
direct_timestamp_o
(
96
+
2
downto
96
)
<=
s3_ts
.
channel
;
direct_timestamp_o
(
96
+
3
)
<=
s3_ts
.
slope
;
direct_timestamp_o
(
127
downto
100
)
<=
(
others
=>
'0'
);
direct_timestamp_valid_o
<=
s3_valid
;
end
if
;
end
if
;
end
process
;
gen_channels
:
for
i
in
0
to
4
generate
p_fsm
:
process
(
clk_sys_i
)
...
...
hdl/top/spec/wr_spec_tdc.vhd
View file @
abad9a6f
...
...
@@ -823,7 +823,7 @@ begin
cmp_tdc_mezzanine
:
entity
work
.
fmc_tdc_wrapper
generic
map
(
g_simulation
=>
g_simulation
,
g_with_direct_readout
=>
fals
e
,
g_with_direct_readout
=>
tru
e
,
g_use_dma_readout
=>
g_use_dma_readout
,
g_use_fake_timestamps_for_sim
=>
g_use_fake_timestamps_for_sim
)
port
map
(
...
...
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