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FMC TDC 1ns 5cha - Gateware
Commit aee4cec7 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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parent 45f22114
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Showing with 203 additions and 177 deletions
hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ aee4cec7
......@@ -536,12 +536,12 @@ begin
slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
desc_o => open,
scl_pad_i => i2c_scl_i,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => i2c_sda_i,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n);
scl_pad_i(0) => i2c_scl_i,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => i2c_sda_i,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
i2c_sda_oen_o <= sys_sda_oe_n;
......
hdl/wr_spec_tdc/hdl/rtl/reg_ctrl.vhd
View file @ aee4cec7
......@@ -145,7 +145,7 @@ entity reg_ctrl is
-- Signal to the one_hz_gen unit
load_utc_p_o : out std_logic;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
irq_tstamp_threshold_o: out std_logic_vector(g_width-1 downto 0); -- threshold in number of timestamps
irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of timestamps
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of ms
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0); -- for debug only
......@@ -167,7 +167,7 @@ end reg_ctrl;
architecture rtl of reg_ctrl is
signal acam_config : config_vector;
signal reg_adr,reg_adr_pipe0 : std_logic_vector(7 downto 0);
signal reg_adr, reg_adr_pipe0 : std_logic_vector(7 downto 0);
signal starting_utc, acam_inputs_en, start_phase : std_logic_vector(g_width-1 downto 0);
signal ctrl_reg, one_hz_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
signal irq_time_threshold : std_logic_vector(g_width-1 downto 0);
......@@ -176,9 +176,17 @@ architecture rtl of reg_ctrl is
signal pulse_extender_en : std_logic;
signal pulse_extender_c : std_logic_vector(2 downto 0);
signal dat_out, wrabbit_ctrl_reg, deactivate_chan : std_logic_vector(g_span-1 downto 0);
signal tdc_config_wb_ack_o_pipe0 : std_logic;
signal ack_out_pipe0, ack_out_pipe1 : std_logic;
signal dat_out_comb0, dat_out_comb1 : std_logic_vector(g_span-1 downto 0);
signal dat_out_comb2, dat_out_comb3 : std_logic_vector(g_span-1 downto 0);
signal dat_out_pipe0, dat_out_pipe1 : std_logic_vector(g_span-1 downto 0);
signal dat_out_pipe2, dat_out_pipe3 : std_logic_vector(g_span-1 downto 0);
signal cyc_in_progress : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -193,18 +201,23 @@ begin
-- TDCconfig_ack_generator: generation of the WISHBONE acknowledge signal for the
-- interactions with the GN4124/VME_core.
TDCconfig_ack_generator: process (clk_i)
TDCconfig_ack_generator : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
tdc_config_wb_ack_o <= '0';
tdc_config_wb_ack_o_pipe0 <= '0';
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
elsif(tdc_config_wb_cyc_i = '0') then
tdc_config_wb_ack_o <= '0';
tdc_config_wb_ack_o_pipe0 <= '0';
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
else
tdc_config_wb_ack_o <= tdc_config_wb_ack_o_pipe0;
tdc_config_wb_ack_o_pipe0 <= tdc_config_wb_stb_i and tdc_config_wb_cyc_i;
cyc_in_progress <= '1';
tdc_config_wb_ack_o <= ack_out_pipe1;
ack_out_pipe1 <= ack_out_pipe0;
ack_out_pipe0 <= tdc_config_wb_stb_i and tdc_config_wb_cyc_i and not cyc_in_progress;
end if;
end if;
end process;
......@@ -219,21 +232,21 @@ begin
-- input to the data_engine and the acam_databus_interface units for the further transfer to the
-- ACAM chip.
ACAM_config_reg_reception: process (clk_i)
ACAM_config_reg_reception : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
acam_config(0) <= (others =>'0');
acam_config(1) <= (others =>'0');
acam_config(2) <= (others =>'0');
acam_config(3) <= (others =>'0');
acam_config(4) <= (others =>'0');
acam_config(5) <= (others =>'0');
acam_config(6) <= (others =>'0');
acam_config(7) <= (others =>'0');
acam_config(8) <= (others =>'0');
acam_config(9) <= (others =>'0');
acam_config(10) <= (others =>'0');
acam_config(0) <= (others => '0');
acam_config(1) <= (others => '0');
acam_config(2) <= (others => '0');
acam_config(3) <= (others => '0');
acam_config(4) <= (others => '0');
acam_config(5) <= (others => '0');
acam_config(6) <= (others => '0');
acam_config(7) <= (others => '0');
acam_config(8) <= (others => '0');
acam_config(9) <= (others => '0');
acam_config(10) <= (others => '0');
elsif tdc_config_wb_cyc_i = '1' and tdc_config_wb_stb_i = '1' and tdc_config_wb_we_i = '1' then -- WISHBONE writes
......@@ -302,14 +315,14 @@ begin
-- o one_hz_phase : eva: think it s not used
-- o start_phase : eva: think it s not used
TDCcore_config_reg_reception: process (clk_i)
TDCcore_config_reg_reception : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' then
acam_inputs_en <= (others =>'0');
starting_utc <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
if rst_i = '1' then
acam_inputs_en <= (others => '0');
starting_utc <= (others => '0');
start_phase <= (others => '0');
one_hz_phase <= (others => '0');
irq_tstamp_threshold <= x"00000100"; -- default 256 timestamps: full memory
irq_time_threshold <= x"000000C8"; -- default 200 ms
dac_word <= c_DEFAULT_DAC_WORD; -- default DAC Vout = 1.65
......@@ -376,15 +389,15 @@ begin
-- Note that only one bit of the register should be written at a time. The process receives
-- the register, defines the action to be taken and after 1 clk cycle clears the register.
TDCcore_ctrl_reg_reception: process (clk_i)
TDCcore_ctrl_reg_reception : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
ctrl_reg <= (others =>'0');
ctrl_reg <= (others => '0');
clear_ctrl_reg <= '0';
elsif clear_ctrl_reg = '1' then
ctrl_reg <= (others =>'0');
ctrl_reg <= (others => '0');
clear_ctrl_reg <= '0';
elsif tdc_config_wb_cyc_i = '1' and tdc_config_wb_stb_i = '1' and tdc_config_wb_we_i = '1' then -- WISHBONE writes
......@@ -415,7 +428,7 @@ begin
-- Pulse_stretcher: Increases the width of the send_dac_word_p pulse so that it can be sampled
-- by the 20 MHz clock of the clks_rsts_manager that is communicating with the DAC.
Pulse_stretcher: incr_counter
Pulse_stretcher : incr_counter
generic map
(width => 3)
port map
......@@ -437,19 +450,23 @@ begin
-- including those of the ACAM and the TDC core.
-- Note: pipelining of the address for timing/slack reasons
WISHBONEreads: process (clk_i)
WISHBONEreads : process (clk_i)
begin
if rising_edge (clk_i) then
--if tdc_config_wb_cyc_i = '1' and tdc_config_wb_stb_i = '1' and tdc_config_wb_we_i = '0' then -- WISHBONE reads
-- tdc_config_wb_dat_o <= dat_out;
reg_adr_pipe0 <= reg_adr;
tdc_config_wb_dat_o <= dat_out;
dat_out_pipe0 <= dat_out_comb0;
dat_out_pipe1 <= dat_out_comb1;
dat_out_pipe2 <= dat_out_comb2;
dat_out_pipe3 <= dat_out_comb3;
tdc_config_wb_dat_o <= dat_out_pipe0 or dat_out_pipe1 or dat_out_pipe2 or dat_out_pipe3;
--end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
with reg_adr_pipe0 select dat_out <=
with reg_adr_pipe0 select dat_out_comb0 <=
-- regs written by the GN4124/VME interface
acam_config(0) when c_ACAM_REG0_ADR,
acam_config(1) when c_ACAM_REG1_ADR,
......@@ -462,6 +479,9 @@ begin
acam_config(8) when c_ACAM_REG11_ADR,
acam_config(9) when c_ACAM_REG12_ADR,
acam_config(10) when c_ACAM_REG14_ADR,
x"00000000" when others;
with reg_adr_pipe0 select dat_out_comb1 <=
-- regs read from the ACAM
acam_config_rdbk_i(0) when c_ACAM_REG0_RDBK_ADR,
acam_config_rdbk_i(1) when c_ACAM_REG1_RDBK_ADR,
......@@ -473,6 +493,9 @@ begin
acam_config_rdbk_i(7) when c_ACAM_REG7_RDBK_ADR,
acam_ififo1_i when c_ACAM_REG8_RDBK_ADR,
acam_ififo2_i when c_ACAM_REG9_RDBK_ADR,
x"00000000" when others;
with reg_adr_pipe0 select dat_out_comb2 <=
acam_start01_i when c_ACAM_REG10_RDBK_ADR,
acam_config_rdbk_i(8) when c_ACAM_REG11_RDBK_ADR,
acam_config_rdbk_i(9) when c_ACAM_REG12_RDBK_ADR,
......@@ -485,6 +508,9 @@ begin
irq_tstamp_threshold when c_IRQ_TSTAMP_THRESH_ADR,
irq_time_threshold when c_IRQ_TIME_THRESH_ADR,
x"00" & dac_word when c_DAC_WORD_ADR,
x"00000000" when others;
with reg_adr_pipe0 select dat_out_comb3 <=
-- regs written locally by the TDC core units
local_utc_i when c_LOCAL_UTC_ADR,
irq_code_i when c_IRQ_CODE_ADR,
......@@ -495,7 +521,7 @@ begin
wrabbit_ctrl_reg when c_WRABBIT_CTRL_ADR,
deactivate_chan when c_DEACT_CHAN_ADR,
-- others
x"C0FFEEEE" when others;
x"00000000" when others;
end architecture rtl;
......
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