Commit b10c63a4 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'greg-wrpc-v4.2'

parents b2433b14 c8b144e8
...@@ -7,5 +7,9 @@ modelsim.ini ...@@ -7,5 +7,9 @@ modelsim.ini
*.vstf *.vstf
work work
*.bak *.bak
syn/* hdl/syn/*
transcript transcript
\ No newline at end of file work/
NullFile
*.orig
*.html
\ No newline at end of file
...@@ -10,3 +10,6 @@ ...@@ -10,3 +10,6 @@
[submodule "hdl/ip_cores/gn4124-core"] [submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
etherbone-core @ 84894459
Subproject commit 8489445985ff2afe6c72712014a92a271869f20a
general-cores @ 5205d975
Subproject commit 29db1b2af734d9a9e530cb4dbeb2ec56f9f38980 Subproject commit 5205d9754b1e0887df5914a47f8aa745e4f3c2fe
gn4124-core @ 9b9625bb
Subproject commit 7082c5833a2569b24ad69d5f94269eaeff1c7af3 Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
vme64x-core @ fa34d06e
Subproject commit d8ae98675b15a5dc6bf5cc9e7e3fcbdd266187f7 Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
wr-cores @ 69cc4cc3
Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07
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...@@ -113,7 +113,7 @@ begin ...@@ -113,7 +113,7 @@ begin
regs_i => regs_in, regs_i => regs_in,
regs_o => regs_out); regs_o => regs_out);
buf_count <= unsigned(regs_out.fifo_wr_usedw_o); buf_count <= resize(unsigned(regs_out.fifo_wr_usedw_o), 10);
ts_match <= '1' when timestamp_valid_i = '1' and unsigned(timestamp_i(98 downto 96)) = g_channel else '0'; ts_match <= '1' when timestamp_valid_i = '1' and unsigned(timestamp_i(98 downto 96)) = g_channel else '0';
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wb.vhd -- File : timestamp_fifo_wb.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb -- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Mon Apr 20 17:34:12 2015 -- Created : Wed Sep 20 18:41:08 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
...@@ -89,26 +89,16 @@ signal tsf_csr_rst_seq_sync2 : std_logic ; ...@@ -89,26 +89,16 @@ signal tsf_csr_rst_seq_sync2 : std_logic ;
signal tsf_fifo_full_int : std_logic ; signal tsf_fifo_full_int : std_logic ;
signal tsf_fifo_empty_int : std_logic ; signal tsf_fifo_empty_int : std_logic ;
signal tsf_fifo_clear_bus_int : std_logic ; signal tsf_fifo_clear_bus_int : std_logic ;
signal tsf_fifo_usedw_int : std_logic_vector(9 downto 0); signal tsf_fifo_usedw_int : std_logic_vector(8 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0); signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ; signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards. -- Some internal signals assignments
wrdata_reg <= wb_dat_i; wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
-- --
-- Main register bank access process. -- Main register bank access process.
process (clk_sys_i, rst_n_i) process (clk_sys_i, rst_n_i)
...@@ -310,7 +300,8 @@ begin ...@@ -310,7 +300,8 @@ begin
rddata_reg(16) <= tsf_fifo_full_int; rddata_reg(16) <= tsf_fifo_full_int;
rddata_reg(17) <= tsf_fifo_empty_int; rddata_reg(17) <= tsf_fifo_empty_int;
rddata_reg(18) <= '0'; rddata_reg(18) <= '0';
rddata_reg(9 downto 0) <= tsf_fifo_usedw_int; rddata_reg(8 downto 0) <= tsf_fifo_usedw_int;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(12) <= 'X';
...@@ -353,9 +344,9 @@ begin ...@@ -353,9 +344,9 @@ begin
tsf_fifo_rst_n <= rst_n_i and (not tsf_fifo_clear_bus_int); tsf_fifo_rst_n <= rst_n_i and (not tsf_fifo_clear_bus_int);
tsf_fifo_INST : wbgen2_fifo_async tsf_fifo_INST : wbgen2_fifo_async
generic map ( generic map (
g_size => 1024, g_size => 512,
g_width => 128, g_width => 128,
g_usedw_size => 10 g_usedw_size => 9
) )
port map ( port map (
wr_req_i => regs_i.fifo_wr_req_i, wr_req_i => regs_i.fifo_wr_req_i,
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd -- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb -- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Mon Apr 20 17:34:12 2015 -- Created : Wed Sep 20 18:41:08 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
...@@ -51,7 +51,7 @@ package tsf_wbgen2_pkg is ...@@ -51,7 +51,7 @@ package tsf_wbgen2_pkg is
type t_tsf_out_registers is record type t_tsf_out_registers is record
fifo_wr_full_o : std_logic; fifo_wr_full_o : std_logic;
fifo_wr_empty_o : std_logic; fifo_wr_empty_o : std_logic;
fifo_wr_usedw_o : std_logic_vector(9 downto 0); fifo_wr_usedw_o : std_logic_vector(8 downto 0);
csr_last_valid_o : std_logic; csr_last_valid_o : std_logic;
csr_last_valid_load_o : std_logic; csr_last_valid_load_o : std_logic;
csr_rst_seq_o : std_logic; csr_rst_seq_o : std_logic;
......
...@@ -9,7 +9,7 @@ peripheral { ...@@ -9,7 +9,7 @@ peripheral {
-- TXTSU shared FIFO -- TXTSU shared FIFO
fifo_reg { fifo_reg {
size = 1024; -- or more. We'll see :) size = 512; -- or more. We'll see :)
direction = CORE_TO_BUS; direction = CORE_TO_BUS;
prefix = "fifo"; prefix = "fifo";
name = "Timestamp FIFO"; name = "Timestamp FIFO";
......
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...@@ -8,5 +8,6 @@ syn_grade = "-3" ...@@ -8,5 +8,6 @@ syn_grade = "-3"
syn_package = "fgg900" syn_package = "fgg900"
syn_top = "wr_svec_tdc" syn_top = "wr_svec_tdc"
syn_project = "wr_svec_tdc.xise" syn_project = "wr_svec_tdc.xise"
syn_tool = "ise"
modules = { "local" : [ "../../top/svec" ] } modules = { "local" : [ "../../top/svec" ] }
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...@@ -8,7 +8,11 @@ modules = { ...@@ -8,7 +8,11 @@ modules = {
"local" : [ "../../rtl/", "local" : [ "../../rtl/",
"../../ip_cores/gn4124-core", "../../ip_cores/gn4124-core",
"../../ip_cores/general-cores", "../../ip_cores/general-cores",
"../../ip_cores/wr-cores" "../../ip_cores/wr-cores",
] "../../ip_cores/wr-cores/board/spec"
],
"git" : [
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
} }
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor -- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha) -- Project : TDC FMC (fmc-tdc-1ns-5cha)
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd -- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou -- Author : Evangelia Gousiou
-- Company : CERN -- Company : CERN
-- Created : 2013-04-16 -- Created : 2013-04-16
-- Last update: 2013-04-16 -- Last update: 2017-09-20
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier. -- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information. -- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed. -- Warning: this file is modified whenever a synthesis is executed.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2013 CERN / BE-CO-HT -- Copyright (c) 2013 CERN / BE-CO-HT
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation; -- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any -- either version 2.1 of the License, or (at your option) any
-- later version. -- later version.
-- --
-- This source is distributed in the hope that it will be -- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more -- PURPOSE. See the GNU Lesser General Public License for more
-- details. -- details.
-- --
-- You should have received a copy of the GNU Lesser General -- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it -- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html -- from http://www.gnu.org/licenses/lgpl-2.1.html
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.STD_LOGIC_1164.all; use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
package synthesis_descriptor is package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis := constant c_sdb_synthesis_info : t_sdb_synthesis :=
( (
syn_module_name => "wr_spec_tdc ", syn_module_name => "wr_spec_tdc ",
syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75", syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
syn_tool_name => "ISE ", syn_tool_name => "ISE ",
syn_tool_version => x"00000147", syn_tool_version => x"00000147",
syn_date => x"20150522", syn_date => x"20170920",
syn_username => "twlostow "); syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url := constant c_sdb_repo_url : t_sdb_repo_url :=
( (
repo_url => "http://svn.ohwr.org/fmc-tdc " repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git "
); );
end package synthesis_descriptor; end package synthesis_descriptor;
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...@@ -8,7 +8,13 @@ modules = { ...@@ -8,7 +8,13 @@ modules = {
"local" : [ "../../rtl/", "local" : [ "../../rtl/",
"../../ip_cores/vme64x-core", "../../ip_cores/vme64x-core",
"../../ip_cores/general-cores", "../../ip_cores/general-cores",
"../../ip_cores/wr-cores" "../../ip_cores/wr-cores",
] "../../ip_cores/wr-cores/board/svec"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
} }
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Evangelia Gousiou -- Author : Evangelia Gousiou
-- Company : CERN -- Company : CERN
-- Created : 2013-04-16 -- Created : 2013-04-16
-- Last update: 2015-04-08 -- Last update: 2015-05-27
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -46,12 +46,12 @@ constant c_sdb_synthesis_info : t_sdb_synthesis := ...@@ -46,12 +46,12 @@ constant c_sdb_synthesis_info : t_sdb_synthesis :=
syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75", syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
syn_tool_name => "ISE ", syn_tool_name => "ISE ",
syn_tool_version => x"00000147", syn_tool_version => x"00000147",
syn_date => x"20150522", syn_date => x"20150527",
syn_username => "twlostow "); syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url := constant c_sdb_repo_url : t_sdb_repo_url :=
( (
repo_url => "http://svn.ohwr.org/fmc-tdc " repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git "
); );
end package synthesis_descriptor; end package synthesis_descriptor;
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