Commit b5af3b6c authored by penacoba's avatar penacoba

Memory core generated by coregen.


git-svn-id: http://svn.ohwr.org/fmc-tdc@47 85dfdc96-de2c-444c-878d-45b388be74a9
parent 4af69194
Core name: Xilinx LogiCORE Block Memory Generator
Version: 6.1
Release Date: March 01 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the IP installation instructions for this core,please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Block Memory
Generator v6.1 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
2. NEW FEATURES
- ISE 13.1 Software support
- Virtex-7 and Kintex-7 device support
- AXI4/AXI4-Lite interface support for Virtex-6 and Spartan-6 devices
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
- Virtex-7
- Kintex-7
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Virtex-5 XC LX/LXT/SXT/TXT/FXT
- Virtex-5 XQ LX/ LXT/SXT/FXT
- Virtex-4 XC LX/SX/FX
- Virtex-4 XQ LX/SX/FX
- Virtex-4 XQR LX/SX/FX
- Spartan-3 XC
- Spartan-3 XA
- Spartan-3A XC 3A / 3A DSP / 3AN DSP
- Spartan-3A XA 3A / 3A DSP
- Spartan-3E XC
- Spartan-3E XA
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v6.1:
a. "Fill remaining memory locations" - option disabled in GUI
- Version fixed : 6.1
1.Core does not allow the customer to use the "remaining memory locations" option.
Solution: "Fill remaining memory locations" - option enbaled in GUI
- CR 575015
- AR 37944
5. KNOWN ISSUES
The following are known issues for v6.1 of this core at time of release:
a. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
Workaround: Generate two shallower FIFOs and pass the appropriate address
lines to implement the FIFO of the required depth
- CR587481
- AR 39718
b. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
Solution: The user must review the possible scenarios that causes the collission and revise
their design to avoid those situations.
- CR588505
Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
Write Mode = Read First in conjunction with asynchronous clocking
c. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
d. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
e. Out-of-range address input can cause the core to generate X's on the DOUT bus
- AR 23744
f. When the IP core is generated for Spartan-6 devices, the core does not combine
two adjacent 9k BRAMs into one 18K BRAM.
- CR 526429
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
10/29/2010 Xilinx, Inc. 5.2 ISE 13.0.2 support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/30/2010 Xilinx, Inc. 5.1 ISE 13.0.1 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="blk_mem_gen_v6_1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_1.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
This diff is collapsed.
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v6_1.vhd when simulating
-- the core, blk_mem_gen_v6_1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v6_1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END blk_mem_gen_v6_1;
ARCHITECTURE blk_mem_gen_v6_1_a OF blk_mem_gen_v6_1 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v6_1
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v6_1 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_1(behavioral)
GENERIC MAP (
c_addra_width => 9,
c_addrb_width => 9,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 1,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 512,
c_read_depth_b => 512,
c_read_width_a => 32,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 512,
c_write_depth_b => 512,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 32,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v6_1
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END blk_mem_gen_v6_1_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.
-- Interfaces:
-- AXI4_SLAVE_S_AXI
-- AXILite_SLAVE_S_AXI
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT blk_mem_gen_v6_1
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : blk_mem_gen_v6_1
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file blk_mem_gen_v6_1.vhd when simulating
-- the core, blk_mem_gen_v6_1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
##############################################################
#
# Xilinx Core Generator version 13.1
# Date: Tue Oct 4 17:14:15 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatParenNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Synplicity
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=blk_mem_gen_v6_1
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=32
CSET read_width_b=32
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=true
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=512
CSET write_width_a=32
CSET write_width_b=32
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-02-03T22:20:43.000Z
# END Extra information
GENERATE
# CRC: 23a3dcc
This diff is collapsed.
# Output products list for <blk_mem_gen_v6_1>
blk_mem_gen_ds512.pdf
blk_mem_gen_readme.txt
blk_mem_gen_v6_1.gise
blk_mem_gen_v6_1.ngc
blk_mem_gen_v6_1.vhd
blk_mem_gen_v6_1.vho
blk_mem_gen_v6_1.xco
blk_mem_gen_v6_1.xise
blk_mem_gen_v6_1_flist.txt
blk_mem_gen_v6_1_xmdf.tcl
# The package naming convention is <core_name>_xmdf
package provide blk_mem_gen_v6_1_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::blk_mem_gen_v6_1_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::blk_mem_gen_v6_1_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name blk_mem_gen_v6_1
}
# ::blk_mem_gen_v6_1_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::blk_mem_gen_v6_1_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_1.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_1.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_1.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_1.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_1_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blk_mem_gen_v6_1
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="blk_mem_gen_v6_2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_2.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
This diff is collapsed.
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --