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FMC TDC 1ns 5cha - Gateware
Commit c2a10e64 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: independent FIFO buffers per channel - top level verified on the SVEC

parent 8b800231
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hdl/rtl/data_formatting.vhd
View file @ c2a10e64
......@@ -137,7 +137,7 @@ architecture rtl of data_formatting is
signal un_current_retrig_from_roll_over : unsigned(31 downto 0);
signal un_acam_fine_time : unsigned(31 downto 0);
signal previous_utc : std_logic_vector(31 downto 0);
signal timestamp_valid_int : std_logic;
--=================================================================================================
-- architecture begin
......@@ -149,9 +149,9 @@ begin
begin
if rising_edge (clk_i) then
if rst_i = '1' then
timestamp_valid_o <= '0';
timestamp_valid_int <= '0';
else
timestamp_valid_o <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i;
timestamp_valid_int <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i;
end if;
end if;
end process;
......@@ -333,8 +333,15 @@ begin
full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(95 downto 64) <= utc;
full_timestamp(127 downto 96) <= metadata;
timestamp_o <= full_timestamp;
process(clk_i)
begin
if rising_edge(clk_i) then
timestamp_o <= full_timestamp;
timestamp_valid_o <= timestamp_valid_int;
end if;
end process;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_core.vhd
View file @ c2a10e64
......@@ -549,7 +549,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
---------------------------------------------------------------------------------------------------
start_dis_o <= '0';
channel_enable_o <= acam_inputs_en(4 downto 0);
channel_enable_o <= acam_inputs_en(20 downto 16);
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ c2a10e64
......@@ -416,9 +416,6 @@ begin
end generate gen_fifos;
irq_tstamp <= '1' when unsigned(irq_channel) /= 0 else '0';
p_gen_1ms_tick : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
......@@ -515,21 +512,23 @@ begin
-- 2 -> ACAM error
cmp_tdc_eic : tdc_eic
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall,
wb_int_o => wb_irq_o,
irq_tdc_tstamps_i => irq_tstamp,
irq_tdc_time_i => '0',
irq_tdc_acam_err_i => '0');
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall,
wb_int_o => wb_irq_o,
irq_tdc_fifo1_i => irq_channel(0),
irq_tdc_fifo2_i => irq_channel(1),
irq_tdc_fifo3_i => irq_channel(2),
irq_tdc_fifo4_i => irq_channel(3),
irq_tdc_fifo5_i => irq_channel(4));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
......
hdl/rtl/tdc_core_pkg.vhd
View file @ c2a10e64
......@@ -726,24 +726,25 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component tdc_eic
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_tdc_tstamps_i : in std_logic;
irq_tdc_time_i : in std_logic;
irq_tdc_acam_err_i : in std_logic);
component tdc_eic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_tdc_fifo1_i : in std_logic;
irq_tdc_fifo2_i : in std_logic;
irq_tdc_fifo3_i : in std_logic;
irq_tdc_fifo4_i : in std_logic;
irq_tdc_fifo5_i : in std_logic);
end component tdc_eic;
......
hdl/rtl/tdc_eic.vhd
View file @ c2a10e64
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC EIC
---------------------------------------------------------------------------------------
-- File : output.vhd
-- Author : auto-generated by wbgen2 from tdc_eic.wb
-- Created : 01/21/14 15:13:26
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_eic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity tdc_eic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_tdc_tstamps_i : in std_logic;
irq_tdc_time_i : in std_logic;
irq_tdc_acam_err_i : in std_logic
);
end tdc_eic;
architecture syn of tdc_eic is
signal eic_idr_int : std_logic_vector(2 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(2 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(2 downto 0);
signal eic_isr_clear_int : std_logic_vector(2 downto 0);
signal eic_isr_status_int : std_logic_vector(2 downto 0);
signal eic_irq_ack_int : std_logic_vector(2 downto 0);
signal eic_isr_write_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(2 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(2 downto 0) <= eic_imr_int(2 downto 0);
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(2 downto 0) <= eic_isr_status_int(2 downto 0);
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 3,
g_irq00_mode => 0,
g_irq01_mode => 0,
g_irq02_mode => 0,
g_irq03_mode => 0,
g_irq04_mode => 0,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_tdc_tstamps_i;
irq_inputs_vector_int(1) <= irq_tdc_time_i;
irq_inputs_vector_int(2) <= irq_tdc_acam_err_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC EIC
---------------------------------------------------------------------------------------
-- File : tdc_eic.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_eic.wb
-- Created : Mon Apr 20 17:34:12 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_eic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity tdc_eic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_tdc_fifo1_i : in std_logic;
irq_tdc_fifo2_i : in std_logic;
irq_tdc_fifo3_i : in std_logic;
irq_tdc_fifo4_i : in std_logic;
irq_tdc_fifo5_i : in std_logic
);
end tdc_eic;
architecture syn of tdc_eic is
signal eic_idr_int : std_logic_vector(4 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(4 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(4 downto 0);
signal eic_isr_clear_int : std_logic_vector(4 downto 0);
signal eic_isr_status_int : std_logic_vector(4 downto 0);
signal eic_irq_ack_int : std_logic_vector(4 downto 0);
signal eic_isr_write_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(4 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= eic_imr_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(4 downto 0) <= eic_isr_status_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(4 downto 0) <= wrdata_reg(4 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 5,
g_irq00_mode => 3,
g_irq01_mode => 3,
g_irq02_mode => 3,
g_irq03_mode => 3,
g_irq04_mode => 3,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_tdc_fifo1_i;
irq_inputs_vector_int(1) <= irq_tdc_fifo2_i;
irq_inputs_vector_int(2) <= irq_tdc_fifo3_i;
irq_inputs_vector_int(3) <= irq_tdc_fifo4_i;
irq_inputs_vector_int(4) <= irq_tdc_fifo5_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/timestamp_fifo.vhd
View file @ c2a10e64
......@@ -85,8 +85,17 @@ architecture rtl of timestamp_fifo is
signal channel_id : std_logic_vector(2 downto 0);
signal ts_match : std_logic;
signal seq_counter : unsigned(31 downto 0);
signal timestamp_with_seq : std_logic_vector(127 downto 0);
begin
timestamp_with_seq(95 downto 0) <= timestamp_i(95 downto 0); -- TS
timestamp_with_seq(98 downto 96) <= timestamp_i(98 downto 96); -- channel
timestamp_with_seq(100) <= timestamp_i(100); -- slope
timestamp_with_seq(127 downto 101) <= std_logic_vector(seq_counter(26 downto 0));
U_WB_Slave : timestamp_fifo_wb
port map (
rst_n_i => rst_n_sys_i,
......@@ -114,6 +123,7 @@ begin
if rst_tdc_i = '1' then
regs_in.fifo_wr_req_i <= '0';
else
if(enable_i = '1' and regs_out.fifo_wr_full_o = '0' and ts_match = '1') then
regs_in.fifo_wr_req_i <= '1';
else
......@@ -123,24 +133,43 @@ begin
end if;
end process;
regs_in.fifo_ts0_i <= timestamp_with_seq(31 downto 0);
regs_in.fifo_ts1_i <= timestamp_with_seq(63 downto 32);
regs_in.fifo_ts2_i <= timestamp_with_seq(95 downto 64);
regs_in.fifo_ts3_i <= timestamp_with_seq(127 downto 96);
p_seq_counter : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' or regs_out.csr_rst_seq_o = '1' then
seq_counter <= (others => '0');
else
if(enable_i = '1' and ts_match = '1') then
seq_counter <= seq_counter + 1;
end if;
end if;
end if;
end process;
p_latch_last_timestamp : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
regs_in.ltsctl_valid_i <= '0';
regs_in.csr_last_valid_i <= '0';
else
if (enable_i = '1' and ts_match = '1') then
regs_in.ltsctl_valid_i <= '1';
last_ts <= timestamp_i;
elsif (regs_out.ltsctl_valid_o = '0' and regs_out.ltsctl_valid_load_o = '1') then
regs_in.ltsctl_valid_i <= '0';
-- latch only the last rising edge TS
if (enable_i = '1' and ts_match = '1' and timestamp_with_seq(100) = '1') then
regs_in.csr_last_valid_i <= '1';
last_ts <= timestamp_with_seq;
elsif (regs_out.csr_last_valid_o = '0' and regs_out.csr_last_valid_load_o = '1') then
regs_in.csr_last_valid_i <= '0';
end if;
if (regs_out.ltsctl_valid_o = '0' and regs_out.ltsctl_valid_load_o = '1') then
regs_in.lts0_i <= last_ts(127 downto 96);
regs_in.lts1_i <= last_ts(95 downto 64);
regs_in.lts2_i <= last_ts(63 downto 32);
regs_in.lts3_i <= last_ts(31 downto 0);
if (regs_out.csr_last_valid_o = '0' and regs_out.csr_last_valid_load_o = '1') then
regs_in.lts0_i <= last_ts(31 downto 0);
regs_in.lts1_i <= last_ts(63 downto 32);
regs_in.lts2_i <= last_ts(95 downto 64);
regs_in.lts3_i <= last_ts(127 downto 96);
end if;
end if;
end if;
......@@ -152,7 +181,7 @@ begin
if rst_tdc_i = '1' or enable_i = '0' then
buf_irq_int <= '0';
else
if(buf_count = 0) then
if(regs_out.fifo_wr_empty_o = '1') then
buf_irq_int <= '0';
tmr_timeout <= (others => '0');
else
......@@ -172,7 +201,7 @@ begin
-- Case 2: amount of data exceeded the threshold - assert the IRQ
-- line immediately.
if(buf_count > unsigned(irq_threshold_i(9 downto 0))) then
if(regs_out.fifo_wr_full_o = '1' or (buf_count > unsigned(irq_threshold_i(9 downto 0)))) then
buf_irq_int <= '1';
end if;
end if;
......
hdl/rtl/timestamp_fifo_wb.vhd
View file @ c2a10e64
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Timestamp FIFO
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wb.vhd
-- Author : auto-generated by wbgen2 from timestamp_fifo_wb.wb
-- Created : Tue Apr 14 16:47:08 2015
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Mon Apr 20 17:34:12 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timestamp_fifo_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -72,17 +72,23 @@ signal tsf_lts3_lwb_in_progress : std_logic ;
signal tsf_lts3_lwb_s0 : std_logic ;
signal tsf_lts3_lwb_s1 : std_logic ;
signal tsf_lts3_lwb_s2 : std_logic ;
signal tsf_ltsctl_valid_int_read : std_logic ;
signal tsf_ltsctl_valid_int_write : std_logic ;
signal tsf_ltsctl_valid_lw : std_logic ;
signal tsf_ltsctl_valid_lw_delay : std_logic ;
signal tsf_ltsctl_valid_lw_read_in_progress : std_logic ;
signal tsf_ltsctl_valid_lw_s0 : std_logic ;
signal tsf_ltsctl_valid_lw_s1 : std_logic ;
signal tsf_ltsctl_valid_lw_s2 : std_logic ;
signal tsf_ltsctl_valid_rwsel : std_logic ;
signal tsf_csr_last_valid_int_read : std_logic ;
signal tsf_csr_last_valid_int_write : std_logic ;
signal tsf_csr_last_valid_lw : std_logic ;
signal tsf_csr_last_valid_lw_delay : std_logic ;
signal tsf_csr_last_valid_lw_read_in_progress : std_logic ;
signal tsf_csr_last_valid_lw_s0 : std_logic ;
signal tsf_csr_last_valid_lw_s1 : std_logic ;
signal tsf_csr_last_valid_lw_s2 : std_logic ;
signal tsf_csr_last_valid_rwsel : std_logic ;
signal tsf_csr_rst_seq_int : std_logic ;
signal tsf_csr_rst_seq_int_delay : std_logic ;
signal tsf_csr_rst_seq_sync0 : std_logic ;
signal tsf_csr_rst_seq_sync1 : std_logic ;
signal tsf_csr_rst_seq_sync2 : std_logic ;
signal tsf_fifo_full_int : std_logic ;
signal tsf_fifo_empty_int : std_logic ;
signal tsf_fifo_clear_bus_int : std_logic ;
signal tsf_fifo_usedw_int : std_logic_vector(9 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
......@@ -123,11 +129,14 @@ begin
tsf_lts3_lwb <= '0';
tsf_lts3_lwb_delay <= '0';
tsf_lts3_lwb_in_progress <= '0';
tsf_ltsctl_valid_lw <= '0';
tsf_ltsctl_valid_lw_delay <= '0';
tsf_ltsctl_valid_lw_read_in_progress <= '0';
tsf_ltsctl_valid_rwsel <= '0';
tsf_ltsctl_valid_int_write <= '0';
tsf_csr_last_valid_lw <= '0';
tsf_csr_last_valid_lw_delay <= '0';
tsf_csr_last_valid_lw_read_in_progress <= '0';
tsf_csr_last_valid_rwsel <= '0';
tsf_csr_last_valid_int_write <= '0';
tsf_csr_rst_seq_int <= '0';
tsf_csr_rst_seq_int_delay <= '0';
tsf_fifo_clear_bus_int <= '0';
tsf_fifo_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -135,6 +144,7 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tsf_fifo_clear_bus_int <= '0';
ack_in_progress <= '0';
else
tsf_lts0_lwb <= tsf_lts0_lwb_delay;
......@@ -161,12 +171,14 @@ begin
rddata_reg(31 downto 0) <= tsf_lts3_int;
tsf_lts3_lwb_in_progress <= '0';
end if;
tsf_ltsctl_valid_lw <= tsf_ltsctl_valid_lw_delay;
tsf_ltsctl_valid_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_ltsctl_valid_lw_read_in_progress = '1')) then
rddata_reg(0) <= tsf_ltsctl_valid_int_read;
tsf_ltsctl_valid_lw_read_in_progress <= '0';
tsf_csr_last_valid_lw <= tsf_csr_last_valid_lw_delay;
tsf_csr_last_valid_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_csr_last_valid_lw_read_in_progress = '1')) then
rddata_reg(0) <= tsf_csr_last_valid_int_read;
tsf_csr_last_valid_lw_read_in_progress <= '0';
end if;
tsf_csr_rst_seq_int <= tsf_csr_rst_seq_int_delay;
tsf_csr_rst_seq_int_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -213,20 +225,22 @@ begin
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
tsf_ltsctl_valid_int_write <= wrdata_reg(0);
tsf_ltsctl_valid_lw <= '1';
tsf_ltsctl_valid_lw_delay <= '1';
tsf_ltsctl_valid_lw_read_in_progress <= '0';
tsf_ltsctl_valid_rwsel <= '1';
tsf_csr_last_valid_int_write <= wrdata_reg(0);
tsf_csr_last_valid_lw <= '1';
tsf_csr_last_valid_lw_delay <= '1';
tsf_csr_last_valid_lw_read_in_progress <= '0';
tsf_csr_last_valid_rwsel <= '1';
tsf_csr_rst_seq_int <= wrdata_reg(1);
tsf_csr_rst_seq_int_delay <= wrdata_reg(1);
end if;
if (wb_we_i = '0') then
rddata_reg(0) <= 'X';
tsf_ltsctl_valid_lw <= '1';
tsf_ltsctl_valid_lw_delay <= '1';
tsf_ltsctl_valid_lw_read_in_progress <= '1';
tsf_ltsctl_valid_rwsel <= '0';
tsf_csr_last_valid_lw <= '1';
tsf_csr_last_valid_lw_delay <= '1';
tsf_csr_last_valid_lw_read_in_progress <= '1';
tsf_csr_last_valid_rwsel <= '0';
end if;
rddata_reg(1) <= 'X';
rddata_reg(1) <= '0';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
......@@ -265,194 +279,37 @@ begin
if (tsf_fifo_rdreq_int_d0 = '0') then
tsf_fifo_rdreq_int <= not tsf_fifo_rdreq_int;
else
rddata_reg(31 downto 0) <= tsf_fifo_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
when "0110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 0) <= tsf_fifo_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 0) <= tsf_fifo_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(31 downto 0) <= tsf_fifo_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
if (wrdata_reg(18) = '1') then
tsf_fifo_clear_bus_int <= '1';
end if;
end if;
rddata_reg(16) <= tsf_fifo_full_int;
rddata_reg(17) <= tsf_fifo_empty_int;
rddata_reg(18) <= '0';
rddata_reg(9 downto 0) <= tsf_fifo_usedw_int;
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -460,7 +317,6 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
......@@ -490,8 +346,11 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Timestamp FIFO
tsf_fifo_in_int(127 downto 0) <= regs_i.fifo_value_i;
tsf_fifo_rst_n <= rst_n_i;
tsf_fifo_in_int(31 downto 0) <= regs_i.fifo_ts0_i;
tsf_fifo_in_int(63 downto 32) <= regs_i.fifo_ts1_i;
tsf_fifo_in_int(95 downto 64) <= regs_i.fifo_ts2_i;
tsf_fifo_in_int(127 downto 96) <= regs_i.fifo_ts3_i;
tsf_fifo_rst_n <= rst_n_i and (not tsf_fifo_clear_bus_int);
tsf_fifo_INST : wbgen2_fifo_async
generic map (
g_size => 1024,
......@@ -599,31 +458,48 @@ begin
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_ltsctl_valid_lw_s0 <= '0';
tsf_ltsctl_valid_lw_s1 <= '0';
tsf_ltsctl_valid_lw_s2 <= '0';
tsf_ltsctl_valid_int_read <= '0';
regs_o.ltsctl_valid_load_o <= '0';
regs_o.ltsctl_valid_o <= '0';
tsf_csr_last_valid_lw_s0 <= '0';
tsf_csr_last_valid_lw_s1 <= '0';
tsf_csr_last_valid_lw_s2 <= '0';
tsf_csr_last_valid_int_read <= '0';
regs_o.csr_last_valid_load_o <= '0';
regs_o.csr_last_valid_o <= '0';
elsif rising_edge(clk_tdc_i) then
tsf_ltsctl_valid_lw_s0 <= tsf_ltsctl_valid_lw;
tsf_ltsctl_valid_lw_s1 <= tsf_ltsctl_valid_lw_s0;
tsf_ltsctl_valid_lw_s2 <= tsf_ltsctl_valid_lw_s1;
if ((tsf_ltsctl_valid_lw_s2 = '0') and (tsf_ltsctl_valid_lw_s1 = '1')) then
if (tsf_ltsctl_valid_rwsel = '1') then
regs_o.ltsctl_valid_o <= tsf_ltsctl_valid_int_write;
regs_o.ltsctl_valid_load_o <= '1';
tsf_csr_last_valid_lw_s0 <= tsf_csr_last_valid_lw;
tsf_csr_last_valid_lw_s1 <= tsf_csr_last_valid_lw_s0;
tsf_csr_last_valid_lw_s2 <= tsf_csr_last_valid_lw_s1;
if ((tsf_csr_last_valid_lw_s2 = '0') and (tsf_csr_last_valid_lw_s1 = '1')) then
if (tsf_csr_last_valid_rwsel = '1') then
regs_o.csr_last_valid_o <= tsf_csr_last_valid_int_write;
regs_o.csr_last_valid_load_o <= '1';
else
regs_o.ltsctl_valid_load_o <= '0';
tsf_ltsctl_valid_int_read <= regs_i.ltsctl_valid_i;
regs_o.csr_last_valid_load_o <= '0';
tsf_csr_last_valid_int_read <= regs_i.csr_last_valid_i;
end if;
else
regs_o.ltsctl_valid_load_o <= '0';
regs_o.csr_last_valid_load_o <= '0';
end if;
end if;
end process;
-- Reset Sequence Counter
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.csr_rst_seq_o <= '0';
tsf_csr_rst_seq_sync0 <= '0';
tsf_csr_rst_seq_sync1 <= '0';
tsf_csr_rst_seq_sync2 <= '0';
elsif rising_edge(clk_tdc_i) then
tsf_csr_rst_seq_sync0 <= tsf_csr_rst_seq_int;
tsf_csr_rst_seq_sync1 <= tsf_csr_rst_seq_sync0;
tsf_csr_rst_seq_sync2 <= tsf_csr_rst_seq_sync1;
regs_o.csr_rst_seq_o <= tsf_csr_rst_seq_sync2 and (not tsf_csr_rst_seq_sync1);
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 0
process (clk_sys_i, rst_n_i)
begin
......@@ -638,7 +514,6 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 4
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
View file @ c2a10e64
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Timestamp FIFO
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from timestamp_fifo_wb.wb
-- Created : Tue Apr 14 16:47:08 2015
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Mon Apr 20 17:34:12 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timestamp_fifo_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -22,22 +22,28 @@ package tsf_wbgen2_pkg is
type t_tsf_in_registers is record
fifo_wr_req_i : std_logic;
fifo_value_i : std_logic_vector(127 downto 0);
fifo_ts0_i : std_logic_vector(31 downto 0);
fifo_ts1_i : std_logic_vector(31 downto 0);
fifo_ts2_i : std_logic_vector(31 downto 0);
fifo_ts3_i : std_logic_vector(31 downto 0);
lts0_i : std_logic_vector(31 downto 0);
lts1_i : std_logic_vector(31 downto 0);
lts2_i : std_logic_vector(31 downto 0);
lts3_i : std_logic_vector(31 downto 0);
ltsctl_valid_i : std_logic;
csr_last_valid_i : std_logic;
end record;
constant c_tsf_in_registers_init_value: t_tsf_in_registers := (
fifo_wr_req_i => '0',
fifo_value_i => (others => '0'),
fifo_ts0_i => (others => '0'),
fifo_ts1_i => (others => '0'),
fifo_ts2_i => (others => '0'),
fifo_ts3_i => (others => '0'),
lts0_i => (others => '0'),
lts1_i => (others => '0'),
lts2_i => (others => '0'),
lts3_i => (others => '0'),
ltsctl_valid_i => '0'
csr_last_valid_i => '0'
);
-- Output registers (WB slave -> user design)
......@@ -46,16 +52,18 @@ package tsf_wbgen2_pkg is
fifo_wr_full_o : std_logic;
fifo_wr_empty_o : std_logic;
fifo_wr_usedw_o : std_logic_vector(9 downto 0);
ltsctl_valid_o : std_logic;
ltsctl_valid_load_o : std_logic;
csr_last_valid_o : std_logic;
csr_last_valid_load_o : std_logic;
csr_rst_seq_o : std_logic;
end record;
constant c_tsf_out_registers_init_value: t_tsf_out_registers := (
fifo_wr_full_o => '0',
fifo_wr_empty_o => '0',
fifo_wr_usedw_o => (others => '0'),
ltsctl_valid_o => '0',
ltsctl_valid_load_o => '0'
csr_last_valid_o => '0',
csr_last_valid_load_o => '0',
csr_rst_seq_o => '0'
);
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -87,12 +95,15 @@ function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is
variable tmp: t_tsf_in_registers;
begin
tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
tmp.fifo_value_i := f_x_to_zero(left.fifo_value_i) or f_x_to_zero(right.fifo_value_i);
tmp.fifo_ts0_i := f_x_to_zero(left.fifo_ts0_i) or f_x_to_zero(right.fifo_ts0_i);
tmp.fifo_ts1_i := f_x_to_zero(left.fifo_ts1_i) or f_x_to_zero(right.fifo_ts1_i);
tmp.fifo_ts2_i := f_x_to_zero(left.fifo_ts2_i) or f_x_to_zero(right.fifo_ts2_i);
tmp.fifo_ts3_i := f_x_to_zero(left.fifo_ts3_i) or f_x_to_zero(right.fifo_ts3_i);
tmp.lts0_i := f_x_to_zero(left.lts0_i) or f_x_to_zero(right.lts0_i);
tmp.lts1_i := f_x_to_zero(left.lts1_i) or f_x_to_zero(right.lts1_i);
tmp.lts2_i := f_x_to_zero(left.lts2_i) or f_x_to_zero(right.lts2_i);
tmp.lts3_i := f_x_to_zero(left.lts3_i) or f_x_to_zero(right.lts3_i);
tmp.ltsctl_valid_i := f_x_to_zero(left.ltsctl_valid_i) or f_x_to_zero(right.ltsctl_valid_i);
tmp.csr_last_valid_i := f_x_to_zero(left.csr_last_valid_i) or f_x_to_zero(right.csr_last_valid_i);
return tmp;
end function;
end package body;
hdl/rtl/wbgen/tdc_eic.wb
View file @ c2a10e64
......@@ -5,25 +5,41 @@ peripheral {
prefix = "tdc_eic";
irq {
name = "FMC TDC timestamps interrupt (FIFO1)";
description = "FMC TDC FIFO1 not empty.";
prefix = "tdc_fifo1";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt (FIFO2)";
description = "FMC TDC FIFO1 not empty.";
prefix = "tdc_fifo2";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt";
description = "FMC TDC timestamp interrupt (rising edge sensitive).";
prefix = "tdc_tstamps";
trigger = EDGE_RISING;
name = "FMC TDC timestamps interrupt (FIFO3)";
description = "FMC TDC FIFO3 not empty.";
prefix = "tdc_fifo3";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC time interrupt";
description = "FMC TDC time interrupt (rising edge sensitive).";
prefix = "tdc_time";
trigger = EDGE_RISING;
name = "FMC TDC timestamps interrupt (FIFO4)";
description = "FMC TDC FIFO4 not empty.";
prefix = "tdc_fifo4";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC acam error interrupt";
description = "FMC slot 1 acam error interrupt (rising edge sensitive).";
prefix = "tdc_acam_err";
trigger = EDGE_RISING;
name = "FMC TDC timestamps interrupt (FIFO5)";
description = "FMC TDC FIFO5 not empty.";
prefix = "tdc_fifo5";
trigger = LEVEL_1;
};
};
hdl/rtl/timestamp_fifo_wb.wb → hdl/rtl/wbgen/timestamp_fifo_wb.wb
View file @ c2a10e64
......@@ -15,14 +15,35 @@ peripheral {
name = "Timestamp FIFO";
clock = "clk_tdc_i";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT, FIFO_CLEAR};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
field {
name = "The timestamp";
prefix = "value";
name = "The timestamp (word 0)";
prefix = "ts0";
type = SLV;
size = 128;
size = 32;
};
field {
name = "The timestamp (word 1)";
prefix = "ts1";
type = SLV;
size = 32;
};
field {
name = "The timestamp (word 2)";
prefix = "ts2";
type = SLV;
size = 32;
};
field {
name = "The timestamp (word 4)";
prefix = "ts3";
type = SLV;
size = 32;
};
};
......@@ -84,19 +105,31 @@ peripheral {
};
};
reg {
name = "Last Timestamp Control/Status";
prefix = "LTSCTL";
name = "Control/Status";
prefix = "CSR";
field {
name = "Last Timestamp Valid";
clock = "clk_tdc_i";
prefix = "VALID";
prefix = "LAST_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Reset Sequence Counter";
clock = "clk_tdc_i";
prefix = "RST_SEQ";
type = MONOSTABLE;
};
};
};
hdl/syn/svec/wr_svec_tdc.xise
View file @ c2a10e64
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/svec/main.sv
View file @ c2a10e64
......@@ -51,12 +51,12 @@ module fake_acam(
if (addr == 8) begin
acam_fifo_entry ent;
ent=fifo1.pop_front();
data <= ent.ts | (ent.channel << 26);
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else if (addr == 9) begin
acam_fifo_entry ent;
ent=fifo2.pop_front();
data <= ent.ts | (ent.channel << 26);
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else
data <= 28'bz;
......@@ -218,7 +218,7 @@ module main;
acc.write('hc13004, 'hf); // enable EIC irq
acc.write('hc12084, 'h1f); // enable all ACAM inputs
acc.write('hc12084, 'h1f0000); // enable all ACAM inputs
acc.write('hc120fc, (1<<0)); // start acquisition
acc.write('hc120fc, (1<<0)); // start acquisition
......@@ -230,11 +230,11 @@ module main;
#300us;
fork
forever begin
acc.read('hc15000 + `ADDR_TSF_LTSCTL, d);
acc.read('hc15000 + `ADDR_TSF_CSR, d);
if(d&1) begin
uint64_t t0,t1,t2,t3;
acc.write('hc15000 + `ADDR_TSF_LTSCTL, 0);
acc.write('hc15000 + `ADDR_TSF_CSR, 0);
acc.read('hc15000 + `ADDR_TSF_LTS0, t0);
acc.read('hc15000 + `ADDR_TSF_LTS1, t1);
acc.read('hc15000 + `ADDR_TSF_LTS2, t2);
......@@ -244,8 +244,23 @@ module main;
end
acc.read('hc15000 + `ADDR_TSF_FIFO_CSR, d);
// $display("FIFO CSR %x", d);
/* -----\/----- EXCLUDED -----\/-----
if(!(d&`TSF_FIFO_CSR_EMPTY)) begin
uint64_t t0,t1,t2,t3;
acc.read('hc15000 + `ADDR_TSF_FIFO_R0, t0);
acc.read('hc15000 + `ADDR_TSF_FIFO_R1, t1);
acc.read('hc15000 + `ADDR_TSF_FIFO_R2, t2);
acc.read('hc15000 + `ADDR_TSF_FIFO_R3, t3);
$display("Fifo: %08x %08x %08x %08x",t0,t1,t2,t3);
end
-----/\----- EXCLUDED -----/\----- */
end
......
hdl/testbench/svec/wave.do
View file @ c2a10e64
......@@ -103,140 +103,143 @@ add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/i
add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/irq_timeout
add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tick_1ms
add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/counter_1ms
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/address_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef1_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef2_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_adr
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_stb
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_we
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_ack
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_start01
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reset_acam
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_utc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/window_delay
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_period
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/starting_utc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_start01
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/state_active_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc_p
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_channel
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_sys
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/address_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef1_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef2_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_adr
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_stb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_we
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_ack
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_start01
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reset_acam
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/window_delay
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_period
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/starting_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_start01
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/state_active_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc_p
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_sys
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/ts_match
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/seq_counter
add wave -noupdate -expand -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_with_seq
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {936185162 ps} 0}
WaveRestoreCursors {{Cursor 1} {971916383 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -251,4 +254,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {890208852 ps} {1005778482 ps}
WaveRestoreZoom {969414062 ps} {973025614 ps}
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