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FMC TDC 1ns 5cha - Gateware
Commit c863a036 authored by egousiou's avatar egousiou
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small change on svec top_tdc: irq synchronisation 

git-svn-id: http://svn.ohwr.org/fmc-tdc@137 85dfdc96-de2c-444c-878d-45b388be74a9
parent 0b9d3454
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hdl/syn/svec/svec-tdc-fmc.gise
View file @ c863a036
......@@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1383763118" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1383762954">
<transform xil_pn:end_ts="1383822997" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1383822823">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -125,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1383763130" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1383763118">
<transform xil_pn:end_ts="1383823013" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1383822997">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -135,7 +135,7 @@
<outfile xil_pn:name="top_tdc.ngd"/>
<outfile xil_pn:name="top_tdc_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1383763330" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1383763130">
<transform xil_pn:end_ts="1383823223" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1383823013">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -148,7 +148,7 @@
<outfile xil_pn:name="top_tdc_summary.xml"/>
<outfile xil_pn:name="top_tdc_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1383763581" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1383763330">
<transform xil_pn:end_ts="1383823767" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1383823223">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -163,7 +163,7 @@
<outfile xil_pn:name="top_tdc_pad.txt"/>
<outfile xil_pn:name="top_tdc_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1383763691" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1383763630">
<transform xil_pn:end_ts="1383823828" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1383823767">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -175,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1383763581" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1383763560">
<transform xil_pn:end_ts="1383823767" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1383823744">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/syn/svec/svec-tdc-fmc.xise
View file @ c863a036
......@@ -418,7 +418,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../top/svec/top_tdc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
......@@ -446,7 +446,7 @@
</file>
<file xil_pn:name="../../ip_cores/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
......@@ -462,7 +462,7 @@
</file>
<file xil_pn:name="../../ip_cores/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
......
hdl/syn/svec/top_tdc.bin
View file @ c863a036
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hdl/syn/svec/top_tdc.twr
View file @ c863a036
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hdl/syn/svec/top_tdc_summary.html
View file @ c863a036
......@@ -2,11 +2,12 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status (11/06/2013 - 19:48:11)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status (11/07/2013 - 12:30:28)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>svec-tdc-fmc.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
......@@ -24,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/*.xmsgs?&DataKey=Warning'>3328 Warnings (3326 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/*.xmsgs?&DataKey=Warning'>3329 Warnings (3316 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
......@@ -48,7 +49,7 @@ No Errors</TD>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>1323 &nbsp;<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
<TD>640 &nbsp;<A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
......@@ -60,13 +61,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>6,526</TD>
<TD ALIGN=RIGHT>6,508</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>6,480</TD>
<TD ALIGN=RIGHT>6,462</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -90,19 +91,19 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>9,209</TD>
<TD ALIGN=RIGHT>9,119</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>8,925</TD>
<TD ALIGN=RIGHT>8,921</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>5,942</TD>
<TD ALIGN=RIGHT>5,940</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -114,7 +115,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>2,596</TD>
<TD ALIGN=RIGHT>2,594</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -168,13 +169,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>247</TD>
<TD ALIGN=RIGHT>161</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>173</TD>
<TD ALIGN=RIGHT>87</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -192,9 +193,9 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>3,605</TD>
<TD ALIGN=RIGHT>3,760</TD>
<TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD ALIGN=RIGHT>16%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Nummber of MUXCYs used</TD>
......@@ -204,37 +205,37 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>10,450</TD>
<TD ALIGN=RIGHT>10,554</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>4,699</TD>
<TD ALIGN=RIGHT>10,450</TD>
<TD ALIGN=RIGHT>4,732</TD>
<TD ALIGN=RIGHT>10,554</TD>
<TD ALIGN=RIGHT>44%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>1,241</TD>
<TD ALIGN=RIGHT>10,450</TD>
<TD ALIGN=RIGHT>11%</TD>
<TD ALIGN=RIGHT>1,435</TD>
<TD ALIGN=RIGHT>10,554</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>4,510</TD>
<TD ALIGN=RIGHT>10,450</TD>
<TD ALIGN=RIGHT>43%</TD>
<TD ALIGN=RIGHT>4,387</TD>
<TD ALIGN=RIGHT>10,554</TD>
<TD ALIGN=RIGHT>41%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>207</TD>
<TD ALIGN=RIGHT>206</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>361</TD>
<TD ALIGN=RIGHT>355</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -445,7 +446,7 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>1323 (Setup: 1323, Hold: 0, Component Switching Limit: 0)</TD>
<TD>640 (Setup: 640, Hold: 0, Component Switching Limit: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
......@@ -470,21 +471,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Nov 6 19:38:37 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Warning'>3316 Warnings (3316 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Info'>137 Infos (137 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Nov 6 19:38:50 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Nov 6 19:42:10 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Info'>279 Infos (279 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Nov 6 19:45:59 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Warning'>7 Warnings (7 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (2 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Nov 7 12:16:37 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Warning'>3317 Warnings (3306 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Info'>135 Infos (135 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Nov 7 12:16:53 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Nov 7 12:20:23 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Info'>279 Infos (279 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Nov 7 12:29:04 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Warning'>7 Warnings (7 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (2 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Nov 6 19:46:21 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Nov 6 19:48:02 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Nov 7 12:29:26 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Nov 7 12:30:19 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 6 19:48:03 2013</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 6 19:48:11 2013</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Nov 7 12:30:19 2013</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Nov 7 12:30:28 2013</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 11/06/2013 - 19:48:12</center>
<br><center><b>Date Generated:</b> 11/07/2013 - 12:30:28</center>
</BODY></HTML>
\ No newline at end of file
hdl/top/svec/top_tdc.vhd
View file @ c863a036
......@@ -385,8 +385,8 @@ architecture rtl of top_tdc is
---------------------------------------------------------------------------------------------------
-- Interrupts
signal irq_to_vmecore : std_logic;
signal tdc1_irq, tdc1_irq_synch : std_logic;
signal tdc2_irq, tdc2_irq_synch : std_logic;
signal tdc1_irq, tdc2_irq : std_logic;
signal tdc1_irq_synch, tdc2_irq_synch : std_logic_vector (1 downto 0);
---------------------------------------------------------------------------------------------------
-- Carrier other signals
......@@ -802,30 +802,26 @@ begin
rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => tdc1_irq_synch,
irqs_i(1) => tdc2_irq_synch,
irqs_i(0) => tdc1_irq_synch(1),
irqs_i(1) => tdc2_irq_synch(1),
irq_master_o => irq_to_vmecore);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- since the TDC cores work in their PLL clock domains (tdc1_clk_125m and tdc2_clk_125m)
-- and the rest works with the system clock (clk_62m5_sys) we need to synchronize
-- interrupt pulses.
cmp_sync_irq0 : gc_pulse_synchronizer
port map
(clk_in_i => tdc1_clk_125m,
clk_out_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
d_p_i => tdc1_irq,
q_p_o => tdc1_irq_synch);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sync_irq1 : gc_pulse_synchronizer
port map
(clk_in_i => tdc1_clk_125m,
clk_out_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
d_p_i => tdc2_irq,
q_p_o => tdc2_irq_synch);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- and the rest works with the system clock (clk_62m5_sys) interrupt pulses need to be
-- synchronized
irq_pulse_synchronizer: process (clk_62m5_sys)
begin
if rising_edge (clk_62m5_sys) then
if rst_n_sys = '0' then
tdc1_irq_synch <= (others => '0');
tdc2_irq_synch <= (others => '0');
else
tdc1_irq_synch <= tdc1_irq_synch(0) & tdc1_irq;
tdc2_irq_synch <= tdc2_irq_synch(0) & tdc2_irq;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
......
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