Commit c86fe33b authored by penacoba's avatar penacoba

First operating .bit for the test of the mezzaning pll inside syn/test_tdc_pll


git-svn-id: http://svn.ohwr.org/fmc-tdc@33 85dfdc96-de2c-444c-878d-45b388be74a9
parent b4d12c32
Thu 07 Jul 2011 06:32:13 PM CEST
Wed 13 Jul 2011 11:30:31 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
Wed 13 Jul 2011 11:30:32 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
Wed 13 Jul 2011 11:30:32 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
Wed 13 Jul 2011 11:30:35 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
Wed 13 Jul 2011 11:30:35 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
Wed 13 Jul 2011 11:31:02 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
Wed 13 Jul 2011 11:31:13 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
Wed 13 Jul 2011 11:31:13 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
Wed 13 Jul 2011 11:31:15 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:55 PM CEST
Thu 14 Jul 2011 03:30:18 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:55 PM CEST
Thu 14 Jul 2011 03:32:29 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:55 PM CEST
Thu 14 Jul 2011 03:32:30 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:55 PM CEST
Thu 14 Jul 2011 03:32:37 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:56 PM CEST
Thu 14 Jul 2011 03:32:37 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:56 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:57 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:57 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 07:32:59 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 07:32:59 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Fri 08 Jul 2011 03:05:19 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:04:27 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:05:27 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:05:30 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:31 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:31 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:32 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:32 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:32 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:40:01 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:40:01 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:40:42 AM CEST
Thu 14 Jul 2011 04:16:41 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
......@@ -22,7 +22,7 @@ bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
wait %d90000
-- Drive reset to the FPGA
reset %d320
......
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/gn4124_core_pkg_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/ip_cores/fifo_32x512.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/ip_cores/fifo_64x512.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/serdes_n_to_1_s2_diff.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/serdes_n_to_1_s2_se.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/l2p_ser_s6.vhd
ncvhdl -controlrelax NLSTEX -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/serdes_1_to_n_data_s2_se.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/p2l_des_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/p2l_decode32.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/wbmaster32.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/dma_controller_wb_slave.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/dma_controller.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/l2p_dma_master.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/p2l_dma_master.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/l2p_arbiter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/gn4124_core_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/l2p_ser_s6.vhd
ncvhdl -controlrelax NLSTEX -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/p2l_des_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/p2l_decode32.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/wbmaster32.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/dma_controller.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/l2p_dma_master.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/p2l_dma_master.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/l2p_arbiter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/gn4124_core_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/tdc_core_pkg.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/free_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/incr_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/countdown_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/clk_rst_managr.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/one_hz_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/start_nb_offset_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/data_formatting.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/acam_timecontrol_interface.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/acam_databus_interface.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/tdc_core_pkg.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/free_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/incr_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/countdown_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/clk_rst_managr.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/one_hz_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/start_nb_offset_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/data_formatting.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/acam_timecontrol_interface.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/acam_databus_interface.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/top_tdc.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/test_tdc_acam/top_test_acam.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/test_tdc_pll/top_test_pll.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/top_tdc.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/test_tdc_acam/top_test_acam.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/test_tdc_pll/top_test_pll.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/util.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/textutil.vhd
......
......@@ -6,18 +6,20 @@ probe -create -shm -waveform :dut:acam_refclk
probe -create -shm -waveform :dut:gnum_reset
probe -create -shm -waveform :dut:general_reset
#probe -create -shm -waveform :dut:clocks_and_resets_management_block:half_clk
probe -create -shm -waveform :dut:clocks_and_resets_management_block:cs
#probe -create -shm -waveform :dut:clocks_and_resets_management_block:bit_index
probe -create -shm -waveform :dut:clocks_and_resets_management_block:byte_index
probe -create -shm -waveform :dut:clocks_and_resets_management_block:bit_being_sent
probe -create -shm -waveform :dut:clocks_and_resets_management_block:byte_being_sent
probe -create -shm -waveform :dut:clocks_and_resets_management_block:pll_init_st
probe -create -shm -waveform :dut:clocks_and_resets_management_block:gral_incr
probe -create -shm -waveform :dut:clocks_and_resets_management_block:inv_reset
probe -create -shm -waveform :dut:clocks_and_resets_management_block:general_power_on_reset:current_value
#probe -create -shm -waveform :dut:clocks_and_resets_management_block:nxt_pll_init_st
probe -create -shm -waveform :dut:clks_rsts_mgment:pll_sclk
probe -create -shm -waveform :dut:clks_rsts_mgment:pll_sdi_o
probe -create -shm -waveform :dut:clks_rsts_mgment:cs
probe -create -shm -waveform :dut:clks_rsts_mgment:bit_index
probe -create -shm -waveform :dut:clks_rsts_mgment:byte_index
probe -create -shm -waveform :dut:clks_rsts_mgment:bit_being_sent
probe -create -shm -waveform :dut:clks_rsts_mgment:byte_being_sent
probe -create -shm -waveform :dut:clks_rsts_mgment:word_being_sent
probe -create -shm -waveform :dut:clks_rsts_mgment:pll_init_st
probe -create -shm -waveform :dut:clks_rsts_mgment:gral_incr
probe -create -shm -waveform :dut:clks_rsts_mgment:inv_reset
probe -create -shm -waveform :dut:clks_rsts_mgment:general_power_on_reset:current_value
probe -create -shm -waveform :dut:clks_rsts_mgment:nxt_pll_init_st
probe -create -shm -waveform :spec_led_green
probe -create -shm -waveform :spec_led_red
......@@ -170,4 +172,4 @@ probe -create -shm -waveform :acam:timing_block:start_retrig_nb
set intovf_severity_level warning
run 1 ms
run 2 ms
This diff is collapsed.
# Date: Thu Feb 3 16:41:04 2011
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: f66dfaab
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_32x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_32x512.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_32x512.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_32x512.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_32x512.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
This diff is collapsed.
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_32x512.vhd when simulating
-- the core, fifo_32x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_32x512 IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
END fifo_32x512;
ARCHITECTURE fifo_32x512_a OF fifo_32x512 IS
-- synthesis translate_off
component wrapped_fifo_32x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 508,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 509,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_32x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_32x512_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component fifo_32x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : fifo_32x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file fifo_32x512.vhd when simulating
-- the core, fifo_32x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Feb 3 16:40:52 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=fifo_32x512
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=509
CSET full_threshold_negate_value=508
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
CSET input_depth=512
CSET output_data_width=32
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: adce0ad2
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_64x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_64x512.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_64x512.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_64x512.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_64x512.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
This source diff could not be displayed because it is too large. You can view the blob instead.
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_64x512.vhd when simulating
-- the core, fifo_64x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_64x512 IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
END fifo_64x512;
ARCHITECTURE fifo_64x512_a OF fifo_64x512 IS
-- synthesis translate_off
component wrapped_fifo_64x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_64x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 64,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 64,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 508,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 509,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x72",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_64x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_64x512_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component fifo_64x512
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic;
prog_full: OUT std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_64x512: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : fifo_64x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file fifo_64x512.vhd when simulating
-- the core, fifo_64x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Feb 3 16:45:57 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=fifo_64x512
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=509
CSET full_threshold_negate_value=508
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=64
CSET input_depth=512
CSET output_data_width=64
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: d8162d61
This diff is collapsed.
This diff is collapsed.
......@@ -57,6 +57,7 @@ entity top_tdc is
p_rd_d_rdy_i: in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
spare_o : out std_logic;
-- interface signals with PLL circuit on TDC mezzanine
acam_refclk_i : in std_logic;
......@@ -348,24 +349,21 @@ signal clock_period : std_logic_vector(g_width-1 downto 0);
signal gnum_reset : std_logic;
signal pll_cs : std_logic;
signal spec_clk : std_logic;
signal tdc_led_status : std_logic:='0';
signal spec_led_green : std_logic;
signal spec_led_red : std_logic;
signal tdc_led_status : std_logic;
signal tdc_led_trig1 : std_logic:='0';
signal tdc_led_trig2 : std_logic:='0';
signal tdc_led_trig3 : std_logic:='0';
signal tdc_led_trig4 : std_logic:='0';
signal tdc_led_trig5 : std_logic:='0';
signal spec_led_green : std_logic:='0';
signal spec_led_red : std_logic:='0';
signal acam_errflag_p : std_logic;
signal acam_intflag_p : std_logic;
signal acam_refclk : std_logic;
signal acam_start01 : std_logic_vector(16 downto 0);
signal acam_timestamp : std_logic_vector(28 downto 0);
signal acam_timestamp_valid : std_logic;
signal clk : std_logic;
signal full_timestamp : std_logic_vector(3*g_width-1 downto 0);
signal full_timestamp_valid : std_logic;
signal general_reset : std_logic;
......@@ -404,6 +402,10 @@ signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_ack : std_logic;
signal dma_stall : std_logic;
signal acam_refclk : std_logic;
signal clk : std_logic;
signal spec_clk : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
......@@ -565,7 +567,7 @@ begin
dma_stall_i => dma_stall
);
clocks_and_resets_management_block: clk_rst_managr
clks_rsts_mgment: clk_rst_managr
port map(
acam_refclk_i => acam_refclk_i,
pll_ld_i => pll_ld_i,
......@@ -603,7 +605,9 @@ begin
spec_led: process
begin
if spec_led_count_done ='1' then
if gnum_reset ='1' then
spec_led_red <= '0';
elsif spec_led_count_done ='1' then
spec_led_red <= not(spec_led_red);
end if;
wait until spec_clk ='1';
......@@ -640,12 +644,18 @@ begin
-- outputs
pll_cs_o <= pll_cs;
mute_inputs_o <= '0';
tdc_led_status_o <= tdc_led_status;
tdc_led_trig1_o <= tdc_led_trig1;
tdc_led_trig2_o <= tdc_led_trig2;
tdc_led_trig3_o <= tdc_led_trig3;
tdc_led_trig4_o <= tdc_led_trig4;
tdc_led_trig5_o <= tdc_led_trig5;
term_en_1_o <= '1';
term_en_2_o <= '1';
term_en_3_o <= '1';
term_en_4_o <= '1';
term_en_5_o <= '1';
spec_led_green_o <= spec_led_green;
spec_led_red_o <= spec_led_red;
......@@ -657,6 +667,7 @@ begin
start_dis_o <= '0';
stop_dis_o <= '0';
-- when button 1 is pressed --> start every second. Otherwise start with button 0
start_from_fpga_o <= one_hz_p when spec_aux1_i ='0' else not(spec_aux0_i);
spec_aux2_o <= spec_aux0_i;
spec_aux3_o <= spec_aux1_i;
......
......@@ -57,6 +57,7 @@ entity top_tdc is
p_rd_d_rdy_i: in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
spare_o : out std_logic;
-- interface signals with PLL circuit on TDC mezzanine
acam_refclk_i : in std_logic;
......@@ -180,15 +181,17 @@ signal clock_period : std_logic_vector(g_width-1 downto 0):=x"000030
signal gnum_reset : std_logic;
signal pll_cs : std_logic;
signal pll_sclk : std_logic;
signal pll_sdi : std_logic;
signal tdc_led_status : std_logic:='0';
signal spec_led_green : std_logic;
signal spec_led_red : std_logic;
signal tdc_led_status : std_logic;
signal tdc_led_trig1 : std_logic:='0';
signal tdc_led_trig2 : std_logic:='0';
signal tdc_led_trig3 : std_logic:='0';
signal tdc_led_trig4 : std_logic:='0';
signal tdc_led_trig5 : std_logic:='0';
signal spec_led_green : std_logic:='0';
signal spec_led_red : std_logic:='0';
signal acam_errflag_p : std_logic;
signal acam_intflag_p : std_logic;
......@@ -244,7 +247,7 @@ signal spec_clk : std_logic;
----------------------------------------------------------------------------------------------------
begin
clocks_and_resets_management_block: clk_rst_managr
clks_rsts_mgment: clk_rst_managr
port map(
acam_refclk_i => acam_refclk_i,
pll_ld_i => pll_ld_i,
......@@ -260,8 +263,8 @@ begin
general_reset_o => general_reset,
pll_cs_o => pll_cs,
pll_dac_sync_o => pll_dac_sync_o,
pll_sdi_o => pll_sdi_o,
pll_sclk_o => pll_sclk_o,
pll_sdi_o => pll_sdi,
pll_sclk_o => pll_sclk,
spec_clk_o => spec_clk,
tdc_clk_o => clk
);
......@@ -296,7 +299,9 @@ begin
tdc_led: process
begin
if tdc_led_count_done ='1' then
if general_reset ='1' then
tdc_led_status <= '0';
elsif tdc_led_count_done ='1' then
tdc_led_status <= not(tdc_led_status);
end if;
wait until clk='1';
......@@ -304,7 +309,9 @@ begin
spec_led: process
begin
if spec_led_count_done ='1' then
if gnum_reset ='1' then
spec_led_red <= '0';
elsif spec_led_count_done ='1' then
spec_led_red <= not(spec_led_red);
end if;
wait until spec_clk ='1';
......@@ -313,15 +320,47 @@ begin
spec_led_green <= pll_ld_i;
-- inputs
gnum_reset <= not(rst_n_a_i);
gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i);
-- outputs
pll_cs_o <= pll_cs;
pll_sclk_o <= pll_sclk;
pll_sdi_o <= pll_sdi;
mute_inputs_o <= '0';
term_en_1_o <= '1';
term_en_2_o <= '1';
term_en_3_o <= '1';
term_en_4_o <= '1';
term_en_5_o <= '1';
tdc_led_status_o <= tdc_led_status;
spec_led_green_o <= spec_led_green;
spec_led_red_o <= spec_led_red;
-- tdc_led_trig1_o <= not(spec_aux0_i);
-- tdc_led_trig2_o <= not(spec_aux0_i);
tdc_led_trig3_o <= not(spec_aux0_i);
tdc_led_trig4_o <= not(spec_aux0_i);
tdc_led_trig5_o <= not(spec_aux0_i);
button_with_spec_clk: process
begin
tdc_led_trig1_o <= spec_aux0_i;
wait until spec_clk ='1';
end process;
button_with_tdc_clk: process
begin
tdc_led_trig2_o <= spec_aux0_i;
wait until clk ='1';
end process;
spec_aux2_o <= pll_sclk;
spec_aux3_o <= pll_sdi;
spec_aux4_o <= pll_cs;
spec_aux5_o <= gnum_reset;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
......
......@@ -57,6 +57,7 @@ architecture behavioral of tb_tdc is
p_rd_d_rdy_i: in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
spare_o : out std_logic;
-- interface signals with PLL circuit
acam_refclk_i : in std_logic;
......@@ -336,6 +337,7 @@ signal spec_led_red : std_logic;
-- GN4124 interface
signal rst_n : std_logic;
signal irq_p : std_logic;
signal spare : std_logic;
signal RSTINn : std_logic;
signal RSTOUT18n : std_logic;
......@@ -405,6 +407,7 @@ begin
p_rd_d_rdy_i => p_rd_d_rdy,
tx_error_i => tx_error,
irq_p_o => irq_p,
spare_o => spare,
-- interface with PLL circuit
acam_refclk_i => acam_refclk_i,
......@@ -631,8 +634,9 @@ begin
rst_n <= RSTOUT18n;
GPIO(0) <= irq_p;
GPIO(1) <= spare;
spec_aux0_i <= '1';
spec_aux1_i <= '0';
spec_aux1_i <= '1';
end behavioral;
rm -r backup
rm -r coreip
rm identify.log
rm rpt_tdc_top.areasrr rpt_tdc_top_areasrr.htm
rm rpt_top_tdc.areasrr rpt_top_tdc_areasrr.htm
rm run_ise.tcl
rm run_options.txt scratchproject.prs
rm synplicity.ucf
rm fifo_32x512.ngc
rm fifo_64x512.ngc
rm syn_tdc.edf
rm syn_tdc.fse
rm syn_tdc.htm
......@@ -32,8 +34,8 @@ rm syn_tdc.ngo
rm syn_tdc.pcf
rm syn_tdc_summary.xml
rm syn_tdc_usage.xml
rm tdc_top_map.xrpt
rm tdc_top_par.xrpt
rm top_tdc_map.xrpt
rm top_tdc_par.xrpt
rm -r xlnx_auto_0_xdb
rm -r _xmsgs
......
......@@ -5,27 +5,28 @@
# Clocks
#
define_clock {n:spec_clk} -name {spec_clk20} -freq 20 -clockgroup default_clkgroup_0
define_clock {n:clocks_management_block.half_clk} -name {half_clk} -freq 10 -clockgroup default_clkgroup_0
define_clock {n:acam_refclk} -name {acam_refclk} -freq 1.25 -clockgroup default_clkgroup_1
define_clock {n:clk} -name {tdc_clk125} -freq 125 -clockgroup default_clkgroup_1
#define_clock {spec_clk_i} -name {spec_clki} -freq 20 -clockgroup default_clkgroup_0
#define_clock {clocks_management_block.half_clk} -name {half_clk} -freq 10 -clockgroup default_clkgroup_0
#define_clock {clocks_management_block.tdc_clk125_ibuf} -name {tdc_clk125} -freq 125 -clockgroup default_clkgroup_1
define_clock {n:clk} -name {tdc_clk125} -freq 125
define_clock {n:spec_clk} -name {spec_clk20} -freq 20
define_attribute {n:spec_clk} syn_keep {true}
#define_attribute {n:spec_clk_i} -syn_noclock_buf {1}
# -clockgroup default_clkgroup_0
# Inputs/Outputs
#
define_input_delay -default 2.00 -ref tdc_clk125:r
define_output_delay -default 2.00 -ref tdc_clk125:r
define_output_delay {p:pll_sdi_o} 2.00 -ref half_clk:r
define_output_delay {p:pll_cs_o} 2.00 -ref half_clk:r
define_output_delay {p:pll_sclk_o} 2.00 -ref half_clk:r
define_input_delay {p:pll_ld_i} 2.00 -ref half_clk:r
define_input_delay {p:pll_refmon_i} 2.00 -ref half_clk:r
define_input_delay {p:pll_sdo_i} 2.00 -ref half_clk:r
define_input_delay {p:pll_status_i} 2.00 -ref half_clk:r
define_output_delay {p:spec_led_green_o} 2.00 -ref spec_clk20:r
define_output_delay {p:spec_led_red_o} 2.00 -ref spec_clk20:r
define_output_delay {p:pll_sdi_o} 2.00 -ref spec_clk20:r
define_output_delay {p:pll_cs_o} 2.00 -ref spec_clk20:r
define_output_delay {p:pll_sclk_o} 2.00 -ref spec_clk20:r
define_input_delay {p:pll_ld_i} 2.00 -ref spec_clk20:r
define_input_delay {p:pll_refmon_i} 2.00 -ref spec_clk20:r
define_input_delay {p:pll_sdo_i} 2.00 -ref spec_clk20:r
define_input_delay {p:pll_status_i} 2.00 -ref spec_clk20:r
# Attributes
# Global attribute definitions for improving implementation targetting Xilinx
......@@ -91,7 +92,7 @@ define_attribute {p:p_rd_d_rdy_i[1]} {syn_loc} {P19}
define_attribute {p:p_rd_d_rdy_i[0]} {syn_loc} {N16}
define_attribute {p:tx_error_i} {syn_loc} {M17}
define_attribute {p:irq_p_o} {syn_loc} {U16}
#define_attribute {p:spare_o} {syn_loc} {AB19}
define_attribute {p:spare_o} {syn_loc} {AB19}
define_attribute {p:acam_refclk_i} {syn_loc} {E16}
define_attribute {p:pll_ld_i} {syn_loc} {C18}
......@@ -100,10 +101,10 @@ define_attribute {p:pll_sdo_i} {syn_loc} {AB18}
define_attribute {p:pll_status_i} {syn_loc} {Y18}
define_attribute {p:tdc_clk_p_i} {syn_loc} {L20}
define_attribute {p:tdc_clk_n_i} {syn_loc} {L22}
define_attribute {p:pll_cs_o} {syn_loc} {AB17}
define_attribute {p:pll_cs_o} {syn_loc} {Y17}
define_attribute {p:pll_dac_sync_o} {syn_loc} {AB16}
define_attribute {p:pll_sdi_o} {syn_loc} {AA18}
define_attribute {p:pll_sclk_o} {syn_loc} {Y17}
define_attribute {p:pll_sclk_o} {syn_loc} {AB17}
define_attribute {p:err_flag_i} {syn_loc} {V11}
define_attribute {p:int_flag_i} {syn_loc} {W11}
define_attribute {p:start_dis_o} {syn_loc} {T15}
......@@ -160,6 +161,14 @@ define_attribute {p:term_en_2_o} {syn_loc} {B20}
define_attribute {p:term_en_3_o} {syn_loc} {A20}
define_attribute {p:term_en_4_o} {syn_loc} {H10}
define_attribute {p:term_en_5_o} {syn_loc} {E6}
define_attribute {p:spec_aux0_i} {syn_loc} {C22}
define_attribute {p:spec_aux1_i} {syn_loc} {D21}
define_attribute {p:spec_aux2_o} {syn_loc} {G19}
define_attribute {p:spec_aux3_o} {syn_loc} {F20}
define_attribute {p:spec_aux4_o} {syn_loc} {F18}
define_attribute {p:spec_aux5_o} {syn_loc} {C20}
define_attribute {p:spec_led_green_o} {syn_loc} {E5}
define_attribute {p:spec_led_red_o} {syn_loc} {D5}
define_attribute {p:spec_clk_i} {syn_loc} {H12}
......@@ -177,10 +186,10 @@ define_io_standard {p_wr_req_i[1:0]} syn_pad_type {SSTL_18_Class_I}
define_io_standard {p_wr_rdy_o[1:0]} syn_pad_type {SSTL_18_Class_I}
define_io_standard {rx_error_o} syn_pad_type {SSTL_18_Class_I}
define_io_standard {vc_rdy_i[1:0]} syn_pad_type {SSTL_18_Class_I}
define_io_standard {l2p_clk_p_o} syn_pad_type {SSTL_18_Class_II}
define_io_standard {l2p_clk_n_o} syn_pad_type {SSTL_18_Class_II}
#define_io_standard {l2p_clk_p_o} syn_pad_type {DIFF_SSTL_18_Class_II}
#define_io_standard {l2p_clk_n_o} syn_pad_type {DIFF_SSTL_18_Class_II}
define_io_standard {l2p_clk_p_o} syn_pad_type {SSTL_18_Class_I}
define_io_standard {l2p_clk_n_o} syn_pad_type {SSTL_18_Class_I}
define_io_standard {l2p_data_o[15:0]} syn_pad_type {SSTL_18_Class_I}
define_io_standard {l2p_dframe_o} syn_pad_type {SSTL_18_Class_I}
define_io_standard {l2p_valid_o} syn_pad_type {SSTL_18_Class_I}
......@@ -190,14 +199,15 @@ define_io_standard {l_wr_rdy_i[1:0]} syn_pad_type {SSTL_18_Class_I}
define_io_standard {p_rd_d_rdy_i[1:0]} syn_pad_type {SSTL_18_Class_I}
define_io_standard {tx_error_i} syn_pad_type {SSTL_18_Class_I}
define_io_standard {irq_p_o} syn_pad_type {LVCMOS_25}
define_io_standard {spare_o} syn_pad_type {LVCMOS_25}
define_io_standard {acam_refclk_i} syn_pad_type {LVCMOS_25}
define_io_standard {pll_ld_i} syn_pad_type {LVCMOS_25}
define_io_standard {pll_refmon_i} syn_pad_type {LVCMOS_25}
define_io_standard {pll_sdo_i} syn_pad_type {LVCMOS_25}
define_io_standard {pll_status_i} syn_pad_type {LVCMOS_25}
define_io_standard {tdc_clk_p_i} syn_pad_type {LVDS_25}
define_io_standard {tdc_clk_n_i} syn_pad_type {LVDS_25}
define_io_standard {tdc_clk_p_i} syn_pad_type {DIFF_SSTL_18_Class_II}
define_io_standard {tdc_clk_n_i} syn_pad_type {DIFF_SSTL_18_Class_II}
define_io_standard {pll_cs_o} syn_pad_type {LVCMOS_25}
define_io_standard {pll_dac_sync_o} syn_pad_type {LVCMOS_25}
define_io_standard {pll_sdi_o} syn_pad_type {LVCMOS_25}
......@@ -206,6 +216,7 @@ define_io_standard {pll_sclk_o} syn_pad_type {LVCMOS_25}
define_io_standard {err_flag_i} syn_pad_type {LVCMOS_25}
define_io_standard {int_flag_i} syn_pad_type {LVCMOS_25}
define_io_standard {start_dis_o} syn_pad_type {LVCMOS_25}
define_io_standard {start_from_fpga_o} syn_pad_type {LVCMOS_25}
define_io_standard {stop_dis_o} syn_pad_type {LVCMOS_25}
define_io_standard {data_bus_io[27:0]} syn_pad_type {LVCMOS_25}
define_io_standard {ef1_i} syn_pad_type {LVCMOS_25}
......@@ -231,6 +242,13 @@ define_io_standard {term_en_3_o} syn_pad_type {LVCMOS_25}
define_io_standard {term_en_4_o} syn_pad_type {LVCMOS_25}
define_io_standard {term_en_5_o} syn_pad_type {LVCMOS_25}
define_io_standard {spec_aux0_i} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux1_i} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux2_o} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux3_o} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux4_o} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux5_o} syn_pad_type {LVCMOS18}
define_io_standard {spec_led_green_o} syn_pad_type {LVCMOS_25}
define_io_standard {spec_led_red_o} syn_pad_type {LVCMOS_25}
define_io_standard {spec_clk_i} syn_pad_type {LVCMOS_25}
......
......@@ -5,20 +5,41 @@
#project files
#add_file -vhdl -lib work "../src/gnum_core/gn4124_core_pkg_s6.vhd"
#add_file -vhdl -lib work "../src/design/incr_counter.vhd"
#add_file -vhdl -lib work "../src/design/countdown_counter.vhd"
#add_file -vhdl -lib work "../src/design/one_hz_gen.vhd"
#add_file -vhdl -lib work "../src/design/start_nb_offset_gen.vhd"
#add_file -vhdl -lib work "../src/design/data_formatting.vhd"
#add_file -vhdl -lib work "../src/design/acam_timecontrol_interface.vhd"
#add_file -vhdl -lib work "../src/design/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/design/free_counter.vhd"
add_file -vhdl -lib work "../src/design/clk_managr.vhd"
#add_file -vhdl -lib work "../src/design/tdc_top.vhd"
add_file -vhdl -lib work "../src/design/tdc_pll_test/pll_test_top.vhd"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
#add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -vhdl -lib work "../src/rtl/test_tdc_pll/top_test_pll.vhd"
#add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -constraint -lib work "./tdc_syn_constraints.sdc"
......@@ -48,14 +69,14 @@ set_option -no_sequential_opt 0
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "tdc_top"
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 20
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -num_critical_paths 3
set_option -num_critical_paths 5
# Xilinx options
set_option -run_prop_extract 1
......@@ -81,6 +102,7 @@ set_option -write_vif 0
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
project -result_file "./test_tdc_pll/syn_tdc.edf"
#project -result_file "./test_tdc_acam/syn_tdc.edf"
#project -run -fg synthesis
#project -run -fg timing
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
</messages>
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#Build: Synplify Pro D-2010.03, Build 093R, Feb 19 2010
#install: /afs/cern.ch/project/parc/elec/synplify/D-2010.03
#OS: Linux
#Hostname: lxparc47.cern.ch
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syn_tdc.edf 1310751057
OK
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PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>269</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>709</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>709</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>601</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>9.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>10.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>11.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>12.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>17.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>20.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>12.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>7.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>5.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0271</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
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