Maintenance scheduled 24th July -- expect downtime along that day

Commit d13db7b9 authored by penacoba's avatar penacoba

cleaned up version of the ACAM TDC synthesis results


git-svn-id: http://svn.ohwr.org/fmc-tdc@36 85dfdc96-de2c-444c-878d-45b388be74a9
parent cb30b5d1
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000E02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 02000064
rrcmd w 0:80014 080003E8
rrcmd w 0:80018 000000FF
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
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#Build: Synplify Pro D-2010.03, Build 093R, Feb 19 2010
#install: /afs/cern.ch/project/parc/elec/synplify/D-2010.03
#OS: Linux
#Hostname: lxparc41.cern.ch
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/syn_tdc.edf 1311271086
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_64x512.ngc 1311271059
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_32x512.ngc 1311271059
OK
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Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Thu Jul 21 20:02:16 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
err_flag_i_IBUF
int_flag_i_IBUF
p_wr_req_i(0)_IBUF
p_wr_req_i(1)_IBUF
pll_refmon_i_IBUF
pll_sdo_i_IBUF
pll_status_i_IBUF
tx_error_i_IBUF
vc_rdy_i(0)_IBUF
vc_rdy_i(1)_IBUF
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>4432</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>12280</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>12280</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>11196</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>30.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>36.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>54.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>65.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>87.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>90.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>117.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>117.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>118.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>122.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>9.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>9.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>2.0314</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
#### START OF AREA REPORT #####[
Part: XC6SLX45TFGG484-2 (Xilinx)
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 2683 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2683 (47.45 % Utilization)
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 1736 100 %
MUXCY 314 100 %
XORCY 317 100 %
MULT18x18/MULT18x18S 2 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 2369 (41.90 % Utilization)
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.02 % Utilization)
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 122 100 %
=================================================
Total IO PADS in the block top_tdc: 122 (2.16 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
<html><head><title></title></head><body><a name=TopSummary>
#### START OF AREA REPORT #####[<pre>
Part: XC6SLX45TFGG484-2 (Xilinx)
Click here to go to specific block report:
<a href="rpt_top_tdc_areasrr.htm#top_tdc"><h5 align="center">top_tdc</h5></a><br><a name=top_tdc>
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 2683 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2683 (47.45 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 1736 100 %
MUXCY 314 100 %
XORCY 317 100 %
MULT18x18/MULT18x18S 2 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 2369 (41.90 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.02 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 122 100 %
=================================================
Total IO PADS in the block top_tdc: 122 (2.16 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
</a></body></html>
#########################
### DEFINE VARIABLES ###
#########################
set DesignName "syn_tdc"
set FamilyName "SPARTAN6"
set DeviceName "XC6SLX45T"
set PackageName "FGG484"
set SpeedGrade "-2"
set TopModule "top_tdc"
set EdifFile "syn_tdc.edf"
if {![file exists $DesignName.ise]} {
project new $DesignName.ise
project set family $FamilyName
project set device $DeviceName
project set package $PackageName
project set speed $SpeedGrade
xfile add $EdifFile
if {[file exists synplicity.ucf]} {
xfile add synplicity.ucf
}
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project close
}
file delete -force $DesignName\_xdb
project open $DesignName.ise
process run "Implement Design" -force rerun_all
project close
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/run_options.txt
#-- Written on Thu Jul 21 19:57:38 2011
#project files
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -constraint "./tdc_syn_constraints.sdc"
#implementation: "test_tdc_acam"
impl -add test_tdc_acam -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./test_tdc_acam/syn_tdc.edf"
impl -active "test_tdc_acam"
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/scratchproject.prs
#-- Written on Thu Jul 21 19:57:38 2011
#project files
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -constraint "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc"
#implementation: "test_tdc_acam"
impl -add /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
set_option -include_path /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/syn_tdc.edf"
impl -active "test_tdc_acam"
Release 13.1 ngdbuild O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line:
/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
-uc synplicity.ucf syn_tdc.edf
Executing edif2ngd "syn_tdc.edf" "syn_tdc.ngo"
Release 13.1 - edif2ngd O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 13.1 edif2ngd O.40d (lin64)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Applying constraints in "syn_tdc.ncf" to module "top_tdc"...
Checking Constraint Associations...
Writing module to "syn_tdc.ngo"...
Reading NGO file
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/syn_tdc.
ngo" ...
Loading design module
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_64x
512.ngc"...
Loading design module
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_32x
512.ngc"...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "synplicity.ucf" ...
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
'gnum_interface_block.cmp_clk_in.rx_pll_adv_inst' of type PLL_ADV has been
changed from 'VIRTEX5' to 'SPARTAN6' to correct post-ngdbuild and timing
simulation for this primitive. In order for functional simulation to be
correct, the value of SIM_DEVICE should be changed in this same manner in the
source netlist or constraint file.
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:178 - TNM 'gnum_interface_block_cmp_clk_in_buf_P_clk',
used in period specification 'TS_gnum_interface_block_cmp_clk_in_buf_P_clk',
was traced into PLL_ADV instance
gnum_interface_block.cmp_clk_in.rx_pll_adv_inst. The following new TNM groups
and period specifications were generated at the PLL_ADV output(s):
CLKOUT0: <TIMESPEC TS_gnum_interface_block_un1_cmp_clk_in = PERIOD
"gnum_interface_block_un1_cmp_clk_in"
TS_gnum_interface_block_cmp_clk_in_buf_P_clk / 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'gnum_interface_block_cmp_clk_in_buf_P_clk',
used in period specification 'TS_gnum_interface_block_cmp_clk_in_buf_P_clk',
was traced into PLL_ADV instance
gnum_interface_block.cmp_clk_in.rx_pll_adv_inst. The following new TNM groups
and period specifications were generated at the PLL_ADV output(s):
CLKOUT2: <TIMESPEC TS_gnum_interface_block_cmp_clk_in_rx_pllout_x1_0 = PERIOD
"gnum_interface_block_cmp_clk_in_rx_pllout_x1_0"
TS_gnum_interface_block_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%>
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Total memory usage is 340864 kilobytes
Writing NGD file "syn_tdc.ngd" ...
Total REAL time to NGDBUILD completion: 20 sec
Total CPU time to NGDBUILD completion: 17 sec
Writing NGDBUILD log file "syn_tdc.bld"...
This diff is collapsed.
fsm_encoding {22687681} onehot
fsm_state_encoding {22687681} idle {0000000}
fsm_state_encoding {22687681} rd_start {0000011}
fsm_state_encoding {22687681} read {0000101}
fsm_state_encoding {22687681} rd_ack {0001001}
fsm_state_encoding {22687681} wr_start {0010001}
fsm_state_encoding {22687681} write {0100001}
fsm_state_encoding {22687681} wr_ack {1000001}
fsm_registers {22687681} {acam_data_st[0]} {acam_data_st[1]} {acam_data_st[2]} {acam_data_st[3]} {acam_data_st[4]} {acam_data_st[5]} {acam_data_st_i[6]}
fsm_encoding {1515541552} onehot
fsm_state_encoding {1515541552} 0000 {000000001}
fsm_state_encoding {1515541552} 0001 {000000010}
fsm_state_encoding {1515541552} 0010 {000000100}
fsm_state_encoding {1515541552} 0011 {000001000}
fsm_state_encoding {1515541552} 0100 {000010000}
fsm_state_encoding {1515541552} 0101 {000100000}
fsm_state_encoding {1515541552} 0110 {001000000}
fsm_state_encoding {1515541552} 0111 {010000000}
fsm_state_encoding {1515541552} 1001 {100000000}
fsm_registers {1515541552} {state[0]} {state[1]} {state[2]} {state[3]} {state[4]} {state[5]} {state[6]} {state[7]} {state[8]}
fsm_encoding {1414141413} sequential
fsm_state_encoding {1414141413} 0000 {0}
fsm_state_encoding {1414141413} 0001 {1}
fsm_registers {1414141413} {state[0]}
fsm_encoding {1414141414} sequential
fsm_state_encoding {1414141414} 0000 {0}
fsm_state_encoding {1414141414} 0001 {1}
fsm_registers {1414141414} {state[0]}
fsm_encoding {2634443445} sequential
fsm_state_encoding {2634443445} wb_idle {00}
fsm_state_encoding {2634443445} wb_read_fifo {01}
fsm_state_encoding {2634443445} wb_cycle {10}
fsm_state_encoding {2634443445} wb_wait_ack {11}
fsm_registers {2634443445} {wishbone_current_state[1]} {wishbone_current_state[0]}
fsm_encoding {2624842486} sequential
fsm_state_encoding {2624842486} l2p_idle {00}
fsm_state_encoding {2624842486} l2p_header {01}
fsm_state_encoding {2624842486} l2p_data {10}
fsm_registers {2624842486} {l2p_read_cpl_current_state[1]} {l2p_read_cpl_current_state[0]}
fsm_encoding {2732743277} onehot
fsm_state_encoding {2732743277} dma_idle {0000001}
fsm_state_encoding {2732743277} dma_start_transfer {0000010}
fsm_state_encoding {2732743277} dma_transfer {0000100}
fsm_state_encoding {2732743277} dma_start_chain {0001000}
fsm_state_encoding {2732743277} dma_chain {0010000}
fsm_state_encoding {2732743277} dma_error {0100000}