Commit d13db7b9 authored by penacoba's avatar penacoba

cleaned up version of the ACAM TDC synthesis results


git-svn-id: http://svn.ohwr.org/fmc-tdc@36 85dfdc96-de2c-444c-878d-45b388be74a9
parent cb30b5d1
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000E02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 02000064
rrcmd w 0:80014 080003E8
rrcmd w 0:80018 000000FF
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
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#Build: Synplify Pro D-2010.03, Build 093R, Feb 19 2010
#install: /afs/cern.ch/project/parc/elec/synplify/D-2010.03
#OS: Linux
#Hostname: lxparc41.cern.ch
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/syn_tdc.edf 1311271086
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_64x512.ngc 1311271059
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_32x512.ngc 1311271059
OK
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Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Thu Jul 21 20:02:16 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
err_flag_i_IBUF
int_flag_i_IBUF
p_wr_req_i(0)_IBUF
p_wr_req_i(1)_IBUF
pll_refmon_i_IBUF
pll_sdo_i_IBUF
pll_status_i_IBUF
tx_error_i_IBUF
vc_rdy_i(0)_IBUF
vc_rdy_i(1)_IBUF
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>4432</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>12280</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>12280</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>11196</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>30.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>36.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>54.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>65.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>87.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>90.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>117.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>117.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>118.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>122.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>9.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>9.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>2.0314</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
#### START OF AREA REPORT #####[
Part: XC6SLX45TFGG484-2 (Xilinx)
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 2683 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2683 (47.45 % Utilization)
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 1736 100 %
MUXCY 314 100 %
XORCY 317 100 %
MULT18x18/MULT18x18S 2 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 2369 (41.90 % Utilization)
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.02 % Utilization)
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 122 100 %
=================================================
Total IO PADS in the block top_tdc: 122 (2.16 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
<html><head><title></title></head><body><a name=TopSummary>
#### START OF AREA REPORT #####[<pre>
Part: XC6SLX45TFGG484-2 (Xilinx)
Click here to go to specific block report:
<a href="rpt_top_tdc_areasrr.htm#top_tdc"><h5 align="center">top_tdc</h5></a><br><a name=top_tdc>
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 2683 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2683 (47.45 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 1736 100 %
MUXCY 314 100 %
XORCY 317 100 %
MULT18x18/MULT18x18S 2 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 2369 (41.90 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.02 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 122 100 %
=================================================
Total IO PADS in the block top_tdc: 122 (2.16 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
</a></body></html>
#########################
### DEFINE VARIABLES ###
#########################
set DesignName "syn_tdc"
set FamilyName "SPARTAN6"
set DeviceName "XC6SLX45T"
set PackageName "FGG484"
set SpeedGrade "-2"
set TopModule "top_tdc"
set EdifFile "syn_tdc.edf"
if {![file exists $DesignName.ise]} {
project new $DesignName.ise
project set family $FamilyName
project set device $DeviceName
project set package $PackageName
project set speed $SpeedGrade
xfile add $EdifFile
if {[file exists synplicity.ucf]} {
xfile add synplicity.ucf
}
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project close
}
file delete -force $DesignName\_xdb
project open $DesignName.ise
process run "Implement Design" -force rerun_all
project close
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/run_options.txt
#-- Written on Thu Jul 21 19:57:38 2011
#project files
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -constraint "./tdc_syn_constraints.sdc"
#implementation: "test_tdc_acam"
impl -add test_tdc_acam -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./test_tdc_acam/syn_tdc.edf"
impl -active "test_tdc_acam"
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/scratchproject.prs
#-- Written on Thu Jul 21 19:57:38 2011
#project files
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -constraint "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc"
#implementation: "test_tdc_acam"
impl -add /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
set_option -include_path /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/syn_tdc.edf"
impl -active "test_tdc_acam"
Release 13.1 ngdbuild O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line:
/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
-uc synplicity.ucf syn_tdc.edf
Executing edif2ngd "syn_tdc.edf" "syn_tdc.ngo"
Release 13.1 - edif2ngd O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 13.1 edif2ngd O.40d (lin64)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Applying constraints in "syn_tdc.ncf" to module "top_tdc"...
Checking Constraint Associations...
Writing module to "syn_tdc.ngo"...
Reading NGO file
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/syn_tdc.
ngo" ...
Loading design module
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_64x
512.ngc"...
Loading design module
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_32x
512.ngc"...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "synplicity.ucf" ...
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
'gnum_interface_block.cmp_clk_in.rx_pll_adv_inst' of type PLL_ADV has been
changed from 'VIRTEX5' to 'SPARTAN6' to correct post-ngdbuild and timing
simulation for this primitive. In order for functional simulation to be
correct, the value of SIM_DEVICE should be changed in this same manner in the
source netlist or constraint file.
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:178 - TNM 'gnum_interface_block_cmp_clk_in_buf_P_clk',
used in period specification 'TS_gnum_interface_block_cmp_clk_in_buf_P_clk',
was traced into PLL_ADV instance
gnum_interface_block.cmp_clk_in.rx_pll_adv_inst. The following new TNM groups
and period specifications were generated at the PLL_ADV output(s):
CLKOUT0: <TIMESPEC TS_gnum_interface_block_un1_cmp_clk_in = PERIOD
"gnum_interface_block_un1_cmp_clk_in"
TS_gnum_interface_block_cmp_clk_in_buf_P_clk / 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'gnum_interface_block_cmp_clk_in_buf_P_clk',
used in period specification 'TS_gnum_interface_block_cmp_clk_in_buf_P_clk',
was traced into PLL_ADV instance
gnum_interface_block.cmp_clk_in.rx_pll_adv_inst. The following new TNM groups
and period specifications were generated at the PLL_ADV output(s):
CLKOUT2: <TIMESPEC TS_gnum_interface_block_cmp_clk_in_rx_pllout_x1_0 = PERIOD
"gnum_interface_block_cmp_clk_in_rx_pllout_x1_0"
TS_gnum_interface_block_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%>
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Total memory usage is 340864 kilobytes
Writing NGD file "syn_tdc.ngd" ...
Total REAL time to NGDBUILD completion: 20 sec
Total CPU time to NGDBUILD completion: 17 sec
Writing NGDBUILD log file "syn_tdc.bld"...
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fsm_encoding {22687681} onehot
fsm_state_encoding {22687681} idle {0000000}
fsm_state_encoding {22687681} rd_start {0000011}
fsm_state_encoding {22687681} read {0000101}
fsm_state_encoding {22687681} rd_ack {0001001}
fsm_state_encoding {22687681} wr_start {0010001}
fsm_state_encoding {22687681} write {0100001}
fsm_state_encoding {22687681} wr_ack {1000001}
fsm_registers {22687681} {acam_data_st[0]} {acam_data_st[1]} {acam_data_st[2]} {acam_data_st[3]} {acam_data_st[4]} {acam_data_st[5]} {acam_data_st_i[6]}
fsm_encoding {1515541552} onehot
fsm_state_encoding {1515541552} 0000 {000000001}
fsm_state_encoding {1515541552} 0001 {000000010}
fsm_state_encoding {1515541552} 0010 {000000100}
fsm_state_encoding {1515541552} 0011 {000001000}
fsm_state_encoding {1515541552} 0100 {000010000}
fsm_state_encoding {1515541552} 0101 {000100000}
fsm_state_encoding {1515541552} 0110 {001000000}
fsm_state_encoding {1515541552} 0111 {010000000}
fsm_state_encoding {1515541552} 1001 {100000000}
fsm_registers {1515541552} {state[0]} {state[1]} {state[2]} {state[3]} {state[4]} {state[5]} {state[6]} {state[7]} {state[8]}
fsm_encoding {1414141413} sequential
fsm_state_encoding {1414141413} 0000 {0}
fsm_state_encoding {1414141413} 0001 {1}
fsm_registers {1414141413} {state[0]}
fsm_encoding {1414141414} sequential
fsm_state_encoding {1414141414} 0000 {0}
fsm_state_encoding {1414141414} 0001 {1}
fsm_registers {1414141414} {state[0]}
fsm_encoding {2634443445} sequential
fsm_state_encoding {2634443445} wb_idle {00}
fsm_state_encoding {2634443445} wb_read_fifo {01}
fsm_state_encoding {2634443445} wb_cycle {10}
fsm_state_encoding {2634443445} wb_wait_ack {11}
fsm_registers {2634443445} {wishbone_current_state[1]} {wishbone_current_state[0]}
fsm_encoding {2624842486} sequential
fsm_state_encoding {2624842486} l2p_idle {00}
fsm_state_encoding {2624842486} l2p_header {01}
fsm_state_encoding {2624842486} l2p_data {10}
fsm_registers {2624842486} {l2p_read_cpl_current_state[1]} {l2p_read_cpl_current_state[0]}
fsm_encoding {2732743277} onehot
fsm_state_encoding {2732743277} dma_idle {0000001}
fsm_state_encoding {2732743277} dma_start_transfer {0000010}
fsm_state_encoding {2732743277} dma_transfer {0000100}
fsm_state_encoding {2732743277} dma_start_chain {0001000}
fsm_state_encoding {2732743277} dma_chain {0010000}
fsm_state_encoding {2732743277} dma_error {0100000}
fsm_state_encoding {2732743277} dma_abort {1000000}
fsm_registers {2732743277} {dma_ctrl_current_state[0]} {dma_ctrl_current_state[1]} {dma_ctrl_current_state[2]} {dma_ctrl_current_state[3]} {dma_ctrl_current_state[4]} {dma_ctrl_current_state[5]} {dma_ctrl_current_state[6]}
fsm_encoding {2831243128} onehot
fsm_state_encoding {2831243128} l2p_idle {00000001}
fsm_state_encoding {2831243128} l2p_wait_data {00000010}
fsm_state_encoding {2831243128} l2p_header {00000100}
fsm_state_encoding {2831243128} l2p_addr_h {00001000}
fsm_state_encoding {2831243128} l2p_addr_l {00010000}
fsm_state_encoding {2831243128} l2p_data {00100000}
fsm_state_encoding {2831243128} l2p_last_data {01000000}
fsm_state_encoding {2831243128} l2p_wait_rdy {10000000}
fsm_registers {2831243128} {l2p_dma_current_state[0]} {l2p_dma_current_state[1]} {l2p_dma_current_state[2]} {l2p_dma_current_state[3]} {l2p_dma_current_state[4]} {l2p_dma_current_state[5]} {l2p_dma_current_state[6]} {l2p_dma_current_state[7]}
fsm_encoding {2927242729} onehot
fsm_state_encoding {2927242729} p2l_idle {00001}
fsm_state_encoding {2927242729} p2l_header {00010}
fsm_state_encoding {2927242729} p2l_addr_h {00100}
fsm_state_encoding {2927242729} p2l_addr_l {01000}
fsm_state_encoding {2927242729} p2l_wait_read_completion {10000}
fsm_registers {2927242729} {p2l_dma_current_state[0]} {p2l_dma_current_state[1]} {p2l_dma_current_state[2]} {p2l_dma_current_state[3]} {p2l_dma_current_state[4]}
fsm_encoding {32172717210} onehot
fsm_state_encoding {32172717210} start {00000}
fsm_state_encoding {32172717210} sending_instruction {00011}
fsm_state_encoding {32172717210} sending_data {00101}
fsm_state_encoding {32172717210} rest {01001}
fsm_state_encoding {32172717210} done {10001}
fsm_registers {32172717210} {pll_init_st[0]} {pll_init_st[1]} {pll_init_st[2]} {pll_init_st[3]} {pll_init_st_i[4]}
<html>
<head>
<title>syntmp/syn_tdc_srr.htm log file</title>
</head>
<frameset cols="20%, 80%">
<frameset rows="70%, 30%">
<frame src="syntmp/syn_tdc_toc.htm" name="tocFrame">
<frame src="syntmp/syn_tdc_flink.htm" name="linkFrame">
</frameset>
<frame src="syntmp/syn_tdc_srr.htm" name="srrFrame">
</frameset>
</html>
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#
# Constraints generated by Synplify Pro map510rc, Build 068R
#
# Location Constraints
NET "rst_n_a_i" LOC="N20" ;
NET "p2l_clk_p_i" LOC="M20" ;
NET "p2l_clk_n_i" LOC="M19" ;
NET "p2l_data_i(0)" LOC="K20" ;
NET "p2l_data_i(1)" LOC="H22" ;
NET "p2l_data_i(2)" LOC="H21" ;
NET "p2l_data_i(3)" LOC="L17" ;
NET "p2l_data_i(4)" LOC="K17" ;
NET "p2l_data_i(5)" LOC="G22" ;
NET "p2l_data_i(6)" LOC="G20" ;
NET "p2l_data_i(7)" LOC="K18" ;
NET "p2l_data_i(8)" LOC="K19" ;
NET "p2l_data_i(9)" LOC="H20" ;
NET "p2l_data_i(10)" LOC="J19" ;
NET "p2l_data_i(11)" LOC="E22" ;
NET "p2l_data_i(12)" LOC="E20" ;
NET "p2l_data_i(13)" LOC="F22" ;
NET "p2l_data_i(14)" LOC="F21" ;
NET "p2l_data_i(15)" LOC="H19" ;
NET "p2l_dframe_i" LOC="J22" ;
NET "p2l_valid_i" LOC="L19" ;
NET "p2l_rdy_o" LOC="J16" ;
#(pad missing) NET "p_wr_req_i[0]" LOC="M22" ;
#(pad missing) NET "p_wr_req_i[1]" LOC="M21" ;
NET "p_wr_rdy_o(0)" LOC="L15" ;
NET "p_wr_rdy_o(1)" LOC="K16" ;
NET "rx_error_o" LOC="J17" ;
#(pad missing) NET "vc_rdy_i[0]" LOC="B21" ;
#(pad missing) NET "vc_rdy_i[1]" LOC="B22" ;
NET "l2p_clk_p_o" LOC="K21" ;
NET "l2p_clk_n_o" LOC="K22" ;
NET "l2p_data_o(0)" LOC="P16" ;
NET "l2p_data_o(1)" LOC="P21" ;
NET "l2p_data_o(2)" LOC="P18" ;
NET "l2p_data_o(3)" LOC="T20" ;
NET "l2p_data_o(4)" LOC="V21" ;
NET "l2p_data_o(5)" LOC="V19" ;
NET "l2p_data_o(6)" LOC="W22" ;
NET "l2p_data_o(7)" LOC="Y22" ;
NET "l2p_data_o(8)" LOC="P22" ;
NET "l2p_data_o(9)" LOC="R22" ;
NET "l2p_data_o(10)" LOC="T21" ;
NET "l2p_data_o(11)" LOC="T19" ;
NET "l2p_data_o(12)" LOC="V22" ;
NET "l2p_data_o(13)" LOC="V20" ;
NET "l2p_data_o(14)" LOC="W20" ;
NET "l2p_data_o(15)" LOC="Y21" ;
NET "l2p_dframe_o" LOC="U22" ;
NET "l2p_valid_o" LOC="T18" ;
NET "l2p_edb_o" LOC="U20" ;
NET "l2p_rdy_i" LOC="U19" ;
NET "l_wr_rdy_i(0)" LOC="R20" ;
NET "l_wr_rdy_i(1)" LOC="T22" ;
NET "p_rd_d_rdy_i(0)" LOC="N16" ;
NET "p_rd_d_rdy_i(1)" LOC="P19" ;
#(pad missing) NET "tx_error_i" LOC="M17" ;
NET "irq_p_o" LOC="U16" ;
NET "spare_o" LOC="AB19" ;
NET "acam_refclk_i" LOC="E16" ;
NET "pll_ld_i" LOC="C18" ;
#(pad missing) NET "pll_refmon_i" LOC="D17" ;
#(pad missing) NET "pll_sdo_i" LOC="AB18" ;
#(pad missing) NET "pll_status_i" LOC="Y18" ;
NET "tdc_clk_p_i" LOC="L20" ;
NET "tdc_clk_n_i" LOC="L22" ;
NET "pll_cs_o" LOC="Y17" ;
NET "pll_dac_sync_o" LOC="AB16" ;
NET "pll_sdi_o" LOC="AA18" ;
NET "pll_sclk_o" LOC="AB17" ;
#(pad missing) NET "err_flag_i" LOC="V11" ;
#(pad missing) NET "int_flag_i" LOC="W11" ;
NET "start_dis_o" LOC="T15" ;
NET "start_from_fpga_o" LOC="W17" ;
NET "stop_dis_o" LOC="U15" ;
NET "data_bus_io(0)" LOC="W6" ;
NET "data_bus_io(1)" LOC="Y6" ;
NET "data_bus_io(2)" LOC="V7" ;
NET "data_bus_io(3)" LOC="W8" ;
NET "data_bus_io(4)" LOC="T8" ;
NET "data_bus_io(5)" LOC="AA12" ;
NET "data_bus_io(6)" LOC="U8" ;
NET "data_bus_io(7)" LOC="AB12" ;
NET "data_bus_io(8)" LOC="Y5" ;
NET "data_bus_io(9)" LOC="AB5" ;
NET "data_bus_io(10)" LOC="R9" ;
NET "data_bus_io(11)" LOC="R8" ;
NET "data_bus_io(12)" LOC="AA6" ;
NET "data_bus_io(13)" LOC="AB6" ;
NET "data_bus_io(14)" LOC="U9" ;
NET "data_bus_io(15)" LOC="V9" ;
NET "data_bus_io(16)" LOC="Y7" ;
NET "data_bus_io(17)" LOC="AB7" ;
NET "data_bus_io(18)" LOC="AA8" ;
NET "data_bus_io(19)" LOC="AB8" ;
NET "data_bus_io(20)" LOC="T10" ;
NET "data_bus_io(21)" LOC="U10" ;
NET "data_bus_io(22)" LOC="W10" ;
NET "data_bus_io(23)" LOC="Y10" ;
NET "data_bus_io(24)" LOC="Y9" ;
NET "data_bus_io(25)" LOC="AB9" ;
NET "data_bus_io(26)" LOC="AA4" ;
NET "data_bus_io(27)" LOC="AB4" ;
NET "ef1_i" LOC="W12" ;
NET "ef2_i" LOC="R11" ;
NET "lf1_i" LOC="Y12" ;
NET "lf2_i" LOC="T11" ;
NET "address_o(0)" LOC="T12" ;
NET "address_o(1)" LOC="U12" ;
NET "address_o(2)" LOC="Y15" ;
NET "address_o(3)" LOC="AB15" ;
NET "cs_n_o" LOC="T14" ;
NET "oe_n_o" LOC="V13" ;
NET "rd_n_o" LOC="AB13" ;
NET "wr_n_o" LOC="Y13" ;
NET "mute_inputs_o" LOC="C19" ;
NET "tdc_led_status_o" LOC="W13" ;
NET "tdc_led_trig1_o" LOC="W14" ;
NET "tdc_led_trig2_o" LOC="Y14" ;
NET "tdc_led_trig3_o" LOC="Y16" ;
NET "tdc_led_trig4_o" LOC="W15" ;
NET "tdc_led_trig5_o" LOC="V17" ;
NET "term_en_1_o" LOC="W18" ;
NET "term_en_2_o" LOC="B20" ;
NET "term_en_3_o" LOC="A20" ;
NET "term_en_4_o" LOC="H10" ;
NET "term_en_5_o" LOC="E6" ;
NET "spec_aux0_i" LOC="C22" ;
NET "spec_aux1_i" LOC="D21" ;
NET "spec_aux2_o" LOC="G19" ;
NET "spec_aux3_o" LOC="F20" ;
NET "spec_aux4_o" LOC="F18" ;
NET "spec_aux5_o" LOC="C20" ;
NET "spec_led_green_o" LOC="E5" ;
NET "spec_led_red_o" LOC="D5" ;
NET "spec_clk_i" LOC="H12" ;
# End of generated constraints
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="2">
<CmdHistory>
</CmdHistory>
</DesignSummary>
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#
# Constraints generated by Synplify Pro map510rc, Build 068R
#
# Period Constraints
#Begin clock constraints
NET "gnum_interface_block.cmp_clk_in.buf_P_clk" TNM_NET = "gnum_interface_block_cmp_clk_in_buf_P_clk";
TIMESPEC "TS_gnum_interface_block_cmp_clk_in_buf_P_clk" = PERIOD "gnum_interface_block_cmp_clk_in_buf_P_clk" 5.000 ns HIGH 50.00%;
NET "gnum_interface_block.cmp_clk_in.buf_pll_fb_clk" TNM_NET = "gnum_interface_block_cmp_clk_in_buf_pll_fb_clk";
TIMESPEC "TS_gnum_interface_block_cmp_clk_in_buf_pll_fb_clk" = PERIOD "gnum_interface_block_cmp_clk_in_buf_pll_fb_clk" 5.000 ns HIGH 50.00%;
NET "gnum_interface_block.cmp_clk_in.rx_pllout_x1" TNM_NET = "gnum_interface_block_cmp_clk_in_rx_pllout_x1";
TIMESPEC "TS_gnum_interface_block_cmp_clk_in_rx_pllout_x1" = PERIOD "gnum_interface_block_cmp_clk_in_rx_pllout_x1" 5.000 ns HIGH 50.00%;
NET "spec_clk_i" TNM_NET = "spec_clk_i";
TIMESPEC "TS_spec_clk_i" = PERIOD "spec_clk_i" 50.000 ns HIGH 50.00%;
NET "tdc_clk_p_i" TNM_NET = "tdc_clk_p_i";
TIMESPEC "TS_tdc_clk_p_i" = PERIOD "tdc_clk_p_i" 8.000 ns HIGH 50.00%;
#End clock constraints
# Output Constraints
NET "pll_cs_o" TNM = "pll_cs_o";
NET "pll_sdi_o" TNM = "pll_cs_o";
NET "pll_sclk_o" TNM = "pll_cs_o";
TIMEGRP "pll_cs_o" OFFSET = OUT: 48.000 : AFTER spec_clk_i;
NET "data_bus_io(*)" TNM = "data_bus_io___";
NET "address_o(*)" TNM = "data_bus_io___";
TIMEGRP "data_bus_io___" OFFSET = OUT: 6.000 : AFTER tdc_clk_p_i;
NET "rx_error_o" TNM = "rx_error_o";
NET "l2p_edb_o" TNM = "rx_error_o";
TIMESPEC TS_rx_error_o_gnum_interface_block_cmp_clk_in_rx_pllout_x1 = FROM "gnum_interface_block_cmp_clk_in_rx_pllout_x1" TO "rx_error_o" 3.000 ns;
# Input Constraints
NET "acam_refclk_i" TNM = "acam_refclk_i";
NET "ef1_i" TNM = "acam_refclk_i";
NET "ef2_i" TNM = "acam_refclk_i";
NET "lf1_i" TNM = "acam_refclk_i";
NET "lf2_i" TNM = "acam_refclk_i";
NET "data_bus_io(*)" TNM = "acam_refclk_i";
TIMEGRP "acam_refclk_i" OFFSET = IN: 6.000 : BEFORE tdc_clk_p_i;
NET "l2p_rdy_i" TNM = "l2p_rdy_i";
TIMESPEC TS_l2p_rdy_i_gnum_interface_block_cmp_clk_in_rx_pllout_x1 = FROM "l2p_rdy_i" TO "gnum_interface_block_cmp_clk_in_rx_pllout_x1" 3.000 ns;
# 1037 : define_false_path -to { p:cs_n_o }
NET "cs_n_o" TNM = "to_1037_0";
TIMESPEC "TS_1037_0" = TO "to_1037_0" TIG;
# 1038 : define_false_path -to { p:wr_n_o }
NET "wr_n_o" TNM = "to_1038_0";
TIMESPEC "TS_1038_0" = TO "to_1038_0" TIG;
# 1039 : define_false_path -to { p:rd_n_o }
NET "rd_n_o" TNM = "to_1039_0";
TIMESPEC "TS_1039_0" = TO "to_1039_0" TIG;
# 1040 : define_false_path -from { p:spec_aux0_i }
NET "spec_aux0_i" TNM = "from_1040_0";
TIMESPEC "TS_1040_0" = FROM "from_1040_0" TIG;
# 1041 : define_false_path -from { p:spec_aux1_i }
NET "spec_aux1_i" TNM = "from_1041_0";
TIMESPEC "TS_1041_0" = FROM "from_1041_0" TIG;
# 1042 : define_false_path -to { p:spec_aux2_o }
NET "spec_aux2_o" TNM = "to_1042_0";
TIMESPEC "TS_1042_0" = TO "to_1042_0" TIG;
# 1043 : define_false_path -to { p:spec_aux3_o }
NET "spec_aux3_o" TNM = "to_1043_0";
TIMESPEC "TS_1043_0" = TO "to_1043_0" TIG;
# 1046 : define_false_path -to { p:spec_led_green_o }
NET "spec_led_green_o" TNM = "to_1046_0";
TIMESPEC "TS_1046_0" = TO "to_1046_0" TIG;
# 1047 : define_false_path -to { p:spec_led_red_o }
NET "spec_led_red_o" TNM = "to_1047_0";
TIMESPEC "TS_1047_0" = TO "to_1047_0" TIG;
# 1048 : define_false_path -to { p:tdc_led_status_o }
NET "tdc_led_status_o" TNM = "to_1048_0";
TIMESPEC "TS_1048_0" = TO "to_1048_0" TIG;
# 1053 : define_false_path -to { p:tdc_led_trig5_o }
NET "tdc_led_trig5_o" TNM = "to_1053_0";
TIMESPEC "TS_1053_0" = TO "to_1053_0" TIG;
# 1054 : define_false_path -to { p:start_from_fpga_o }
NET "start_from_fpga_o" TNM = "to_1054_0";
TIMESPEC "TS_1054_0" = TO "to_1054_0" TIG;
# Unused constraints (intentionally commented out)
# define_false_path -to { p:spec_aux4_o }
# define_false_path -to { p:spec_aux5_o }
# define_false_path -to { p:tdc_led_trig1_o }
# define_false_path -to { p:tdc_led_trig2_o }
# define_false_path -to { p:tdc_led_trig3_o }
# define_false_path -to { p:tdc_led_trig4_o }
# Location Constraints
PIN "clks_rsts_mgment.spec_clk_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "clks_rsts_mgment.tdc_clk125_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gnum_interface_block.cmp_clk_in.bufg_135.O" CLOCK_DEDICATED_ROUTE = FALSE;
# End of generated constraints
Release 13.1 - Bitgen O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/.
"top_tdc" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -2
Thu Jul 21 20:02:40 2011
/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/bin/lin64/unwrapped/bitgen par_tdc.ncd tdc
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable* |
+----------------------+----------------------+
| DebugBitstream | No* |
+----------------------+----------------------+
| ConfigRate | 2* |
+----------------------+----------------------+
| StartupClk | Cclk* |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup* |
+----------------------+----------------------+
| TckPin | Pullup* |
+----------------------+----------------------+
| TdiPin | Pullup* |
+----------------------+----------------------+
| TdoPin | Pullup* |
+----------------------+----------------------+
| TmsPin | Pullup* |
+----------------------+----------------------+
| UnusedPin | Pulldown* |
+----------------------+----------------------+
| GWE_cycle | 6* |
+----------------------+----------------------+
| GTS_cycle | 5* |
+----------------------+----------------------+
| LCK_cycle | NoWait* |
+----------------------+----------------------+
| DONE_cycle | 4* |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No* |
+----------------------+----------------------+
| DonePipe | No* |
+----------------------+----------------------+
| Security | None* |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No* |
+----------------------+----------------------+
| Reset_on_err | No* |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No* |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk* |
+----------------------+----------------------+
| sw_gwe_cycle | 5* |
+----------------------+----------------------+
| sw_gts_cycle | 4* |
+----------------------+----------------------+
| multipin_wakeup | No* |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No* |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | None* |
+----------------------+----------------------+
| spi_buswidth | 1* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No* |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
No constraints file was processed.
Running DRC.
WARNING:PhysDesignRules:367 - The signal <vc_rdy_i(0)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <vc_rdy_i(1)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p_wr_req_i(0)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p_wr_req_i(1)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tx_error_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pll_sdo_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pll_refmon_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <err_flag_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pll_status_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <int_flag_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
DRC detected 0 errors and 11 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "tdc.bit".
Bitstream generation is complete.
Release 13.1 Drc O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Thu Jul 21 20:02:40 2011
drc -z par_tdc.ncd
WARNING:PhysDesignRules:367 - The signal <vc_rdy_i(0)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <vc_rdy_i(1)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p_wr_req_i(0)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <p_wr_req_i(1)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tx_error_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pll_sdo_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pll_refmon_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <err_flag_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pll_status_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <int_flag_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
DRC detected 0 errors and 11 warnings. Please see the previously displayed
individual error or warning messages for more details.
INFILE=/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/par_tdc.ncd
OUTFILE=/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/tdc.bit
FAMILY=Spartan6
PART=xc6slx45t-2fgg484
WORKINGDIR=/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam
LICENSE=ISE
USER_INFO=174122087_174122088_206270080_665
This diff is collapsed.
This diff is collapsed.
Release 13.1 - WebTalk (O.40d)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
WebTalk Summary
----------------
INFO:WebTalk:3 - WebTalk is disabled.
INFO:WebTalk:9 - WebTalk Install setting is OFF.
INFO:WebTalk:6 - WebTalk User setting is ON.
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