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FMC TDC 1ns 5cha - Gateware
Commit d23de3f5 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: various fixes: 

- squeezed A24 address range to 0.5 MB (to fit a full 24-slot VME crate with TDCs)
- fixed IRQ line synchronization issue
parent 35b478e1
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Showing with 891 additions and 1169 deletions
vme64x-core @ e98eb58c
Subproject commit 01d2273ff6ad847c9b8550104670ac328bbfe313
Subproject commit e98eb58ca8757be8fdf4117d0d1d1c8bb2e238bc
hdl/rtl/circular_buffer.vhd
View file @ d23de3f5
......@@ -281,7 +281,7 @@ begin
g_data_width => 32,
g_size => 256,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_addr_conflict_resolution => "write_first",
g_dual_clock => true)
port map (
rst_n_i => rst_n_sys_i,
......@@ -290,12 +290,12 @@ begin
aa_i => tstamp_wr_adr_i(7 downto 0),
da_i => tstamp_wr_dat_i(32*i + 31 downto 32*i),
clkb_i => clk_sys_i,
web_i => tstamp_rd_we(i),
web_i => '0',
ab_i => tdc_mem_wb_adr_i(9 downto 2),
db_i => tdc_mem_wb_dat_i,
qb_o => mb_data(i));
tstamp_rd_we(i) <= '1' when unsigned(tdc_mem_wb_adr_i(1 downto 0)) = i else '0';
-- tstamp_rd_we(i) <= '1' when unsigned(tdc_mem_wb_adr_i(1 downto 0)) = i else '0';
process(clk_sys_i)
begin
......
hdl/rtl/clks_rsts_manager.vhd
View file @ d23de3f5
......@@ -582,11 +582,7 @@ begin
if rst_in_synch(1) = '1' then
divider <= (others => '0');
else
if(divider = "111") then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
divider <= divider + 1;
end if;
end if;
end process;
......
hdl/rtl/fmc_tdc_core.vhd
View file @ d23de3f5
......@@ -281,28 +281,8 @@ architecture rtl of fmc_tdc_core is
signal rst_sys: std_logic;
-- Chipscope
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -628,41 +608,6 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
-- ACAM start_dis, not used --
---------------------------------------------------------------------------------------------------
start_dis_o <= '0';
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_tdc_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--
-- chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
--
-- TRIG0(0) <= utc_p;
-- TRIG0(1) <= ef1_i;
-- TRIG0(2) <= acam_intflag_f_edge_p;
-- TRIG0(15 downto 3) <= roll_over_nb(12 downto 0);
-- TRIG0(16) <= start_from_fpga;
-- TRIG0(24 downto 17) <= retrig_nb_offset(7 downto 0);
-- TRIG0(31 downto 25) <= clk_i_cycles_offset(6 downto 0);
--
-- TRIG1(30 downto 0) <= acam_tstamp1(30 downto 0);
-- TRIG1(31) <= acam_tstamp1_ok_p;
--
-- TRIG2(31 downto 0) <= utc(31 downto 0);
--
-- TRIG3(0) <= tdc_in_fpga_1_i;
-- TRIG3(1) <= roll_over_incr_recent;
-- TRIG3(2) <= wrabbit_tai_p_i;
-- TRIG3(31 downto 3) <= current_retrig_nb(28 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ d23de3f5
......@@ -106,10 +106,10 @@ use work.wishbone_pkg.all;
--=================================================================================================
entity fmc_tdc_mezzanine is
generic
(g_with_wrabbit_core : boolean := FALSE;
g_span : integer := 32;
g_width : integer := 32;
g_simulation : boolean := FALSE);
(g_with_wrabbit_core : boolean := false;
g_span : integer := 32;
g_width : integer := 32;
g_simulation : boolean := false);
port
-- TDC core
(
......@@ -222,11 +222,11 @@ architecture rtl of fmc_tdc_mezzanine is
-- WISHBONE crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
(0 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00011000"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00012000"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00013000"),
4 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE, x"00014000"));
(0 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00002000"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00003000"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00004000"),
4 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE, x"00005000"));
---------------------------------------------------------------------------------------------------
......@@ -258,6 +258,8 @@ architecture rtl of fmc_tdc_mezzanine is
signal wrabbit_synched : std_logic;
signal irq_tstamp_sreg : std_logic_vector(7 downto 0);
function f_wb_shift_address_word ( w: t_wishbone_master_out ) return t_wishbone_master_out is
variable r : t_wishbone_master_out;
......@@ -282,12 +284,12 @@ begin
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- CSR wishbone address decoder
-- 0x10000 -> TDC core configuration
-- 0x11000 -> TDC mezzanine board 1-Wire
-- 0x12000 -> EIC for TDC core
-- 0x13000 -> TDC mezzanine board EEPROM I2C
-- 0x14000 -> TDC core timestamps retrieval
-- 0x0000 -> SDB descriptor
-- 0x1000 -> TDC mezzanine board 1-Wire
-- 0x2000 -> TDC core registers
-- 0x3000 -> TDC core interrupt controller (EIC)
-- 0x4000 -> TDC mezzanine board I2C eeprom
-- 0x5000 -> TDC core circular buffer
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar : xwb_sdb_crossbar
......@@ -381,6 +383,29 @@ begin
direct_timestamp_stb_o => direct_timestamp_stb_o);
p_extend_irq : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
irq_tstamp_sreg <= (others => '0');
else
if(irq_tstamp_p = '1')then
irq_tstamp_sreg <= (others => '1');
else
irq_tstamp_sreg <= '0' & irq_tstamp_sreg(7 downto 1);
end if;
end if;
end if;
end process;
u_sync_irq_line : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
data_i => irq_tstamp_sreg(0),
ppulse_o => irq_tstamp_p_sys);
---------------------------------------------------------------------------------------------------
-- WHITE RABBIT STUFF --
-- only synthesized if g_with_wrabbit_core is TRUE --
......@@ -476,16 +501,6 @@ begin
irq_tdc_time_i => irq_time_p_sys,
irq_tdc_acam_err_i => irq_acam_err_p_sys);
cmp_sync_irq_tstamp: gc_pulse_synchronizer2
port map (
clk_in_i => clk_tdc_i,
rst_in_n_i => rst_ref_0_n,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_sys_n_i,
d_p_i => irq_tstamp_p,
q_p_o => irq_tstamp_p_sys);
irq_time_p_sys <= '0'; -- we don't need these in the driver
irq_acam_err_p_sys <= '0';
......@@ -509,12 +524,12 @@ begin
slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
desc_o => open,
scl_pad_i(0) => i2c_scl_i,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => i2c_sda_i,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n);
scl_pad_i => i2c_scl_i,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => i2c_sda_i,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
i2c_sda_oen_o <= sys_sda_oe_n;
......
hdl/rtl/reg_ctrl.vhd
View file @ d23de3f5
......@@ -72,6 +72,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
--=================================================================================================
......@@ -186,21 +187,36 @@ architecture rtl of reg_ctrl is
signal wb_out : t_wishbone_slave_out;
signal rst_n_tdc : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
signal cc_rst_n : std_logic;
signal cc_rst_n_or_sys : std_logic;
begin
rst_n_tdc <= not rst_tdc_i;
wb_out.stall <= '0';
wb_out.err <= '0';
wb_out.rty <= '0';
u_sync_tdc_reset : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
data_i => rst_n_tdc,
synced_o => cc_rst_n);
cc_rst_n_or_sys <= cc_rst_n and rst_n_sys_i;
cmp_clks_crossing : xwb_clock_crossing
port map
(slave_clk_i => clk_sys_i, -- Slave control port: VME interface at 62.5 MHz
slave_rst_n_i => rst_n_sys_i,
slave_rst_n_i => cc_rst_n_or_sys, -- reset the slave port also when resetting the TDC
slave_i => slave_i,
slave_o => slave_o,
master_clk_i => clk_tdc_i,
......@@ -225,7 +241,7 @@ begin
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
elsif(wb_in.cyc /= '1') then
elsif(wb_in.cyc = '0') then
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
......@@ -347,7 +363,7 @@ begin
elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then
if reg_adr = c_STARTING_UTC_ADR then
if reg_adr = c_STARTING_UTC_ADR then
starting_utc <= wb_in.dat;
end if;
......
hdl/syn/svec/wr_svec_tdc.xise
View file @ d23de3f5
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/svec/Manifest.py
View file @ d23de3f5
......@@ -5,5 +5,5 @@ vlog_opt="+incdir+../../sim +incdir+../include/vme64x_bfm +incdir+../include "
files = [ "main.sv" ]
modules = { "local" : [ "../../top/svec/with_wrabbit" ] }
modules = { "local" : [ "../../top/svec" ] }
hdl/top/svec/synthesis_descriptor.vhd
View file @ d23de3f5
......@@ -6,7 +6,7 @@
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Last update: 2015-04-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -46,7 +46,7 @@ constant c_sdb_synthesis_info : t_sdb_synthesis :=
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20150326",
syn_date => x"20150408",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
......@@ -54,4 +54,4 @@ constant c_sdb_repo_url : t_sdb_repo_url :=
repo_url => "http://svn.ohwr.org/fmc-tdc "
);
end package synthesis_descriptor;
\ No newline at end of file
end package synthesis_descriptor;
hdl/top/svec/wr_svec_tdc.vhd
View file @ d23de3f5
......@@ -873,6 +873,9 @@ begin
-- VME CORE --
---------------------------------------------------------------------------------------------------
U_VME_Core : xvme64x_core
generic map (
g_clock_freq => 62500000,
g_adem_a24 => x"fff80000")
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
......
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