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FMC TDC 1ns 5cha - Gateware
Commit d34e1405 authored by egousiou's avatar egousiou
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added logic for controlling the mezzanine DAC that controls the OSC1 that controls the PLL! 

added leds_manager unit to remove logic from top level
/!\treatment of 2 bugs in data_formatting (not completed though, check top_tdc.vhd comments) 


git-svn-id: http://svn.ohwr.org/fmc-tdc@76 85dfdc96-de2c-444c-878d-45b388be74a9
parent 14637348
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Showing with 1736 additions and 1416 deletions
hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ d34e1405
......@@ -56,7 +56,7 @@ use work.tdc_core_pkg.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for start_retrig_ctrl
-- Entity declaration for acam_timecontrol_interface
--=================================================================================================
entity acam_timecontrol_interface is
......
hdl/spec/src/rtl/clks_rsts_manager.vhd
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hdl/spec/src/rtl/data_formatting.vhd
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hdl/spec/src/rtl/leds_manager.vhd 0 → 100644
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hdl/spec/src/rtl/reg_ctrl.vhd
View file @ d34e1405
......@@ -136,6 +136,10 @@ entity reg_ctrl is
-- Signal to the data_formatting unit
dacapo_c_rst_p_o : out std_logic; -- clears the dacapo counter
-- Signals to the clks_resets_manager ubit
send_dac_word_p_o : out std_logic; -- starts spi_dac_
dac_word_o : out std_logic_vector(23 downto 0);
-- Signal to the one_hz_gen unit
load_utc_p_o : out std_logic;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
......@@ -157,11 +161,15 @@ end reg_ctrl;
--=================================================================================================
architecture rtl of reg_ctrl is
signal acam_config : config_vector;
signal reg_adr : std_logic_vector(7 downto 0);
signal starting_utc, acam_inputs_en, start_phase, ctrl_reg : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase, irq_tstamp_threshold, irq_time_threshold : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg : std_logic;
signal acam_config : config_vector;
signal reg_adr : std_logic_vector(7 downto 0);
signal starting_utc, acam_inputs_en, start_phase : std_logic_vector(g_width-1 downto 0);
signal ctrl_reg, one_hz_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
signal irq_time_threshold : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg, send_dac_word_p : std_logic;
signal dac_word : std_logic_vector(23 downto 0);
signal pulse_extender_en : std_logic;
signal pulse_extender_c : std_logic_vector(2 downto 0);
--=================================================================================================
-- architecture begin
......@@ -275,7 +283,7 @@ begin
-- to be loaded locally.
-- The following information is received:
-- o acam_inputs_en: for the activation of the stop signals arriving to the ACAM
-- o starting_utc : think not useful......
-- o starting_utc
-- o one_hz_phase : think not useful......
-- o start_phase : think not useful......
TDCcore_config_reg_reception: process (clk_i)
......@@ -286,8 +294,10 @@ begin
starting_utc <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
irq_tstamp_threshold <= (others =>'0');
irq_time_threshold <= (others =>'0');
irq_tstamp_threshold <= x"00000100"; -- default 256 timestamps: full memory
irq_time_threshold <= x"00000078"; -- default 2 minutes
dac_word <= c_DEFAULT_DAC_WORD; -- for DAC Vout = 1.65
elsif gnum_csr_cyc_i = '1' and gnum_csr_stb_i = '1' and gnum_csr_we_i = '1' then
......@@ -307,13 +317,18 @@ begin
one_hz_phase <= gnum_csr_dat_i;
end if;
if reg_adr = c_IRQ_TSTAMP_THRESHOLD then
if reg_adr = c_IRQ_TSTAMP_THRESH_ADR then
irq_tstamp_threshold <= gnum_csr_dat_i;
end if;
if reg_adr = c_IRQ_TIME_THRESHOLD then
if reg_adr = c_IRQ_TIME_THRESH_ADR then
irq_time_threshold <= gnum_csr_dat_i;
end if;
if reg_adr = c_DAC_WORD_ADR then
dac_word <= gnum_csr_dat_i(23 downto 0);
end if;
end if;
end if;
end process;
......@@ -325,6 +340,7 @@ begin
one_hz_phase_o <= one_hz_phase;
irq_tstamp_threshold_o <= irq_tstamp_threshold;
irq_time_threshold_o <= irq_time_threshold;
dac_word_o <= dac_word;
......@@ -370,9 +386,26 @@ begin
acam_rst_p_o <= ctrl_reg(8);
load_utc_p_o <= ctrl_reg(9);
dacapo_c_rst_p_o <= ctrl_reg(10);
-- ctrl_reg bits 11 to 31 not used for the moment!
send_dac_word_p <= ctrl_reg(11);
-- ctrl_reg bits 12 to 31 not used for the moment!
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Pulse_stretcher: Increases the width of the send_dac_word_p pulse so that it can be sampled
-- by the 20 MHz clock of the clks_rsts_manager that is communication with the DAC.
Pulse_stretcher: incr_counter
generic map
(width => 3)
port map
(clk_i => clk_i,
rst_i => send_dac_word_p,
counter_top_i => "111",
counter_incr_en_i => pulse_extender_en,
counter_is_full_o => open,
counter_o => pulse_extender_c);
pulse_extender_en <= '1' when pulse_extender_c < "111" else '0';
send_dac_word_p_o <= pulse_extender_en;
---------------------------------------------------------------------------------------------------
-- Delivery of ACAM and TDC core Readback Registers --
......@@ -420,8 +453,9 @@ begin
acam_inputs_en when c_ACAM_INPUTS_EN_ADR,
start_phase when c_START_PHASE_ADR,
one_hz_phase when c_ONE_HZ_PHASE_ADR,
irq_tstamp_threshold when c_IRQ_TSTAMP_THRESHOLD,
irq_time_threshold when c_IRQ_TIME_THRESHOLD,
irq_tstamp_threshold when c_IRQ_TSTAMP_THRESH_ADR,
irq_time_threshold when c_IRQ_TIME_THRESH_ADR,
x"00" & dac_word when c_DAC_WORD_ADR,
----------------------------------------------------
-- regs written locally by the TDC core units
......
hdl/spec/src/rtl/start_retrig_ctrl.vhd
View file @ d34e1405
......@@ -151,8 +151,9 @@ entity start_retrig_ctrl is
-- OUTPUTS
-- Signals to the data_formatting unit
roll_over_incr_recent_o : out std_logic;
clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
current_roll_over_o : out std_logic_vector(g_width-1 downto 0);
roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
end start_retrig_ctrl;
......@@ -286,7 +287,7 @@ begin
clk_i_cycles_offset <= (others=>'0');
retrig_nb_offset <= (others=>'0');
elsif one_hz_p_i ='1' then
elsif one_hz_p_i = '1' then
clk_i_cycles_offset <= current_cycles;
retrig_nb_offset <= current_retrig_nb;
end if;
......@@ -297,9 +298,11 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- outputs
clk_i_cycles_offset_o <= clk_i_cycles_offset;
retrig_nb_offset_o <= retrig_nb_offset;
current_roll_over_o <= roll_over_c;
roll_over_incr_recent_o <= '1' when unsigned(current_retrig_nb) < 64 else '0';
clk_i_cycles_offset_o <= clk_i_cycles_offset;
retrig_nb_offset_o <= retrig_nb_offset;
roll_over_nb_o <= roll_over_c;
end architecture rtl;
......
hdl/spec/src/rtl/start_retrigger_control.vhd deleted 100644 → 0
View file @ 14637348
----------------------------------------------------------------------------------------------------
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : start retrigger control and internal start number offset generator
-- (start_retrigger_control)
-- author : G. Penacoba
-- date : July 2011
-- version : Revision 1
-- description : launches the start pulses and the ACAM generates the internal start retriggers.
-- Also generates the offset to be added to the start number provided by tha Acam
-- by counting the number of times the 1-Byte counter of the Acam is overloaded.
-- The result is then multiplied by 256 (shifted by 8).
-- dependencies:
-- references :
-- modified by :
--
----------------------------------------------------------------------------------------------------
-- last changes:
----------------------------------------------------------------------------------------------------
-- to do: NEEDS TO BE COMPLETELY REVAMPED AFTER DECISION FOR UNIQUE START. ROLL OVER COUNTER etc..
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for start_retrigger_control
----------------------------------------------------------------------------------------------------
entity start_retrigger_control is
generic(
g_width : integer :=32
);
port(
acam_rise_intflag_p_i : in std_logic;
acam_fall_intflag_p_i : in std_logic;
clk : in std_logic;
one_hz_p_i : in std_logic;
reset_i : in std_logic;
retrig_period_i : in std_logic_vector(g_width-1 downto 0);
clk_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
current_roll_over_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0)
);
end start_retrigger_control;
----------------------------------------------------------------------------------------------------
-- architecture declaration for start_retrigger_control
----------------------------------------------------------------------------------------------------
architecture rtl of start_retrigger_control is
component free_counter is
generic(
width : integer :=32
);
port(
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
);
end component;
component incr_counter
generic(
width : integer :=32
);
port(
clk : in std_logic;
end_value : in std_logic_vector(width-1 downto 0);
incr : in std_logic;
reset : in std_logic;
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
);
end component;
signal acam_fall_intflag_p : std_logic;
signal acam_rise_intflag_p : std_logic;
signal add_roll_over : std_logic;
signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0);
signal current_cycles, current_cycles_2 : std_logic_vector(g_width-1 downto 0);
signal current_cycles_2_2 : unsigned(5 downto 0);
signal current_retrig_nb : std_logic_vector(g_width-1 downto 0);
signal one_hz_p : std_logic;
signal reset : std_logic;
signal retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
signal retrig_nb_reset : std_logic;
signal retrig_p, retrig_p2 : std_logic;
signal retrig_period : std_logic_vector(g_width-1 downto 0);
signal retrig_period_reset : std_logic;
signal roll_over_reset : std_logic;
signal roll_over_value : std_logic_vector(g_width-1 downto 0);
signal cycles_c_restart, current_cycles_2_is_full : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
retrig_period_counter: free_counter
generic map(
width => g_width
)
port map(
clk => clk,
enable => '1',
reset => retrig_period_reset,
start_value => retrig_period,
count_done => retrig_p,
current_value => current_cycles
);
-----------------------------------------------------------------
retrig_period_counter2: incr_counter
generic map
(width => g_width)
port map
(clk => clk,
reset => cycles_c_restart,
end_value => retrig_period_i,
incr => '1',
-------------------------------------------
count_done => open,
current_value => current_cycles_2);
-------------------------------------------
cycles_c_restart <= acam_fall_intflag_p or current_cycles_2_is_full;
current_cycles_2_is_full <= '1' when (unsigned(current_cycles_2) = (unsigned(retrig_period_i) - "1")) else '0';
--(current_cycles_2_2) <= unsigned(current_cycles_2) -1;
-----------------------------------------------------------------
retrig_nb_counter: incr_counter
generic map(
width => g_width
)
port map(
clk => clk,
end_value => x"00000100",
incr => retrig_p,
reset => retrig_nb_reset,
count_done => open,
current_value => current_retrig_nb
);
-- These two counters keep a track of the current internal start retrigger
-- of the Acam in parallel with the Acam itself
roll_over_counter: incr_counter
generic map(
width => g_width
)
port map(
clk => clk,
end_value => x"FFFFFFFF",
incr => add_roll_over,
reset => roll_over_reset,
count_done => open,
current_value => roll_over_value
);
-- This counter keeps track of the number of overflows of the Acam counter
-- for the internal start retrigger
capture_offset: process
begin
if reset ='1' then
clk_cycles_offset <= (others=>'0');
retrig_nb_offset <= (others=>'0');
elsif one_hz_p ='1' then
clk_cycles_offset <= current_cycles;
retrig_nb_offset <= current_retrig_nb;
end if;
wait until clk ='1';
end process;
-- When a new second starts, all values are captured and stored as offsets.
-- when a timestamps arrives, these offset will be subrstracted in order
-- to base the final timestamp with respect to the current second.
retrig_period_reset <= acam_fall_intflag_p;
retrig_nb_reset <= acam_fall_intflag_p;
roll_over_reset <= one_hz_p;
add_roll_over <= acam_fall_intflag_p;
-- inputs
acam_fall_intflag_p <= acam_fall_intflag_p_i;
acam_rise_intflag_p <= acam_rise_intflag_p_i;
one_hz_p <= one_hz_p_i;
reset <= reset_i;
retrig_period <= retrig_period_i;
-- outputs
clk_cycles_offset_o <= clk_cycles_offset;
retrig_nb_offset_o <= retrig_nb_offset;
current_roll_over_o <= roll_over_value;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
hdl/spec/src/rtl/tdc_core_pkg.vhd
View file @ d34e1405
......@@ -71,6 +71,13 @@ package tdc_core_pkg is
constant c_SIM_CLK_PERIOD : std_logic_vector(31 downto 0) := x"0001E848";
---------------------------------------------------------------------------------------------------
-- Constant regarding the Mezzanine DAC configuration --
---------------------------------------------------------------------------------------------------
-- Vout = Vref (DAC_WORD/ 65536); for Vout = 1.65V, with Vref = 2.5V the DAC_WORD = xA8F5
constant c_DEFAULT_DAC_WORD : std_logic_vector(23 downto 0) := x"00A8F5";
---------------------------------------------------------------------------------------------------
-- Constants regarding TDC core and GNUM core addressing --
---------------------------------------------------------------------------------------------------
......@@ -151,9 +158,10 @@ package tdc_core_pkg is
constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 20088 of gnum BAR 0
constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 2008C of gnum BAR 0
constant c_IRQ_TSTAMP_THRESHOLD : std_logic_vector(7 downto 0) := x"24"; -- address 20090 of gnum BAR 0
constant c_IRQ_TIME_THRESHOLD : std_logic_vector(7 downto 0) := x"25"; -- address 20090 of gnum BAR 0
-- constant c_RESERVED0 : std_logic_vector(7 downto 0) := x"26"; -- address 20098 of gnum BAR 0
constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 20090 of gnum BAR 0
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 20090 of gnum BAR 0
constant c_DAC_WORD_ADR : std_logic_vector(7 downto 0) := x"26"; -- address 20098 of gnum BAR 0
-- constant c_RESERVED1 : std_logic_vector(7 downto 0) := x"27"; -- address 2009C of gnum BAR 0
---------------------------------------------------------------------------------------------------
......@@ -266,8 +274,9 @@ package tdc_core_pkg is
acam_intflag_f_edge_p_i : in std_logic;
one_hz_p_i : in std_logic;
----------------------------------------------------------------------
roll_over_incr_recent_o : out std_logic;
clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
current_roll_over_o : out std_logic_vector(g_width-1 downto 0);
roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
----------------------------------------------------------------------
end component;
......@@ -370,6 +379,8 @@ package tdc_core_pkg is
load_utc_p_o : out std_logic;
irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0);
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0);
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
dacapo_c_rst_p_o : out std_logic;
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
......@@ -404,27 +415,29 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component data_formatting
port
(tstamp_wr_wb_ack_i : in std_logic;
tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
acam_tstamp1_i : in std_logic_vector(31 downto 0);
acam_tstamp1_ok_p_i : in std_logic;
acam_tstamp2_i : in std_logic_vector(31 downto 0);
acam_tstamp2_ok_p_i : in std_logic;
clk_i : in std_logic;
dacapo_c_rst_p_i : in std_logic;
rst_i : in std_logic;
clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
current_roll_over_i : in std_logic_vector(31 downto 0);
local_utc_i : in std_logic_vector(31 downto 0);
retrig_nb_offset_i : in std_logic_vector(31 downto 0);
(tstamp_wr_wb_ack_i : in std_logic;
tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
acam_tstamp1_i : in std_logic_vector(31 downto 0);
acam_tstamp1_ok_p_i : in std_logic;
acam_tstamp2_i : in std_logic_vector(31 downto 0);
acam_tstamp2_ok_p_i : in std_logic;
clk_i : in std_logic;
dacapo_c_rst_p_i : in std_logic;
rst_i : in std_logic;
roll_over_incr_recent_i : in std_logic;
clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
roll_over_nb_i : in std_logic_vector(31 downto 0);
local_utc_i : in std_logic_vector(31 downto 0);
retrig_nb_offset_i : in std_logic_vector(31 downto 0);
one_hz_p_i : in std_logic;
----------------------------------------------------------------------
tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0);
tstamp_wr_wb_cyc_o : out std_logic;
tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
tstamp_wr_wb_stb_o : out std_logic;
tstamp_wr_wb_we_o : out std_logic;
tstamp_wr_p_o : out std_logic;
wr_index_o : out std_logic_vector(31 downto 0));
tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0);
tstamp_wr_wb_cyc_o : out std_logic;
tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
tstamp_wr_wb_stb_o : out std_logic;
tstamp_wr_wb_we_o : out std_logic;
tstamp_wr_p_o : out std_logic;
wr_index_o : out std_logic_vector(31 downto 0));
----------------------------------------------------------------------
end component;
......@@ -467,30 +480,66 @@ package tdc_core_pkg is
irq_p_o : out std_logic);
end component irq_controller;
---------------------------------------------------------------------------------------------------
component clks_rsts_manager
generic
(nb_of_reg : integer := 68;
values_for_simulation : boolean := FALSE);
(nb_of_reg : integer := 68);
port
(acam_refclk_i : in std_logic;
pll_ld_i : in std_logic;
pll_refmon_i : in std_logic;
pll_sdo_i : in std_logic;
pll_status_i : in std_logic;
gnum_rst_i : in std_logic;
spec_clk_i : in std_logic;
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
(spec_clk_i : in std_logic;
acam_refclk_i : in std_logic;
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
rst_n_a_i : in std_logic;
pll_ld_i : in std_logic;
pll_refmon_i : in std_logic;
pll_sdo_i : in std_logic;
pll_status_i : in std_logic;
send_dac_word_p_i : in std_logic;
dac_word_i : in std_logic_vector(23 downto 0);
----------------------------------------------------------------------
tdc_clk_o : out std_logic;
internal_rst_o : out std_logic;
spec_clk_o : out std_logic;
gnum_rst_o : out std_logic;
acam_refclk_r_edge_p_o : out std_logic;
internal_rst_o : out std_logic;
pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
spec_clk_o : out std_logic;
tdc_clk_o : out std_logic);
pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
pll_ld_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component leds_manager is
generic
(g_width : integer := 32;
values_for_simulation : boolean := FALSE);
port
(clk_20mhz_i : in std_logic;
clk_125mhz_i : in std_logic;
gnum_rst_i : in std_logic;
internal_rst_i : in std_logic;
pll_ld_i : in std_logic;
spec_aux_butt_1_i : in std_logic;
spec_aux_butt_2_i : in std_logic;
one_hz_p_i : in std_logic;
acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
spec_led_green_o : out std_logic;
spec_led_red_o : out std_logic;
spec_aux_led_1_o : out std_logic;
spec_aux_led_2_o : out std_logic;
spec_aux_led_3_o : out std_logic;
spec_aux_led_4_o : out std_logic);
----------------------------------------------------------------------
end component;
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ d34e1405
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