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FMC TDC 1ns 5cha - Gateware
Commit d7077e06 authored by penacoba's avatar penacoba
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Modifications for large Tstart pulse 


git-svn-id: http://svn.ohwr.org/fmc-tdc@41 85dfdc96-de2c-444c-878d-45b388be74a9
parent 8d74d3fa
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hdl/spec/src/rtl/acam_databus_interface.vhd
View file @ d7077e06
...@@ -79,8 +79,11 @@ signal cyc : std_logic; ...@@ -79,8 +79,11 @@ signal cyc : std_logic;
signal stb : std_logic; signal stb : std_logic;
signal we : std_logic; signal we : std_logic;
signal cs : std_logic; signal cs : std_logic;
signal cs_extend : std_logic;
signal rd : std_logic; signal rd : std_logic;
signal rd_extend : std_logic;
signal wr : std_logic; signal wr : std_logic;
signal wr_extend : std_logic;
signal ack : std_logic; signal ack : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
...@@ -103,9 +106,9 @@ begin ...@@ -103,9 +106,9 @@ begin
case acam_data_st is case acam_data_st is
when idle => when idle =>
ack <= '0'; ack <= '0';
cs <= '0'; cs_extend <= '0';
rd <= '0'; rd_extend <= '0';
wr <= '0'; wr_extend <= '0';
if stb ='1' and cyc ='1' then if stb ='1' and cyc ='1' then
if we = '1' then if we = '1' then
nxt_acam_data_st <= wr_start; nxt_acam_data_st <= wr_start;
...@@ -118,62 +121,66 @@ begin ...@@ -118,62 +121,66 @@ begin
when rd_start => when rd_start =>
ack <= '0'; ack <= '0';
cs <= '1'; cs_extend <= '1';
rd <= '1'; rd_extend <= '1';
wr <= '0'; wr_extend <= '0';
nxt_acam_data_st <= read; nxt_acam_data_st <= read;
when read => when read =>
ack <= '0'; ack <= '0';
cs <= '1'; cs_extend <= '1';
rd <= '1'; rd_extend <= '1';
wr <= '0'; wr_extend <= '0';
nxt_acam_data_st <= rd_ack; nxt_acam_data_st <= rd_ack;
when rd_ack => when rd_ack =>
ack <= '1'; ack <= '1';
cs <= '0'; cs_extend <= '0';
rd <= '0'; rd_extend <= '0';
wr <= '0'; wr_extend <= '0';
nxt_acam_data_st <= idle; nxt_acam_data_st <= idle;
when wr_start => when wr_start =>
ack <= '0'; ack <= '0';
cs <= '1'; cs_extend <= '1';
rd <= '0'; rd_extend <= '0';
wr <= '1'; wr_extend <= '1';
nxt_acam_data_st <= write; nxt_acam_data_st <= write;
when write => when write =>
ack <= '0'; ack <= '0';
cs <= '0'; cs_extend <= '0';
rd <= '0'; rd_extend <= '0';
wr <= '0'; wr_extend <= '0';
nxt_acam_data_st <= wr_ack; nxt_acam_data_st <= wr_ack;
when wr_ack => when wr_ack =>
ack <= '1'; ack <= '1';
cs <= '0'; cs_extend <= '0';
rd <= '0'; rd_extend <= '0';
wr <= '0'; wr_extend <= '0';
nxt_acam_data_st <= idle; nxt_acam_data_st <= idle;
when others => when others =>
ack <= '0'; ack <= '0';
cs <= '0'; cs_extend <= '0';
rd <= '0'; rd_extend <= '0';
wr <= '0'; wr_extend <= '0';
nxt_acam_data_st <= idle; nxt_acam_data_st <= idle;
end case; end case;
end process; end process;
cs <= ((stb and cyc) or cs_extend) and not(ack);
rd <= ((stb and cyc and not(we)) or rd_extend) and not(ack);
wr <= ((stb and cyc and we) or wr_extend) and not(ack);
-- inputs from other blocks -- inputs from other blocks
clk <= clk_i; clk <= clk_i;
reset <= reset_i; reset <= reset_i;
......
hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ d7077e06
...@@ -71,6 +71,7 @@ architecture rtl of acam_timecontrol_interface is ...@@ -71,6 +71,7 @@ architecture rtl of acam_timecontrol_interface is
signal clk : std_logic; signal clk : std_logic;
signal counter_reset : std_logic; signal counter_reset : std_logic;
signal start_trig : std_logic; signal start_trig : std_logic;
signal reset : std_logic; signal reset : std_logic;
signal s_int_flag : unsigned(2 downto 0); signal s_int_flag : unsigned(2 downto 0);
...@@ -117,9 +118,9 @@ begin ...@@ -117,9 +118,9 @@ begin
acam_rise_intflag_p_o <= s_int_flag(1) and not(s_int_flag(0)); acam_rise_intflag_p_o <= s_int_flag(1) and not(s_int_flag(0));
-- generation of the window allowing the start: -- generation of the start pulse and the enable window:
-- every second an external start retrigger is generated by the -- the start pulse originates from an internal signal
-- rising edge of the ref_clk -- at the same time, the StartDis is de-asserted.
window_counter: incr_counter window_counter: incr_counter
generic map( generic map(
...@@ -147,7 +148,7 @@ begin ...@@ -147,7 +148,7 @@ begin
wait until clk ='1'; wait until clk ='1';
end process; end process;
start_pulse_fitter: process start_window_synchronizer: process
begin begin
if reset ='1' then if reset ='1' then
start_window_reg <= (others=>'0'); start_window_reg <= (others=>'0');
......
hdl/spec/src/rtl/one_hz_gen.vhd
View file @ d7077e06
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- entity declaration for one_hz_gen -- entity declaration for one_hz_gen
......
hdl/spec/src/rtl/start_retrigger_control.vhd
View file @ d7077e06
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- entity declaration for start_retrigger_control -- entity declaration for start_retrigger_control
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ d7077e06
...@@ -95,6 +95,8 @@ entity top_tdc is ...@@ -95,6 +95,8 @@ entity top_tdc is
wr_n_o : out std_logic; wr_n_o : out std_logic;
-- other signals on the TDC mezzanine -- other signals on the TDC mezzanine
tdc_in_fpga_5_i : in std_logic;
mute_inputs_o : out std_logic; mute_inputs_o : out std_logic;
tdc_led_status_o : out std_logic; tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic; tdc_led_trig1_o : out std_logic;
...@@ -347,10 +349,10 @@ architecture rtl of top_tdc is ...@@ -347,10 +349,10 @@ architecture rtl of top_tdc is
constant sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0001E848"; -- 1 ms at 125 MHz (tdc board clock) constant sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0001E848"; -- 1 ms at 125 MHz (tdc board clock)
constant syn_clock_period : std_logic_vector(g_width-1 downto 0):=x"07735940"; -- 1 s at 125 MHz (tdc board clock) constant syn_clock_period : std_logic_vector(g_width-1 downto 0):=x"07735940"; -- 1 s at 125 MHz (tdc board clock)
signal spec_led_count_done : std_logic; signal spec_led_blink_done : std_logic;
signal spec_led_period_done : std_logic;
signal spec_led_period : std_logic_vector(g_width-1 downto 0); signal spec_led_period : std_logic_vector(g_width-1 downto 0);
signal tdc_led_count_done : std_logic; signal tdc_led_blink_done : std_logic;
signal tdc_led_period : std_logic_vector(g_width-1 downto 0);
signal visible_blink_length : std_logic_vector(g_width-1 downto 0); signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
-- will be registers of the core -- will be registers of the core
...@@ -358,7 +360,6 @@ signal pulse_delay : std_logic_vector(g_width-1 downto 0); ...@@ -358,7 +360,6 @@ signal pulse_delay : std_logic_vector(g_width-1 downto 0);
signal clock_period : std_logic_vector(g_width-1 downto 0); signal clock_period : std_logic_vector(g_width-1 downto 0);
signal gnum_reset : std_logic; signal gnum_reset : std_logic;
signal pll_cs : std_logic;
signal spec_led_green : std_logic; signal spec_led_green : std_logic;
signal spec_led_red : std_logic; signal spec_led_red : std_logic;
...@@ -419,6 +420,9 @@ signal acam_refclk : std_logic; ...@@ -419,6 +420,9 @@ signal acam_refclk : std_logic;
signal clk : std_logic; signal clk : std_logic;
signal spec_clk : std_logic; signal spec_clk : std_logic;
signal conditions_reg : unsigned(2 downto 0);
signal conditions_pulse : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
...@@ -450,7 +454,7 @@ begin ...@@ -450,7 +454,7 @@ begin
reset_i => general_reset, reset_i => general_reset,
start_nb_offset_o => start_nb_offset, start_nb_offset_o => start_nb_offset,
start_trig_o => start_trig start_trig_o => open
); );
data_formatting_block: data_formatting data_formatting_block: data_formatting
...@@ -480,8 +484,10 @@ begin ...@@ -480,8 +484,10 @@ begin
int_flag_i => int_flag_i, int_flag_i => int_flag_i,
-- this is the config for acam test, in normal application connect the outputs -- this is the config for acam test, in normal application connect the outputs
start_dis_o => start_dis_o, -- start_dis_o => start_dis_o,
start_from_fpga_o => start_from_fpga_o, -- start_from_fpga_o => start_from_fpga_o,
start_dis_o => open,
start_from_fpga_o => open,
stop_dis_o => stop_dis_o, stop_dis_o => stop_dis_o,
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
...@@ -609,61 +615,63 @@ begin ...@@ -609,61 +615,63 @@ begin
tdc_clk_o => clk tdc_clk_o => clk
); );
spec_led_counter: free_counter spec_led_period_counter: free_counter
port map( port map(
clk => spec_clk, clk => spec_clk,
enable => '1', enable => '1',
reset => gnum_reset, reset => gnum_reset,
start_value => spec_led_period, start_value => spec_led_period,
count_done => spec_led_count_done, count_done => spec_led_period_done,
current_value => open current_value => open
); );
tdc_led_counter: countdown_counter spec_led_blink_counter: countdown_counter
port map(
clk => spec_clk,
reset => gnum_reset,
start => spec_led_period_done,
start_value => visible_blink_length,
count_done => spec_led_blink_done,
current_value => open
);
tdc_led_blink_counter: countdown_counter
port map( port map(
clk => clk, clk => clk,
reset => general_reset, reset => general_reset,
start => one_hz_p, start => one_hz_p,
start_value => visible_blink_length, start_value => visible_blink_length,
count_done => tdc_led_count_done, count_done => tdc_led_blink_done,
current_value => open current_value => open
); );
spec_led: process spec_led: process
begin begin
if gnum_reset ='1' then if gnum_reset ='1' then
spec_led_red <= '0'; spec_led_red <= '0';
elsif spec_led_count_done ='1' then elsif spec_led_period_done ='1' then
spec_led_red <= not(spec_led_red); spec_led_red <= '1';
elsif spec_led_blink_done ='1' then
spec_led_red <= '0';
end if; end if;
wait until spec_clk ='1'; wait until spec_clk ='1';
end process; end process;
tdc_led: process tdc_led: process
begin begin
if one_hz_p ='1' then if general_reset ='1' then
tdc_led_status <= '1'; tdc_led_status <= '0';
elsif tdc_led_count_done = '1' then elsif one_hz_p ='1' then
tdc_led_status <= '0'; tdc_led_status <= '1';
elsif tdc_led_blink_done = '1' then
tdc_led_status <= '0';
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
-- two_seconds: process
-- begin
-- if gnum_reset ='1' then
-- tdc_led_trig5 <= '0';
-- elsif one_hz_p ='1' then
-- tdc_led_trig5 <= not(tdc_led_trig5);
-- end if;
-- wait until clk ='1';
-- end process;
-- tdc_led_period <= tdc_led_period_sim when values_for_simulation
-- else tdc_led_period_syn;
spec_led_period <= spec_led_period_sim when values_for_simulation spec_led_period <= spec_led_period_sim when values_for_simulation
else spec_led_period_syn; else spec_led_period_syn;
...@@ -686,7 +694,8 @@ begin ...@@ -686,7 +694,8 @@ begin
csr_dat_r <= acm_dat_r; csr_dat_r <= acm_dat_r;
-- inputs -- inputs
gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i); -- gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i);
gnum_reset <= not(rst_n_a_i);
-- outputs -- outputs
...@@ -709,19 +718,33 @@ begin ...@@ -709,19 +718,33 @@ begin
term_en_4_o <= '1'; term_en_4_o <= '1';
term_en_5_o <= '1'; term_en_5_o <= '1';
-- note: all spec_aux signals are active low
spec_aux5_o <= spec_aux0_i; spec_aux5_o <= spec_aux0_i;
spec_aux4_o <= spec_aux1_i; spec_aux4_o <= spec_aux0_i;
button_with_spec_clk: process spec_aux3_o <= spec_aux0_i;
begin
spec_aux3_o <= spec_aux0_i;
wait until spec_clk ='1';
end process;
button_with_tdc_clk: process button_with_tdc_clk: process
begin begin
spec_aux2_o <= spec_aux0_i; spec_aux2_o <= spec_aux1_i;
wait until clk ='1';
end process;
tdc_led5: process
begin
if general_reset ='1' then
tdc_led_trig5 <= '0';
elsif tdc_in_fpga_5_i ='1' or spec_aux0_i ='0' then
tdc_led_trig5 <= '1';
elsif spec_aux1_i = '0' then
tdc_led_trig5 <= '0';
end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
start_trig <= tdc_in_fpga_5_i;
start_from_fpga_o <= tdc_in_fpga_5_i;
start_dis_o <= '0';
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
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