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FMC TDC 1ns 5cha - Gateware
Commit e0addd9d authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use… 

hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use standard WR dac interface instead
parent 1e074bd0
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Showing with 364 additions and 328 deletions
hdl/rtl/clks_rsts_manager.vhd
View file @ e0addd9d
......@@ -87,7 +87,8 @@ use UNISIM.vcomponents.all;
entity clks_rsts_manager is
generic
(nb_of_reg : integer := 68);
(nb_of_reg : integer := 68;
g_simulation : boolean := false);
port
-- INPUTS
-- Clock signal from carrier board
......@@ -172,9 +173,9 @@ architecture rtl of clks_rsts_manager is
signal rst_cnt : unsigned(7 downto 0) := "00000000";
-- SCLK generation
signal sclk : std_logic;
signal sclk_r_edge, sclk_f_edge, sclk_d1, sclk_d2: std_logic;
signal divider : unsigned(7 downto 0) := "00000000";
signal sclk_r_edge, sclk_f_edge, sclk_d1, sclk_d2 : std_logic;
signal divider : unsigned(4 downto 0) := "00000";
signal sclk_en : std_logic;
-- The PLL circuit AD9516-4 needs to be configured through 68 registers.
-- The values and addresses are obtained through the dedicated Analog Devices software & the datasheet.
constant REG_000 : t_byte := x"18";
......@@ -255,8 +256,8 @@ architecture rtl of clks_rsts_manager is
constant REG_231 : t_byte := x"00";
constant REG_232 : t_byte := x"01";
constant SIM_RST : std_logic_vector(31 downto 0):= x"00000400";
constant SYN_RST : std_logic_vector(31 downto 0):= x"00004E20";
constant SIM_RST : std_logic_vector(31 downto 0) := x"00000400";
constant SYN_RST : std_logic_vector(31 downto 0) := x"00004E20";
-- this value may still need adjustment according to the dispersion
-- in the performance of the PLL observed during the production tests
......@@ -280,7 +281,7 @@ begin
port map
(O => tdc_clk_buf, -- Buffer output
I => tdc_125m_clk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => tdc_125m_clk_n_i);-- Diff_n buffer input (connect directly to top-level port)
IB => tdc_125m_clk_n_i); -- Diff_n buffer input (connect directly to top-level port)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc_clk125_gbuf : BUFG
......@@ -303,7 +304,7 @@ begin
-- Synchronous process rst_n_i_synchronizer: Synchronization of the input reset signal rst_n_i,
-- coming from the GN4124/VME interface or a PoR, to the clk_sys_i, using a set of 2 registers.
-- Note that the removal of the reset signal is synchronised.
PoR_synchronizer: process (clk_sys_i)
PoR_synchronizer : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
rst_in_synch <= rst_in_synch(0) & not rst_n_i;
......@@ -313,7 +314,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process pll_status_synchronizer: Synchronization of the pll_status_i input to the
-- clk_sys_i, using a set of 2 registers.
pll_status_synchronizer: process (clk_sys_i)
pll_status_synchronizer : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
......@@ -333,7 +334,7 @@ begin
-- is released. Note that the level of the pll_status signal rather than its rising edge is used,
-- as in the case of a GN4124/VME reset during operation the PLL will remain locked, therefore no
-- rising edge would be detected.
rst_generation: process (clk_sys_i)
rst_generation : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
......@@ -357,7 +358,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process internal_rst_synchronizer: Synchronization of the above generated rst signal
-- to the 125MHz tdc_clk, using a set of 2 registers.
Internal_rst_synchronizer: process (tdc_clk)
Internal_rst_synchronizer : process (tdc_clk)
begin
if rising_edge (tdc_clk) then
internal_rst_synch <= internal_rst_synch(0) & rst;
......@@ -380,10 +381,10 @@ begin
port map
(O => acam_refclk,
I => acam_refclk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => acam_refclk_n_i);-- Diff_n buffer input (connect directly to top-level port)
IB => acam_refclk_n_i); -- Diff_n buffer input (connect directly to top-level port)
---------------------------------------------------------------------------------------------------
acam_refclk_synchronizer: process (tdc_clk)
acam_refclk_synchronizer : process (tdc_clk)
begin
if rising_edge (tdc_clk) then
if internal_rst_synch(1) = '1' then
......@@ -403,7 +404,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process send_dac_word_p_synchronizer: Synchronization of the send_dac_word_p_o
-- input to the clk_sys_i, using a set of 3 registers.
send_dac_word_p_synchronizer: process (clk_sys_i)
send_dac_word_p_synchronizer : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
......@@ -420,7 +421,7 @@ begin
-- Synchronous process dac_word_reg: selection of the word to be sent to the DAC.
-- Upon initialization the default word is being sent; otherwise the word received through the VME
-- interface on the DAC_WORD register.
dac_word_reg: process (clk_sys_i)
dac_word_reg : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
......@@ -445,13 +446,17 @@ begin
-- after a GN4124/VME command for the reconfiguration of the DAC (send_dac_word_p_i) or
-- after a White Rabbit command for the reconfiguration of the DAC(wrabbit_dac_wr_p_i)
---------------------------------------------------------------------------------------------------
pll_dac_initialization_seq: process (clk_sys_i)
pll_dac_initialization_seq : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' or send_dac_word_r_edge_p = '1' then
if rst_in_synch(1) = '1' then
if g_simulation then
config_st <= done;
else
config_st <= config_start;
end if;
dac_only <= '0';
elsif wrabbit_dac_wr_p_i = '1' then
elsif wrabbit_dac_wr_p_i = '1' or send_dac_word_r_edge_p = '1' then
config_st <= config_start;
dac_only <= '1';
else
......@@ -461,7 +466,7 @@ begin
end process;
---------------------------------------------------------------------------------------------------
pll_dac_initialization_comb: process (config_st, dac_bit_index, pll_byte_index, pll_bit_index, sclk,
pll_dac_initialization_comb : process (config_st, dac_bit_index, pll_byte_index, pll_bit_index, sclk,
sclk_r_edge, sclk_f_edge, dac_only)
begin
case config_st is
......@@ -471,6 +476,7 @@ begin
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
sclk_en <= '1';
-----------------------------------
if sclk_r_edge = '1' then
nxt_config_st <= sending_dac_word;
......@@ -537,6 +543,7 @@ begin
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
sclk_en <= '0';
-----------------------------------
nxt_config_st <= done;
......@@ -552,19 +559,19 @@ begin
end process;
---------------------------------------------------------------------------------------------------
pll_sclk_generator: process (clk_sys_i) -- transitions take place on the falling edge of sclk
pll_sclk_generator : process (clk_sys_i) -- transitions take place on the falling edge of sclk
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
if rst_in_synch(1) = '1' and sclk_en = '1' then
sclk <= '0';
sclk_d1 <= '0';
sclk_d2 <= '0';
else
sclk_d1 <= sclk;
sclk_d2 <= sclk_d1;
if divider(2) = '1' then
if divider = 0 then
sclk <= '0';
else
elsif divider = 15 then
sclk <= '1';
end if;
end if;
......@@ -588,7 +595,7 @@ begin
end process;
---------------------------------------------------------------------------------------------------
pll_index_control: process (clk_sys_i) -- counting of bits that are sent on the rising edges
pll_index_control : process (clk_sys_i) -- counting of bits that are sent on the rising edges
begin
if rising_edge (clk_sys_i) then
......@@ -624,7 +631,7 @@ begin
else x"00" & config_reg(pll_byte_index);
---------------------------------------------------------------------------------------------------
dac_index_control: process (clk_sys_i)
dac_index_control : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then -- counting of bits that are sent on the falling edges
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ e0addd9d
......@@ -292,6 +292,10 @@ architecture rtl of fmc_tdc_wrapper is
(c_slave_direct => x"00008000",
c_slave_regs => x"00008000");
signal wr_dac_din, wr_dac_sclk, wr_dac_sync_n : std_logic;
signal pll_cs : std_logic;
begin
......@@ -331,15 +335,16 @@ begin
end generate gen_with_direct_readout;
gen_without_direct_readout: if not g_with_direct_readout generate
gen_without_direct_readout : if not g_with_direct_readout generate
cnx_master_out(c_slave_regs) <= slave_i;
slave_o <= cnx_master_in(c_slave_regs);
end generate gen_without_direct_readout;
cmp_tdc_clks_rsts_mgment : clks_rsts_manager
cmp_tdc_clks_rsts_mgment : entity work.clks_rsts_manager
generic map
(nb_of_reg => 68)
(nb_of_reg => 68,
g_simulation => g_simulation)
port map
(clk_sys_i => clk_sys_i,
acam_refclk_p_i => acam_refclk_p_i,
......@@ -349,23 +354,47 @@ begin
rst_n_i => rst_n_a_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
send_dac_word_p_i => send_dac_word_p,
dac_word_i => dac_word,
send_dac_word_p_i => '0',
dac_word_i => x"000000",
acam_refclk_r_edge_p_o => acam_refclk_r_edge_p,
wrabbit_dac_value_i => tm_dac_value_i,
wrabbit_dac_wr_p_i => tm_dac_wr_i,
wrabbit_dac_value_i => x"000000",
wrabbit_dac_wr_p_i => '0',
internal_rst_o => rst_125m_mezz,
pll_cs_n_o => pll_cs_o,
pll_cs_n_o => pll_cs,
pll_dac_sync_n_o => pll_dac_sync,
pll_sdi_o => pll_sdi,
pll_sclk_o => pll_sclk,
tdc_125m_clk_o => clk_125m_mezz,
pll_status_o => open);
U_WR_DAC : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
value_i => tm_dac_value_i(15 downto 0),
cs_sel_i => "1",
load_i => tm_dac_wr_i,
sclk_divsel_i => "010",
dac_cs_n_o(0) => wr_dac_sync_n,
dac_sclk_o => wr_dac_sclk,
dac_sdata_o => wr_dac_din);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_125m_mezz_n <= not rst_125m_mezz;
pll_dac_sync_o <= pll_dac_sync;
pll_sdi_o <= pll_sdi;
pll_sclk_o <= pll_sclk;
pll_dac_sync_o <= wr_dac_sync_n;
pll_sdi_o <= pll_sdi when pll_cs = '0' else wr_dac_din;
pll_sclk_o <= pll_sclk when pll_cs = '0' else wr_dac_sclk;
pll_cs_o <= pll_cs;
clk_125m_tdc_o <= clk_125m_mezz;
---------------------------------------------------------------------------------------------------
......@@ -458,12 +487,12 @@ begin
sim_timestamp_i => sim_timestamp_i);
mezz_scl_o <= '0' when tdc_scl_out ='0' and tdc_scl_oen = '0' else '1';
mezz_sda_o <= '0' when tdc_sda_out ='0' and tdc_sda_oen = '0' else '1';
mezz_scl_o <= '0' when tdc_scl_out = '0' and tdc_scl_oen = '0' else '1';
mezz_sda_o <= '0' when tdc_sda_out = '0' and tdc_sda_oen = '0' else '1';
end rtl;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
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