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FMC TDC 1ns 5cha - Gateware
Commit f33ef0bc authored by penacoba's avatar penacoba
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New versions of the core from Coregen to instantiate the RAM block for the Circular Buffer 


git-svn-id: http://svn.ohwr.org/fmc-tdc@57 85dfdc96-de2c-444c-878d-45b388be74a9
parent 07d08c43
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hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise 0 → 100644
View file @ f33ef0bc
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hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc 0 → 100644
View file @ f33ef0bc
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\ No newline at end of file
hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd 0 → 100644
View file @ f33ef0bc
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-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_circ_buff_v6_4.vhd when simulating
-- the core, blk_mem_circ_buff_v6_4. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_circ_buff_v6_4 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END blk_mem_circ_buff_v6_4;
ARCHITECTURE blk_mem_circ_buff_v6_4_a OF blk_mem_circ_buff_v6_4 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_circ_buff_v6_4
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_circ_buff_v6_4 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 1,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 1,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 256,
c_read_depth_b => 1024,
c_read_width_a => 128,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 256,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 128,
c_write_width_b => 32,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_circ_buff_v6_4
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
enb => enb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END blk_mem_circ_buff_v6_4_a;
hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vho 0 → 100644
View file @ f33ef0bc
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 --
-- --
-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port --
-- Block Memory and Single Port Block Memory LogiCOREs, but is not a --
-- direct drop-in replacement. It should be used in all new Xilinx --
-- designs. The core supports RAM and ROM functions over a wide range of --
-- widths and depths. Use this core to generate block memories with --
-- symmetric or asymmetric read and write port widths, as well as cores --
-- which can perform simultaneous write operations to separate --
-- locations, and simultaneous read operations from the same location. --
-- For more information on differences in interface and feature support --
-- between this core and the Dual Port Block Memory and Single Port --
-- Block Memory LogiCOREs, please consult the data sheet. --
--------------------------------------------------------------------------------
-- Interfaces:
-- AXI_SLAVE_S_AXI
-- AXILite_SLAVE_S_AXI
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT blk_mem_circ_buff_v6_4
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : blk_mem_circ_buff_v6_4
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
enb => enb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file blk_mem_circ_buff_v6_4.vhd when simulating
-- the core, blk_mem_circ_buff_v6_4. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xco 0 → 100644
View file @ f33ef0bc
##############################################################
#
# Xilinx Core Generator version 13.3
# Date: Thu Nov 3 16:19:30 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatParenNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Synplicity
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=blk_mem_circ_buff_v6_4
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=128
CSET read_width_b=32
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=true
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=256
CSET write_width_a=128
CSET write_width_b=32
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
# END Extra information
GENERATE
# CRC: e87268cc
hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise 0 → 100644
View file @ f33ef0bc
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
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<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="blk_mem_circ_buff_v6_4.ngc" xil_pn:type="FILE_NGC">
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<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
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<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
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<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
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<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
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<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
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<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="blk_mem_circ_buff_v6_4" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
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<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="blk_mem_circ_buff_v6_4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-11-03T17:20:47" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C04346DDB7D4C8A3736523503E81A9A6" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4_flist.txt 0 → 100644
View file @ f33ef0bc
# Output products list for <blk_mem_circ_buff_v6_4>
blk_mem_circ_buff_v6_4.gise
blk_mem_circ_buff_v6_4.ngc
blk_mem_circ_buff_v6_4.vhd
blk_mem_circ_buff_v6_4.vho
blk_mem_circ_buff_v6_4.xco
blk_mem_circ_buff_v6_4.xise
blk_mem_circ_buff_v6_4_flist.txt
blk_mem_circ_buff_v6_4_ste/example_design/blk_mem_circ_buff_v6_4_top.ucf
blk_mem_circ_buff_v6_4_ste/example_design/blk_mem_circ_buff_v6_4_top.vhd
blk_mem_circ_buff_v6_4_ste/example_design/blk_mem_circ_buff_v6_4_top.xdc
blk_mem_circ_buff_v6_4_ste/example_design/bmg_wrapper.vhd
blk_mem_circ_buff_v6_4_ste/implement/implement.bat
blk_mem_circ_buff_v6_4_ste/implement/implement.sh
blk_mem_circ_buff_v6_4_ste/implement/planAhead_rdn.bat
blk_mem_circ_buff_v6_4_ste/implement/planAhead_rdn.sh
blk_mem_circ_buff_v6_4_ste/implement/planAhead_rdn.tcl
blk_mem_circ_buff_v6_4_ste/implement/synplify.prj
blk_mem_circ_buff_v6_4_ste/implement/xst.prj
blk_mem_circ_buff_v6_4_ste/implement/xst.scr
blk_mem_circ_buff_v6_4_xmdf.tcl
blk_mem_gen_ds512.pdf
blk_mem_gen_v6_2_readme.txt
summary.log
hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4_xmdf.tcl 0 → 100644
View file @ f33ef0bc
# The package naming convention is <core_name>_xmdf
package provide blk_mem_circ_buff_v6_4_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::blk_mem_circ_buff_v6_4_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::blk_mem_circ_buff_v6_4_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name blk_mem_circ_buff_v6_4
}
# ::blk_mem_circ_buff_v6_4_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::blk_mem_circ_buff_v6_4_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/example_design/blk_mem_circ_buff_v6_4_top.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/example_design/blk_mem_circ_buff_v6_4_top.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/example_design/blk_mem_circ_buff_v6_4_top.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/example_design/bmg_wrapper.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/implement/planAhead_rdn.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/implement/planAhead_rdn.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/implement/planAhead_rdn.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/implement/synplify.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_ste/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_circ_buff_v6_4_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blk_mem_circ_buff_v6_4
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2_readme.txt 0 → 100644
View file @ f33ef0bc
Core name: Xilinx LogiCORE Block Memory Generator
Version: 6.2
Release Date: June 22, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v6.2
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
2. NEW FEATURES
- ISE 13.2 software support
- Virtex-7L, Kintex-7L, Artix-7* and Zynq-7000* device support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Zynq-7000*
Virtex-7
Virtex-7 XT (7vx485t)
Virtex-7 -2L
Kintex-7
Kintex-7 -2L
Artix-7*
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XQ LXT/SXT
Spartan-6 XC LX/LXT
Spartan-6 XA
Spartan-6 XQ LX/LXT
Spartan-6 -1L XQ LX
Virtex-5 XC LX/LXT/SXT/TXT/FXT
Virtex-5 XQ LX/ LXT/SXT/FXT
Virtex-4 XC LX/SX/FX
Virtex-4 XQ LX/SX/FX
Virtex-4 XQR LX/SX/FX
Spartan-3 XC
Spartan-3 XA
Spartan-3A XC 3A / 3A DSP / 3AN DSP
Spartan-3A XA 3A / 3A DSP
Spartan-3E XC
Spartan-3E XA
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v6.2:
1. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
Version Fixed: v6.2
- CR 587481
- AR 39718
5. KNOWN ISSUES
The following are known issues for v6.2 of this core at time of release:
1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
Work around: The user must review the possible scenarios that causes the collission and revise
their design to avoid those situations.
- CR588505
Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
Write Mode = Read First in conjunction with asynchronous clocking
2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
3. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.gise 0 → 100644
View file @ f33ef0bc
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="blk_mem_gen_v6_3.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_3.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.ngc 0 → 100644
View file @ f33ef0bc
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.vhd 0 → 100644
View file @ f33ef0bc
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-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v6_3.vhd when simulating
-- the core, blk_mem_gen_v6_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v6_3 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END blk_mem_gen_v6_3;
ARCHITECTURE blk_mem_gen_v6_3_a OF blk_mem_gen_v6_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v6_3
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v6_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_1(behavioral)
GENERIC MAP (
c_addra_width => 7,
c_addrb_width => 9,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 1,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 1,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 128,
c_read_depth_b => 512,
c_read_width_a => 128,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 128,
c_write_depth_b => 512,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 128,
c_write_width_b => 32,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v6_3
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
enb => enb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END blk_mem_gen_v6_3_a;
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.vho 0 → 100644
View file @ f33ef0bc
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.
-- Interfaces:
-- AXI4_SLAVE_S_AXI
-- AXILite_SLAVE_S_AXI
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT blk_mem_gen_v6_3
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : blk_mem_gen_v6_3
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
enb => enb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file blk_mem_gen_v6_3.vhd when simulating
-- the core, blk_mem_gen_v6_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.xco 0 → 100644
View file @ f33ef0bc
##############################################################
#
# Xilinx Core Generator version 13.1
# Date: Fri Oct 7 15:49:14 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatParenNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Synplicity
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=blk_mem_gen_v6_3
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=128
CSET read_width_b=32
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=true
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=128
CSET write_width_a=128
CSET write_width_b=32
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-02-03T22:20:43.000Z
# END Extra information
GENERATE
# CRC: d3d95de2
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.xise 0 → 100644
View file @ f33ef0bc
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<!-- project source files, project and process properties. This file, -->
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<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
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<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
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<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="blk_mem_gen_v6_3" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
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<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="blk_mem_gen_v6_3" xil_pn:valueState="non-default"/>
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<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
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</project>
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3_flist.txt 0 → 100644
View file @ f33ef0bc
# Output products list for <blk_mem_gen_v6_3>
blk_mem_gen_ds512.pdf
blk_mem_gen_readme.txt
blk_mem_gen_v6_3.gise
blk_mem_gen_v6_3.ngc
blk_mem_gen_v6_3.vhd
blk_mem_gen_v6_3.vho
blk_mem_gen_v6_3.xco
blk_mem_gen_v6_3.xise
blk_mem_gen_v6_3_flist.txt
blk_mem_gen_v6_3_xmdf.tcl
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3_xmdf.tcl 0 → 100644
View file @ f33ef0bc
# The package naming convention is <core_name>_xmdf
package provide blk_mem_gen_v6_3_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::blk_mem_gen_v6_3_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::blk_mem_gen_v6_3_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name blk_mem_gen_v6_3
}
# ::blk_mem_gen_v6_3_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::blk_mem_gen_v6_3_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_3.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_3.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_3.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_3.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_3_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blk_mem_gen_v6_3
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
hdl/spec/src/ip_cores/mem_core/circular_buffer_coregen.cgc
View file @ f33ef0bc
......@@ -70,38 +70,38 @@
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<xilinx:designEntry>VHDL</xilinx:designEntry>
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<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
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<xilinx:device>xc6slx45t</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>fgg484</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
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<xilinx:flowOptions>
<xilinx:busFormat>BusFormatParenNotRipped</xilinx:busFormat>
<xilinx:designEntry>VHDL</xilinx:designEntry>
<xilinx:asySymbol>false</xilinx:asySymbol>
<xilinx:flowVendor>Synplicity</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
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<xilinx:packageInfo>
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<spirit:componentInstance>
......@@ -166,9 +166,405 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_COLLISION_WARNINGS">false</spirit:configurableElementValue>
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<xilinx:device>xc6slx45t</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>fgg484</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
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<xilinx:busFormat>BusFormatParenNotRipped</xilinx:busFormat>
<xilinx:designEntry>VHDL</xilinx:designEntry>
<xilinx:asySymbol>false</xilinx:asySymbol>
<xilinx:flowVendor>Synplicity</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
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<spirit:componentInstance>
<spirit:instanceName>blk_mem_gen_v6_3</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="6.1" />
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Full</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_SLAVE_TYPE">Memory_Slave</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_AXI_ID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEMORY_TYPE">True_Dual_Port_RAM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSUME_SYNCHRONOUS_CLK">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_A">128</spirit:configurableElementValue>
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<xilinx:generationId>generationid_624131249</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
......@@ -372,13 +881,13 @@
<xilinx:fileSet>
<xilinx:name>flist_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./blk_mem_gen_v6_2_flist.txt</xilinx:name>
<xilinx:name>./blk_mem_circ_buff_v6_4_flist.txt</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>txtFlist</xilinx:userFileType>
<xilinx:userFileType>txt</xilinx:userFileType>
<xilinx:timeStamp>Thu Oct 06 09:34:20 GMT 2011</xilinx:timeStamp>
<xilinx:checkSum>0x33999267</xilinx:checkSum>
<xilinx:generationId>generationid_3716216570</xilinx:generationId>
<xilinx:timeStamp>Thu Nov 03 16:20:50 GMT 2011</xilinx:timeStamp>
<xilinx:checkSum>0x4658C6E8</xilinx:checkSum>
<xilinx:generationId>generationid_624131249</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
......@@ -390,34 +899,35 @@
</spirit:componentInstances>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>circular_buffer_coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc6slx45t</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>fgg484</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatParenNotRipped</xilinx:busFormat>
<xilinx:designEntry>VHDL</xilinx:designEntry>
<xilinx:asySymbol>false</xilinx:asySymbol>
<xilinx:flowVendor>Synplicity</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>circular_buffer_coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc6slx45t</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>fgg484</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatParenNotRipped</xilinx:busFormat>
<xilinx:designEntry>VHDL</xilinx:designEntry>
<xilinx:asySymbol>false</xilinx:asySymbol>
<xilinx:flowVendor>Synplicity</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:design>
hdl/spec/src/ip_cores/mem_core/coregen.log
View file @ f33ef0bc
The IP Catalog has been reloaded.
Welcome to Xilinx CORE Generator.
Help system initialized.
The IP Catalog has been reloaded.
CoreGen has not been configured with any user repositories.
CoreGen has been configured with the following Xilinx repositories:
- '/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/coregen/'
[xil_index.xml]
- '/afs/cern.ch/project/parc/elec/xilinx/xilinx133/ISE_DS/ISE/coregen/' [using
existing xil_index.xml]
The IP Catalog has been reloaded.
Opening project file
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/circu
lar_buffer_coregen.cgp.
Customize and GenerateINFO:sim:927 - Generating component instance 'blk_mem_gen_v6_1' of
'xilinx.com:ip:blk_mem_gen:6.1' from
'/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/coregen/ip/xilinx/primar
y/com/xilinx/ip/blk_mem_gen_v6_1/component.xml'.
Executing Tcl generator...
Finished executing Tcl generator.
Executing Tcl generator...
INFO:sim - Resolving generics for 'blk_mem_gen_v6_2'...
INFO:sim - Applying external generics to 'blk_mem_gen_v6_2'...
Finished executing Tcl generator.
Executing Tcl generator...
INFO:sim - Delivering associated files for 'blk_mem_gen_v6_2'...
Finished executing Tcl generator.
Executing Tcl generator...
INFO:sim - Delivering EJava files for 'blk_mem_gen_v6_2'...
Finished executing Tcl generator.
Executing Tcl generator...
INFO:sim - Generating implementation netlist for 'blk_mem_gen_v6_2'...
INFO:sim - Pre-processing HDL files for 'blk_mem_gen_v6_2'...
Finished executing Tcl generator.
Executing Tcl generator...
Finished executing Tcl generator.
Executing Tcl generator...
Finished executing Tcl generator.
Executing Tcl generator...
INFO:sim - Writing VHO instantiation template for 'blk_mem_gen_v6_2'...
Finished executing Tcl generator.
Executing Tcl generator...
INFO:sim - Writing VHDL behavioral simulation model for 'blk_mem_gen_v6_2'...
Finished executing Tcl generator.
WARNING:sim - The project IP instance 'blk_mem_gen_v6_1' for IP 'Block Memory
Generator v6.1' was generated with a different version of the IP than is
currently in the IP Catalog. It was originally generated using IP with the
packaged timestamp '2011-02-03T22:20:43.000Z'; the IP in the current catalog
has a different packaged timestamp '2011-10-05T00:23:53.000Z'. This mismatch
is due to changes made to the IP in the user repositories. It may affect some
functionality of the IP, if there are differences between these two versions
of the IP.
WARNING:sim - The project IP instance 'blk_mem_gen_v6_2' for IP 'Block Memory
Generator v6.1' was generated with a different version of the IP than is
currently in the IP Catalog. It was originally generated using IP with the
packaged timestamp '2011-02-03T22:20:43.000Z'; the IP in the current catalog
has a different packaged timestamp '2011-10-05T00:23:53.000Z'. This mismatch
is due to changes made to the IP in the user repositories. It may affect some
functionality of the IP, if there are differences between these two versions
of the IP.
WARNING:sim - The project IP instance 'blk_mem_gen_v6_3' for IP 'Block Memory
Generator v6.1' was generated with a different version of the IP than is
currently in the IP Catalog. It was originally generated using IP with the
packaged timestamp '2011-02-03T22:20:43.000Z'; the IP in the current catalog
has a different packaged timestamp '2011-10-05T00:23:53.000Z'. This mismatch
is due to changes made to the IP in the user repositories. It may affect some
functionality of the IP, if there are differences between these two versions
of the IP.
WARNING:sim - The project IP instance 'reg_mem_gen_v6_1' for IP 'Block Memory
Generator v6.1' was generated with a different version of the IP than is
currently in the IP Catalog. It was originally generated using IP with the
packaged timestamp '2011-02-03T22:20:43.000Z'; the IP in the current catalog
has a different packaged timestamp '2011-10-05T00:23:53.000Z'. This mismatch
is due to changes made to the IP in the user repositories. It may affect some
functionality of the IP, if there are differences between these two versions
of the IP.
WARNING:sim - The project IP instance 'reg_mem_gen_v6_2' for IP 'Block Memory
Generator v6.1' was generated with a different version of the IP than is
currently in the IP Catalog. It was originally generated using IP with the
packaged timestamp '2011-02-03T22:20:43.000Z'; the IP in the current catalog
has a different packaged timestamp '2011-10-05T00:23:53.000Z'. This mismatch
is due to changes made to the IP in the user repositories. It may affect some
functionality of the IP, if there are differences between these two versions
of the IP.
Customize and GenerateINFO:sim - Generating component instance 'blk_mem_gen_v6_2' of
'xilinx.com:ip:blk_mem_gen:6.2' from
'/afs/cern.ch/project/parc/elec/xilinx/xilinx133/ISE_DS/ISE/coregen/./ip/xili
nx/primary/com/xilinx/ip/blk_mem_gen_v6_2/component.xml'.
Applying current project options...
Finished applying current project options.
Resolving generics for 'blk_mem_circ_buff_v6_4'...
Applying external generics to 'blk_mem_circ_buff_v6_4'...
Delivering associated files for 'blk_mem_circ_buff_v6_4'...
Delivering EJava files for 'blk_mem_circ_buff_v6_4'...
Generating implementation netlist for 'blk_mem_circ_buff_v6_4'...
INFO:sim - Pre-processing HDL files for 'blk_mem_circ_buff_v6_4'...
Running synthesis for 'blk_mem_circ_buff_v6_4'
Running ngcbuild...
Writing VHO instantiation template for 'blk_mem_circ_buff_v6_4'...
Writing VHDL behavioral simulation model for 'blk_mem_circ_buff_v6_4'...
INFO:sim - Finished generation of ASY schematic symbol.
Generating metadata file...
Finished generating metadata file.
Generating ISE project...
Finished generating ISE project.Generating README file...
Finished generating README file.
Generating README file...
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
INFO:sim - Finished FLIST file generation.
Launching README viewer...
Launched README viewer.
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'circular_buffer_coregen'.
Saved CGP file for project 'circular_buffer_coregen'.
Closed project file.
hdl/spec/src/ip_cores/mem_core/summary.log 0 → 100644
View file @ f33ef0bc
User Configuration
-------------------------------------
Algorithm : Minimum_Area
Memory Type : True_Dual_Port_RAM
Port A Read Width : 128
Port B Read Width : 32
Port A Write Width : 128
Port B Write Width : 32
Memory Depth : 256
--------------------------------------------------------------
Block RAM resource(s) (9K BRAMs) : 0
Block RAM resource(s) (18K BRAMs) : 4
--------------------------------------------------------------
Clock A Frequency : 100
Port A Enable Rate : 100
Port A Write Rate : 50
----------------------------------------------------------
Estimated Power for IP : 11.020496 mW
----------------------------------------------------------
hdl/spec/src/ip_cores/mem_core/tmp/_xmsgs/pn_parser.xmsgs
View file @ f33ef0bc
......@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/blk_mem_gen_v6_2.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/blk_mem_circ_buff_v6_4.vhd&quot; into library work</arg>
</msg>
</messages>
......
hdl/spec/src/ip_cores/mem_core/tmp/_xmsgs/xst.xmsgs
View file @ f33ef0bc
......@@ -32,82 +32,82 @@
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">27</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">5</arg>
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_input_block.vhd" Line 496: Range is empty (null range)
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_input_block.vhd" Line 529: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_prim_wrapper_s6.vhd" Line 2001: Range is empty (null range)
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_prim_wrapper_s6.vhd" Line 2001: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="220" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_prim_wrapper_s6.vhd" Line 2001: Assignment ignored
<msg type="warning" file="HDLCompiler" num="220" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_prim_wrapper_s6.vhd" Line 2001: Assignment ignored
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_prim_width.vhd" Line 428: Net &lt;<arg fmt="%s" index="1">dina_pad[35]</arg>&gt; does not have a driver.
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_prim_width.vhd" Line 429: Net &lt;<arg fmt="%s" index="1">dina_pad[35]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_prim_width.vhd" Line 432: Net &lt;<arg fmt="%s" index="1">dinb_pad[8]</arg>&gt; does not have a driver.
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_prim_width.vhd" Line 433: Net &lt;<arg fmt="%s" index="1">dinb_pad[8]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd" Line 1542: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" Line 1544: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd" Line 1555: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" Line 1557: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdata</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdata</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_awready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_awready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_wready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_wready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_arready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_arready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rlast</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rlast</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2.vhd</arg>&quot; line <arg fmt="%s" index="2">146</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_circ_buff_v6_4.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWID&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
......@@ -176,13 +176,13 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="2935" delta="old" >Signal &apos;<arg fmt="%s" index="1">S_AXI_BID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_1_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">S_AXI_BID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_2_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="2935" delta="old" >Signal &apos;<arg fmt="%s" index="1">S_AXI_RID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_1_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">S_AXI_RID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_2_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDATA</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
......@@ -221,18 +221,12 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
......@@ -254,7 +248,7 @@
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WEA&lt;14:1&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RSTB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;3:1&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
......@@ -266,28 +260,28 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1340</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1340</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1340</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1340</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1340</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1340</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1340</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_1/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1340</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
......@@ -362,7 +356,7 @@
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RDADDRECC_I&lt;8:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RDADDRECC_I&lt;9:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CLKB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
......
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