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FMC TDC 1ns 5cha - Gateware
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FMC TDC 1ns 5cha - Gateware
Commits
f55986af
Commit
f55986af
authored
Oct 02, 2019
by
Evangelia Gousiou
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Plain Diff
ise changes to meet timing closure
parent
136154cf
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2 changed files
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794 additions
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758 deletions
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-758
syn_extra_steps.tcl
hdl/syn/spec/syn_extra_steps.tcl
+35
-0
wr_spec_tdc.xise
hdl/syn/spec/wr_spec_tdc.xise
+759
-758
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hdl/syn/spec/syn_extra_steps.tcl
0 → 100644
View file @
f55986af
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
if
{
!
[
file
exists
$project
_file
]}
{
report ERROR
"Missing file
$project
_file, exiting."
exit -1
}
xilinx::project open
$project
_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set
"Enable Multi-Threading"
"off"
xilinx::project set
"Enable Multi-Threading"
"off"
-process
"Place & Route"
xilinx::project set
"Pack I/O Registers into IOBs"
"Yes"
xilinx::project set
"Pack I/O Registers/Latches into IOBs"
"For Inputs and Outputs"
xilinx::project set
"Register Duplication Map"
"Off"
xilinx::project set
"Register Balancing"
"Yes"
xilinx::project set
"Placer Effort Level Map"
"High"
xilinx::project set
"Placer Extra Effort Map"
"Continue on Impossible"
xilinx::project set
"Extra Effort (Highest PAR level only)"
"Continue on Impossible"
xilinx::project save
xilinx::project close
hdl/syn/spec/wr_spec_tdc.xise
View file @
f55986af
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