rtl: store debug metadata in upper 20 bits of frac field, added raw readout mode for debugging

fc5df2b2 · Tomasz Wlostowski · bb0af513 · fc5df2b2 · fc5df2b2
Commit fc5df2b2 authored Sep 11, 2018 by Tomasz Wlostowski
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Showing with 41 additions and 15 deletions

tdc_dma_channel.vhd hdl/rtl/tdc_dma_channel.vhd +36 -15

tdc_dma_engine.vhd hdl/rtl/tdc_dma_engine.vhd +5 -0

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--- a/hdl/rtl/tdc_dma_channel.vhd
+++ b/hdl/rtl/tdc_dma_channel.vhd
@@ -9,12 +9,16 @@ use work.genram_pkg.all;
 use work.tdc_buf_wbgen2_pkg.all;

 entity tdc_dma_channel is
+  generic(
+    g_channel : integer
+    );
  port (

    clk_i   : in std_logic;
    rst_n_i : in std_logic;

    enable_i   : in std_logic;
+    raw_mode_i : in std_logic;

    ts_i       : in  t_tdc_timestamp;
    ts_valid_i : in  std_logic;
@@ -98,7 +102,6 @@ begin
      clk_sys_i => clk_i,
      slave_i   => slave_i,
      slave_o   => slave_o,
--      int_o     => int_o,
      regs_i    => regs_in,
      regs_o    => regs_out);

@@ -249,22 +252,40 @@ begin
 --  bit  2-0 chan  (mask: 0x7)

          when SER0 =>
-            fifo_in_data    <= ts.tai;
+            if raw_mode_i = '0' then
+              fifo_in_data <= ts.tai(31 downto 0);
+            else
+              fifo_in_data <= f_pack_raw_acam_timestamp (ts.raw)(31 downto 0);
+            end if;
+
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER1;
          when SER1 =>
+            if raw_mode_i = '0' then
              fifo_in_data <= ts.coarse;
+            else
+              fifo_in_data <= f_pack_raw_acam_timestamp (ts.raw)(63 downto 32);
+            end if;
+
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER2;
          when SER2 =>
-            fifo_in_data    <= x"00000" & ts.frac;
+            if raw_mode_i = '0' then
+              fifo_in_data <= ts.meta(19 downto 0) & ts.frac;
+            else
+              fifo_in_data <= f_pack_raw_acam_timestamp (ts.raw)(95 downto 64);
+            end if;
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER3;
          when SER3 =>
+            if raw_mode_i = '0' then
              fifo_in_data <= ts.seq(27 downto 0) & ts.slope & ts.channel(2 downto 0);
+            else
+              fifo_in_data <= f_pack_raw_acam_timestamp (ts.raw)(127 downto 96);
+            end if;
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= WAIT_NEXT_TS;

--- a/hdl/rtl/tdc_dma_engine.vhd
+++ b/hdl/rtl/tdc_dma_engine.vhd
@@ -17,6 +17,7 @@ entity tdc_dma_engine is
    rst_n_i   : in std_logic;

    enable_i : in std_logic_vector(4 downto 0);
+    raw_mode_i : in std_logic_vector(4 downto 0);
    
    ts_i       : in  t_tdc_timestamp_array(4 downto 0);
    ts_valid_i : in  std_logic_vector(4 downto 0);
@@ -113,10 +114,14 @@ begin
  gen_channels : for i in 0 to 4 generate

    U_DMA_Channel : entity work.tdc_dma_channel
+      generic map(
+        g_channel => i
+        )
      port map (
        clk_i      => clk_i,
        rst_n_i    => rst_n_i,
        enable_i => enable_i(i),
+        raw_mode_i => raw_mode_i(i),
        ts_i       => ts_i(i),
        ts_valid_i => ts_valid_i(i),
        ts_ready_o => ts_ready_o(i),