Commit fea36da1 authored by penacoba's avatar penacoba

Syn folder after manual cleanup to remove svn lock


git-svn-id: http://svn.ohwr.org/fmc-tdc@74 85dfdc96-de2c-444c-878d-45b388be74a9
parent a03c43a2
This diff is collapsed.
rm -r backup
rm -r coreip
rm identify.log
rm rpt_top_tdc.areasrr rpt_top_tdc_areasrr.htm
rm run_ise.tcl
rm run_options.txt scratchproject.prs
rm synplicity.ucf
rm fifo_32x512.ngc
rm fifo_64x512.ngc
rm syn_tdc.edf
rm syn_tdc.fse
rm syn_tdc.htm
rm syn_tdc.map
rm syn_tdc.ncf
rm syn_tdc_prepass.srd
rm syn_tdc.sap
rm syn_tdc.srd
rm syn_tdc.srl
rm syn_tdc.srm
rm syn_tdc.srr
rm syn_tdc.srs
rm syn_tdc.szr
rm syn_tdc.tlg
rm -r syntmp
rm -r xplace
rm syn_tdc.bld
rm syn_tdc.mrp
rm syn_tdc.ncd
rm syn_tdc.ngd
rm syn_tdc_ngdbuild.xrpt
rm syn_tdc.ngm
rm syn_tdc.ngo
rm syn_tdc.pcf
rm syn_tdc_summary.xml
rm syn_tdc_usage.xml
rm top_tdc_map.xrpt
rm top_tdc_par.xrpt
rm -r xlnx_auto_0_xdb
rm -r _xmsgs
rm netlist.lst
rm par_tdc.ncd
rm par_tdc.pad
rm par_tdc_pad.csv
rm par_tdc_pad.txt
rm par_tdc.par
rm par_tdc.ptwx
rm par_tdc.unroutes
rm par_tdc.xpi
rm par_usage_statistics.html
rm timing_report.twr
rm timing_report.twx
rm tdc.bgn
rm tdc.bit
rm tdc_bitgen.xwbt
rm tdc.drc
rm webtalk.log
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.edf 1321462749
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/blk_mem_circ_buff_v6_4.ngc 1321462688
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_64x512.ngc 1321462688
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_32x512.ngc 1321462688
OK
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Release 13.3 - par O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Wed Nov 16 18:06:18 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
err_flag_i_IBUF
p_wr_req_i(0)_IBUF
p_wr_req_i(1)_IBUF
pll_refmon_i_IBUF
pll_sdo_i_IBUF
pll_status_i_IBUF
tdc_in_fpga_5_i_IBUF
tx_error_i_IBUF
vc_rdy_i(0)_IBUF
vc_rdy_i(1)_IBUF
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>7792</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>22101</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>22101</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>20680</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>39.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>46.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>82.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>98.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>144.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>153.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>249.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>249.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>250.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>257.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>6.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>6.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>11.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>12.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>3.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>2.8688</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
#### START OF AREA REPORT #####[
Part: XC6SLX45TFGG484-3 (Xilinx)
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 4175 100 %
LATCHES 22 100 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 4197 (42.37 % Utilization)
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 3462 100 %
MUXCY 892 100 %
XORCY 873 100 %
MULT18x18/MULT18x18S 3 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 5230 (52.80 % Utilization)
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.01 % Utilization)
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 123 100 %
=================================================
Total IO PADS in the block top_tdc: 123 (1.24 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
<html><head><title></title></head><body><a name=TopSummary>
#### START OF AREA REPORT #####[<pre>
Part: XC6SLX45TFGG484-3 (Xilinx)
Click here to go to specific block report:
<a href="rpt_top_tdc_areasrr.htm#top_tdc"><h5 align="center">top_tdc</h5></a><br><a name=top_tdc>
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 4175 100 %
LATCHES 22 100 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 4197 (42.37 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 3462 100 %
MUXCY 892 100 %
XORCY 873 100 %
MULT18x18/MULT18x18S 3 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 5230 (52.80 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.01 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 123 100 %
=================================================
Total IO PADS in the block top_tdc: 123 (1.24 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
</a></body></html>
#########################
### DEFINE VARIABLES ###
#########################
set DesignName "syn_tdc"
set FamilyName "SPARTAN6"
set DeviceName "XC6SLX45T"
set PackageName "FGG484"
set SpeedGrade "-3"
set TopModule "top_tdc"
set EdifFile "syn_tdc.edf"
if {![file exists $DesignName.ise]} {
project new $DesignName.ise
project set family $FamilyName
project set device $DeviceName
project set package $PackageName
project set speed $SpeedGrade
xfile add $EdifFile
if {[file exists synplicity.ucf]} {
xfile add synplicity.ucf
}
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project close
}
file delete -force $DesignName\_xdb
project open $DesignName.ise
process run "Implement Design" -force rerun_all
project close
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/run_options.txt
#-- Written on Wed Nov 16 17:58:07 2011
#project files
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -constraint "./tdc_syn_constraints.sdc"
#implementation: "syn"
impl -add syn -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
impl -active "syn"
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/scratchproject.prs
#-- Written on Wed Nov 16 17:58:07 2011
#project files
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd"
add_file -constraint "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc"
#implementation: "syn"
impl -add /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
set_option -include_path /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.edf"
impl -active "syn"
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000F02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 02000063
rrcmd w 0:80014 000007D0
rrcmd w 0:80018 00000003
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000F02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 0200000F
rrcmd w 0:80014 000007D0
rrcmd w 0:80018 00000003
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
rrcmd w 0:80000 01F0FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000E02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 0200000F
rrcmd w 0:80014 000007D0
rrcmd w 0:80018 00000003
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
rrcmd w 0:80000 01F0FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000E02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 0200000F
rrcmd w 0:80014 000007D0
rrcmd w 0:80018 00000003
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
rrcmd w 0:80084 0000009F
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:80020
rrcmd r c:00000
rrcmd r c:00004
rrcmd r c:00008
rrcmd r c:0000C
rrcmd r c:00010
rrcmd r c:00014
rrcmd r c:00018
rrcmd r c:0001C
rrcmd r c:00020
rrcmd r c:00024
rrcmd r c:00028
rrcmd r c:0002C
rrcmd r c:00030
rrcmd r c:00034
rrcmd r c:00038
rrcmd r c:0003C
rrcmd r c:00040
rrcmd r c:00044
rrcmd r c:00048
rrcmd r c:0004C
rrcmd r c:00050
rrcmd r c:00054
rrcmd r c:00058
rrcmd r c:0005C
rrcmd r c:00060
rrcmd r c:00064
rrcmd r c:00068
rrcmd r c:0006C
rrcmd r c:00070
rrcmd r c:00074
rrcmd r c:00078
rrcmd r c:0007C
rrcmd r c:00080
rrcmd r c:00084
rrcmd r c:00088
rrcmd r c:0008C
rrcmd r c:00090
rrcmd r c:00094
rrcmd r c:00098
rrcmd r c:0009C
rrcmd r c:000A0
rrcmd r c:000A4
rrcmd r c:000A8
rrcmd r c:000AC
rrcmd r c:000B0
rrcmd r c:000B4
rrcmd r c:000B8
rrcmd r c:000BC
rrcmd r c:000C0
rrcmd r c:000C4
rrcmd r c:000C8
rrcmd r c:000CC
rrcmd r c:000D0
rrcmd r c:000D4
rrcmd r c:000D8
rrcmd r c:000DC
rrcmd r c:000E0
rrcmd r c:000E4
rrcmd r c:000E8
rrcmd r c:000EC
rrcmd r c:000F0
rrcmd r c:000F4
rrcmd r c:000F8
rrcmd r c:000FC
rrcmd r c:00100
rrcmd r c:00104
rrcmd r c:00108
rrcmd r c:0010C
rrcmd r c:00110
rrcmd r c:00114
rrcmd r c:00118
rrcmd r c:0011C
rrcmd r c:00120
rrcmd r c:00124
rrcmd r c:00128
rrcmd r c:0012C
rrcmd r c:00130
rrcmd r c:00134
rrcmd r c:00138
rrcmd r c:0013C
rrcmd r c:00140
rrcmd r c:00144
rrcmd r c:00148
rrcmd r c:0014C
rrcmd r c:00150
rrcmd r c:00154
rrcmd r c:00158
rrcmd r c:0015C
rrcmd r c:00160
rrcmd r c:00164
rrcmd r c:00168
rrcmd r c:0016C
rrcmd r c:00170
rrcmd r c:00174
rrcmd r c:00178
rrcmd r c:0017C
rrcmd r c:00180
rrcmd r c:00184
rrcmd r c:00188
rrcmd r c:0018C
rrcmd r c:00190
rrcmd r c:00194
rrcmd r c:00198
rrcmd r c:0019C
rrcmd r c:001A0
rrcmd r c:001A4
rrcmd r c:001A8
rrcmd r c:001AC
rrcmd r c:001B0
rrcmd r c:001B4
rrcmd r c:001B8
rrcmd r c:001BC
rrcmd r c:001C0
rrcmd r c:001C4
rrcmd r c:001C8
rrcmd r c:001CC
rrcmd r c:001D0
rrcmd r c:001D4
rrcmd r c:001D8
rrcmd r c:001DC
rrcmd r c:001E0
rrcmd r c:001E4
rrcmd r c:001E8
rrcmd r c:001EC
rrcmd r c:001F0
rrcmd r c:001F4
rrcmd r c:001F8
rrcmd r c:001FC
rrcmd r c:00200
rrcmd r c:00204
rrcmd r c:00208
rrcmd r c:0020C
rrcmd r c:00210
rrcmd r c:00214
rrcmd r c:00218
rrcmd r c:0021C
rrcmd r c:00220
rrcmd r c:00224
rrcmd r c:00228
rrcmd r c:0022C
rrcmd r c:00230
rrcmd r c:00234
rrcmd r c:00238
rrcmd r c:0023C
rrcmd r c:00240
rrcmd r c:00244
rrcmd r c:00248
rrcmd r c:0024C
rrcmd r c:00250
rrcmd r c:00254
rrcmd r c:00258
rrcmd r c:0025C
rrcmd r c:00260
rrcmd r c:00264
rrcmd r c:00268
rrcmd r c:0026C
rrcmd r c:00270
rrcmd r c:00274
rrcmd r c:00278
rrcmd r c:0027C
rrcmd r c:00280
rrcmd r c:00284
rrcmd r c:00288
rrcmd r c:0028C
rrcmd r c:00290
rrcmd r c:00294
rrcmd r c:00298
rrcmd r c:0029C
rrcmd r c:002A0
rrcmd r c:002A4
rrcmd r c:002A8
rrcmd r c:002AC
rrcmd r c:002B0
rrcmd r c:002B4
rrcmd r c:002B8
rrcmd r c:002BC
rrcmd r c:002C0
rrcmd r c:002C4
rrcmd r c:002C8
rrcmd r c:002CC
rrcmd r c:002D0
rrcmd r c:002D4
rrcmd r c:002D8
rrcmd r c:002DC
rrcmd r c:002E0
rrcmd r c:002E4
rrcmd r c:002E8
rrcmd r c:002EC
rrcmd r c:002F0
rrcmd r c:002F4
rrcmd r c:002F8
rrcmd r c:002FC
rrcmd r c:00300
rrcmd r c:00304
rrcmd r c:00308
rrcmd r c:0030C
rrcmd r c:00310
rrcmd r c:00314
rrcmd r c:00318
rrcmd r c:0031C
rrcmd r c:00320
rrcmd r c:00324
rrcmd r c:00328
rrcmd r c:0032C
rrcmd r c:00330
rrcmd r c:00334
rrcmd r c:00338
rrcmd r c:0033C
rrcmd r c:00340
rrcmd r c:00344
rrcmd r c:00348
rrcmd r c:0034C
rrcmd r c:00350
rrcmd r c:00354
rrcmd r c:00358
rrcmd r c:0035C
rrcmd r c:00360
rrcmd r c:00364
rrcmd r c:00368
rrcmd r c:0036C
rrcmd r c:00370
rrcmd r c:00374
rrcmd r c:00378
rrcmd r c:0037C
rrcmd r c:00380
rrcmd r c:00384
rrcmd r c:00388
rrcmd r c:0038C
rrcmd r c:00390
rrcmd r c:00394
rrcmd r c:00398
rrcmd r c:0039C
rrcmd r c:003A0
rrcmd r c:003A4
rrcmd r c:003A8
rrcmd r c:003AC
rrcmd r c:003B0
rrcmd r c:003B4
rrcmd r c:003B8
rrcmd r c:003BC
rrcmd r c:003C0
rrcmd r c:003C4
rrcmd r c:003C8
rrcmd r c:003CC
rrcmd r c:003D0
rrcmd r c:003D4
rrcmd r c:003D8
rrcmd r c:003DC
rrcmd r c:003E0
rrcmd r c:003E4
rrcmd r c:003E8
rrcmd r c:003EC
rrcmd r c:003F0
rrcmd r c:003F4
rrcmd r c:003F8
rrcmd r c:003FC
rrcmd r c:00400
rrcmd r c:00404
rrcmd r c:00408
rrcmd r c:0040C
rrcmd r c:00410
rrcmd r c:00414
rrcmd r c:00418
rrcmd r c:0041C
rrcmd r c:00420
rrcmd r c:00424
rrcmd r c:00428
rrcmd r c:0042C
rrcmd r c:00430
rrcmd r c:00434
rrcmd r c:00438
rrcmd r c:0043C
rrcmd r c:00440
rrcmd r c:00444
rrcmd r c:00448
rrcmd r c:0044C
rrcmd r c:00450
rrcmd r c:00454
rrcmd r c:00458
rrcmd r c:0045C
rrcmd r c:00460
rrcmd r c:00464
rrcmd r c:00468
rrcmd r c:0046C
rrcmd r c:00470
rrcmd r c:00474
rrcmd r c:00478
rrcmd r c:0047C
rrcmd r c:00480
rrcmd r c:00484
rrcmd r c:00488
rrcmd r c:0048C
rrcmd r c:00490
rrcmd r c:00494
rrcmd r c:00498
rrcmd r c:0049C
rrcmd r c:004A0
rrcmd r c:004A4
rrcmd r c:004A8
rrcmd r c:004AC
rrcmd r c:004B0
rrcmd r c:004B4
rrcmd r c:004B8
rrcmd r c:004BC
rrcmd r c:004C0
rrcmd r c:004C4
rrcmd r c:004C8
rrcmd r c:004CC
rrcmd r c:004D0
rrcmd r c:004D4
rrcmd r c:004D8
rrcmd r c:004DC
rrcmd r c:004E0
rrcmd r c:004E4
rrcmd r c:004E8
rrcmd r c:004EC
rrcmd r c:004F0
rrcmd r c:004F4
rrcmd r c:004F8
rrcmd r c:004FC
rrcmd r c:00500
rrcmd r c:00504
rrcmd r c:00508
rrcmd r c:0050C
rrcmd r c:00510
rrcmd r c:00514
rrcmd r c:00518
rrcmd r c:0051C
rrcmd r c:00520
rrcmd r c:00524
rrcmd r c:00528
rrcmd r c:0052C
rrcmd r c:00530
rrcmd r c:00534
rrcmd r c:00538
rrcmd r c:0053C
rrcmd r c:00540
rrcmd r c:00544
rrcmd r c:00548
rrcmd r c:0054C
rrcmd r c:00550
rrcmd r c:00554
rrcmd r c:00558
rrcmd r c:0055C
rrcmd r c:00560
rrcmd r c:00564
rrcmd r c:00568
rrcmd r c:0056C
rrcmd r c:00570
rrcmd r c:00574
rrcmd r c:00578
rrcmd r c:0057C
rrcmd r c:00580
rrcmd r c:00584
rrcmd r c:00588
rrcmd r c:0058C
rrcmd r c:00590
rrcmd r c:00594
rrcmd r c:00598
rrcmd r c:0059C
rrcmd r c:005A0
rrcmd r c:005A4
rrcmd r c:005A8
rrcmd r c:005AC
rrcmd r c:005B0
rrcmd r c:005B4
rrcmd r c:005B8
rrcmd r c:005BC
rrcmd r c:005C0
rrcmd r c:005C4
rrcmd r c:005C8
rrcmd r c:005CC
rrcmd r c:005D0
rrcmd r c:005D4
rrcmd r c:005D8
rrcmd r c:005DC
rrcmd r c:005E0
rrcmd r c:005E4
rrcmd r c:005E8
rrcmd r c:005EC
rrcmd r c:005F0
rrcmd r c:005F4
rrcmd r c:005F8
rrcmd r c:005FC
rrcmd r c:00600
rrcmd r c:00604
rrcmd r c:00608
rrcmd r c:0060C
rrcmd r c:00610
rrcmd r c:00614
rrcmd r c:00618
rrcmd r c:0061C
rrcmd r c:00620
rrcmd r c:00624
rrcmd r c:00628
rrcmd r c:0062C
rrcmd r c:00630
rrcmd r c:00634
rrcmd r c:00638
rrcmd r c:0063C
rrcmd r c:00640
rrcmd r c:00644
rrcmd r c:00648
rrcmd r c:0064C
rrcmd r c:00650
rrcmd r c:00654
rrcmd r c:00658
rrcmd r c:0065C
rrcmd r c:00660
rrcmd r c:00664
rrcmd r c:00668
rrcmd r c:0066C
rrcmd r c:00670
rrcmd r c:00674
rrcmd r c:00678
rrcmd r c:0067C
rrcmd r c:00680
rrcmd r c:00684
rrcmd r c:00688
rrcmd r c:0068C
rrcmd r c:00690
rrcmd r c:00694
rrcmd r c:00698
rrcmd r c:0069C
rrcmd r c:006A0
rrcmd r c:006A4
rrcmd r c:006A8
rrcmd r c:006AC
rrcmd r c:006B0
rrcmd r c:006B4
rrcmd r c:006B8
rrcmd r c:006BC
rrcmd r c:006C0
rrcmd r c:006C4
rrcmd r c:006C8
rrcmd r c:006CC
rrcmd r c:006D0
rrcmd r c:006D4
rrcmd r c:006D8
rrcmd r c:006DC
rrcmd r c:006E0
rrcmd r c:006E4
rrcmd r c:006E8
rrcmd r c:006EC
rrcmd r c:006F0
rrcmd r c:006F4
rrcmd r c:006F8
rrcmd r c:006FC
rrcmd r c:00700
rrcmd r c:00704
rrcmd r c:00708
rrcmd r c:0070C
rrcmd r c:00710
rrcmd r c:00714
rrcmd r c:00718
rrcmd r c:0071C
rrcmd r c:00720
rrcmd r c:00724
rrcmd r c:00728
rrcmd r c:0072C
rrcmd r c:00730
rrcmd r c:00734
rrcmd r c:00738
rrcmd r c:0073C
rrcmd r c:00740
rrcmd r c:00744
rrcmd r c:00748
rrcmd r c:0074C
rrcmd r c:00750
rrcmd r c:00754
rrcmd r c:00758
rrcmd r c:0075C
rrcmd r c:00760
rrcmd r c:00764
rrcmd r c:00768
rrcmd r c:0076C
rrcmd r c:00770
rrcmd r c:00774
rrcmd r c:00778
rrcmd r c:0077C
rrcmd r c:00780
rrcmd r c:00784
rrcmd r c:00788
rrcmd r c:0078C
rrcmd r c:00790
rrcmd r c:00794
rrcmd r c:00798
rrcmd r c:0079C
rrcmd r c:007A0
rrcmd r c:007A4
rrcmd r c:007A8
rrcmd r c:007AC
rrcmd r c:007B0
rrcmd r c:007B4
rrcmd r c:007B8
rrcmd r c:007BC
rrcmd r c:007C0
rrcmd r c:007C4
rrcmd r c:007C8
rrcmd r c:007CC
rrcmd r c:007D0
rrcmd r c:007D4
rrcmd r c:007D8
rrcmd r c:007DC
rrcmd r c:007E0
rrcmd r c:007E4
rrcmd r c:007E8
rrcmd r c:007EC
rrcmd r c:007F0
rrcmd r c:007F4
rrcmd r c:007F8
rrcmd r c:007FC
rrcmd r 0:00000
rrcmd r 0:00004
rrcmd r 0:00008
rrcmd r 0:0000C
rrcmd r 0:00010
rrcmd r 0:00014
rrcmd r 0:00018
rrcmd r 0:0001C
rrcmd r 0:00020
rrcmd r 0:80040
rrcmd r 0:80044
rrcmd r 0:80048
rrcmd r 0:8004C
rrcmd r 0:80050
rrcmd r 0:80054
rrcmd r 0:80058
rrcmd r 0:8005C
rrcmd r 0:8006C
rrcmd r 0:80070
rrcmd r 0:80078
rrcmd r 0:80060
rrcmd r 0:80064
rrcmd r 0:80068
Release 13.3 ngdbuild O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line:
/afs/cern.ch/project/parc/elec/xilinx/xilinx133/ISE_DS/ISE/bin/lin64/unwrapped/n
gdbuild -uc synplicity.ucf syn_tdc.edf
Executing edif2ngd "syn_tdc.edf" "syn_tdc.ngo"
Release 13.3 - edif2ngd O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 13.3 edif2ngd O.76xd (lin64)
INFO:NgdBuild - Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Applying constraints in "syn_tdc.ncf" to module "top_tdc"...
Checking Constraint Associations...
Writing module to "syn_tdc.ngo"...
Reading NGO file
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.ngo" ...
Loading design module
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/blk_mem_circ_buff_v6_4
.ngc"...
Loading design module
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_64x512.ngc"...
Loading design module
"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_32x512.ngc"...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "synplicity.ucf" ...
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
'gnum_interface_block.cmp_clk_in.rx_pll_adv_inst' of type PLL_ADV has been
changed from 'VIRTEX5' to 'SPARTAN6' to correct post-ngdbuild and timing
simulation for this primitive. In order for functional simulation to be
correct, the value of SIM_DEVICE should be changed in this same manner in the
source netlist or constraint file.
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:178 - TNM 'gnum_interface_block_cmp_clk_in_buf_P_clk',
used in period specification 'TS_gnum_interface_block_cmp_clk_in_buf_P_clk',
was traced into PLL_ADV instance
gnum_interface_block.cmp_clk_in.rx_pll_adv_inst. The following new TNM groups
and period specifications were generated at the PLL_ADV output(s):
CLKOUT0: <TIMESPEC TS_gnum_interface_block_un1_cmp_clk_in = PERIOD
"gnum_interface_block_un1_cmp_clk_in"
TS_gnum_interface_block_cmp_clk_in_buf_P_clk / 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'gnum_interface_block_cmp_clk_in_buf_P_clk',
used in period specification 'TS_gnum_interface_block_cmp_clk_in_buf_P_clk',
was traced into PLL_ADV instance
gnum_interface_block.cmp_clk_in.rx_pll_adv_inst. The following new TNM groups
and period specifications were generated at the PLL_ADV output(s):
CLKOUT2: <TIMESPEC TS_gnum_interface_block_cmp_clk_in_rx_pllout_x1_0 = PERIOD
"gnum_interface_block_cmp_clk_in_rx_pllout_x1_0"
TS_gnum_interface_block_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%>
WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "acam_refclk_i" OFFSET
= IN: 6.000 : BEFORE tdc_clk_p_i;> [synplicity.ucf(44)], is specified
without a duration. This will result in a lack of hold time checks in timing
reports. If hold time checks are desired a duration value should be
specified following the 'VALID' keyword.
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 2
Total memory usage is 501832 kilobytes
Writing NGD file "syn_tdc.ngd" ...
Total REAL time to NGDBUILD completion: 39 sec
Total CPU time to NGDBUILD completion: 28 sec
Writing NGDBUILD log file "syn_tdc.bld"...
This diff is collapsed.
fsm_encoding {36887882} onehot
fsm_state_encoding {36887882} active {00000000000}
fsm_state_encoding {36887882} inactive {00000000011}
fsm_state_encoding {36887882} get_stamp1 {00000000101}
fsm_state_encoding {36887882} get_stamp2 {00000001001}
fsm_state_encoding {36887882} wr_config {00000010001}
fsm_state_encoding {36887882} rdbk_config {00000100001}
fsm_state_encoding {36887882} rd_status {00001000001}
fsm_state_encoding {36887882} rd_ififo1 {00010000001}
fsm_state_encoding {36887882} rd_ififo2 {00100000001}
fsm_state_encoding {36887882} rd_start01 {01000000001}
fsm_state_encoding {36887882} wr_reset {10000000001}
fsm_registers {36887882} {engine_st[0]} {engine_st[1]} {engine_st[2]} {engine_st[3]} {engine_st[4]} {engine_st[5]} {engine_st[6]} {engine_st[7]} {engine_st[8]} {engine_st[9]} {engine_st_i[10]}
fsm_encoding {23777771} onehot
fsm_state_encoding {23777771} idle {0000000}
fsm_state_encoding {23777771} rd_start {0000011}
fsm_state_encoding {23777771} rd_fetch {0000101}
fsm_state_encoding {23777771} rd_ack {0001001}
fsm_state_encoding {23777771} wr_start {0010001}
fsm_state_encoding {23777771} wr_push {0100001}
fsm_state_encoding {23777771} wr_ack {1000001}
fsm_registers {23777771} {acam_data_st[0]} {acam_data_st[1]} {acam_data_st[2]} {acam_data_st[3]} {acam_data_st[4]} {acam_data_st[5]} {acam_data_st_i[6]}
fsm_encoding {38907903} sequential
fsm_state_encoding {38907903} idle {00}
fsm_state_encoding {38907903} mem_access {01}
fsm_state_encoding {38907903} mem_access_and_acknowledge {10}
fsm_state_encoding {38907903} acknowledge {11}
fsm_registers {38907903} {wb_pipelined_st[1]} {wb_pipelined_st[0]}
fsm_encoding {3317371734} onehot
fsm_state_encoding {3317371734} start {00000}
fsm_state_encoding {3317371734} sending_instruction {00011}
fsm_state_encoding {3317371734} sending_data {00101}
fsm_state_encoding {3317371734} rest {01001}
fsm_state_encoding {3317371734} done {10001}
fsm_registers {3317371734} {pll_init_st[0]} {pll_init_st[1]} {pll_init_st[2]} {pll_init_st[3]} {pll_init_st_i[4]}
fsm_encoding {1515541555} onehot
fsm_state_encoding {1515541555} 0000 {000000001}
fsm_state_encoding {1515541555} 0001 {000000010}
fsm_state_encoding {1515541555} 0010 {000000100}
fsm_state_encoding {1515541555} 0011 {000001000}
fsm_state_encoding {1515541555} 0100 {000010000}
fsm_state_encoding {1515541555} 0101 {000100000}
fsm_state_encoding {1515541555} 0110 {001000000}
fsm_state_encoding {1515541555} 0111 {010000000}
fsm_state_encoding {1515541555} 1001 {100000000}
fsm_registers {1515541555} {state[0]} {state[1]} {state[2]} {state[3]} {state[4]} {state[5]} {state[6]} {state[7]} {state[8]}
fsm_encoding {1414141416} sequential
fsm_state_encoding {1414141416} 0000 {0}
fsm_state_encoding {1414141416} 0001 {1}
fsm_registers {1414141416} {state[0]}
fsm_encoding {1414141417} sequential
fsm_state_encoding {1414141417} 0000 {0}
fsm_state_encoding {1414141417} 0001 {1}
fsm_registers {1414141417} {state[0]}
fsm_encoding {2734443448} sequential
fsm_state_encoding {2734443448} wb_idle {00}
fsm_state_encoding {2734443448} wb_read_fifo {01}
fsm_state_encoding {2734443448} wb_cycle {10}
fsm_state_encoding {2734443448} wb_wait_ack {11}
fsm_registers {2734443448} {wishbone_current_state[1]} {wishbone_current_state[0]}
fsm_encoding {2724842489} sequential
fsm_state_encoding {2724842489} l2p_idle {00}
fsm_state_encoding {2724842489} l2p_header {01}
fsm_state_encoding {2724842489} l2p_data {10}
fsm_registers {2724842489} {l2p_read_cpl_current_state[1]} {l2p_read_cpl_current_state[0]}
fsm_encoding {28327432710} onehot
fsm_state_encoding {28327432710} dma_idle {0000001}
fsm_state_encoding {28327432710} dma_start_transfer {0000010}
fsm_state_encoding {28327432710} dma_transfer {0000100}
fsm_state_encoding {28327432710} dma_start_chain {0001000}
fsm_state_encoding {28327432710} dma_chain {0010000}
fsm_state_encoding {28327432710} dma_error {0100000}
fsm_state_encoding {28327432710} dma_abort {1000000}
fsm_registers {28327432710} {dma_ctrl_current_state[0]} {dma_ctrl_current_state[1]} {dma_ctrl_current_state[2]} {dma_ctrl_current_state[3]} {dma_ctrl_current_state[4]} {dma_ctrl_current_state[5]} {dma_ctrl_current_state[6]}
fsm_encoding {29312431211} onehot
fsm_state_encoding {29312431211} l2p_idle {00000001}
fsm_state_encoding {29312431211} l2p_wait_data {00000010}
fsm_state_encoding {29312431211} l2p_header {00000100}
fsm_state_encoding {29312431211} l2p_addr_h {00001000}
fsm_state_encoding {29312431211} l2p_addr_l {00010000}
fsm_state_encoding {29312431211} l2p_data {00100000}
fsm_state_encoding {29312431211} l2p_last_data {01000000}
fsm_state_encoding {29312431211} l2p_wait_rdy {10000000}
fsm_registers {29312431211} {l2p_dma_current_state[0]} {l2p_dma_current_state[1]} {l2p_dma_current_state[2]} {l2p_dma_current_state[3]} {l2p_dma_current_state[4]} {l2p_dma_current_state[5]} {l2p_dma_current_state[6]} {l2p_dma_current_state[7]}
fsm_encoding {30272427212} onehot
fsm_state_encoding {30272427212} p2l_idle {00001}
fsm_state_encoding {30272427212} p2l_header {00010}
fsm_state_encoding {30272427212} p2l_addr_h {00100}
fsm_state_encoding {30272427212} p2l_addr_l {01000}
fsm_state_encoding {30272427212} p2l_wait_read_completion {10000}
fsm_registers {30272427212} {p2l_dma_current_state[0]} {p2l_dma_current_state[1]} {p2l_dma_current_state[2]} {p2l_dma_current_state[3]} {p2l_dma_current_state[4]}
<html>
<head>
<title>syntmp/syn_tdc_srr.htm log file</title>
</head>
<frameset cols="20%, 80%">
<frameset rows="70%, 30%">
<frame src="syntmp/syn_tdc_toc.htm" name="tocFrame">
<frame src="syntmp/syn_tdc_flink.htm" name="linkFrame">
</frameset>
<frame src="syntmp/syn_tdc_srr.htm" name="srrFrame">
</frameset>
</html>
Release 13.3 Map O.76xd (lin64)
Xilinx Map Application Log File for Design 'top_tdc'
Design Information
------------------
Command Line : map -detail -w -timing -ol high syn_tdc.ngd
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Nov 16 18:00:53 2011
Mapping design into LUTs...
Writing file syn_tdc.ngm...
Running directed packing...
WARNING:Pack:2548 - The register "spec_aux3_o_1" has the property IOB=TRUE, but
was not packed into the ILOGIC component.
WARNING:Pack:2548 - The register "spec_aux5_o_1" has the property IOB=TRUE, but
was not packed into the ILOGIC component.
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3223 - Timing constraint TS_1039_1 = MAXDELAY FROM TIMEGRP "from_1039_1" TO TIMEGRP "to_1039_0" 20 ns ignored during timing
analysis.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 40 secs
Total CPU time at the beginning of Placer: 1 mins 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:61457d2f) REAL time: 45 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:61457d2f) REAL time: 46 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:61457d2f) REAL time: 46 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:d9a8d7be) REAL time: 1 mins 28 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:d9a8d7be) REAL time: 1 mins 28 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:d9a8d7be) REAL time: 1 mins 28 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:d9a8d7be) REAL time: 1 mins 29 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:d9a8d7be) REAL time: 1 mins 29 secs
Phase 9.8 Global Placement
......................
................................................................................................................................
...............................................
.........................
Phase 9.8 Global Placement (Checksum:f822b5fa) REAL time: 2 mins 19 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:f822b5fa) REAL time: 2 mins 19 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:8cddda7) REAL time: 2 mins 51 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:8cddda7) REAL time: 2 mins 51 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:14718f9c) REAL time: 2 mins 52 secs
Total REAL time to Placer completion: 3 mins 4 secs
Total CPU time to Placer completion: 5 mins 35 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 4
Slice Logic Utilization:
Number of Slice Registers: 4,925 out of 54,576 9%
Number used as Flip Flops: 4,902
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,916 out of 27,288 14%
Number used as logic: 3,607 out of 27,288 13%
Number using O6 output only: 2,447
Number using O5 output only: 314
Number using O5 and O6: 846
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 309
Number with same-slice register load: 289
Number with same-slice carry load: 11
Number with other load: 9
Slice Logic Distribution:
Number of occupied Slices: 1,858 out of 6,822 27%
Nummber of MUXCYs used: 1,244 out of 13,644 9%
Number of LUT Flip Flop pairs used: 6,019
Number with an unused Flip Flop: 1,446 out of 6,019 24%
Number with an unused LUT: 2,103 out of 6,019 34%
Number of fully used LUT-FF pairs: 2,470 out of 6,019 41%
Number of unique control sets: 212
Number of slice register sites lost
to control set restrictions: 674 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 136 out of 296 45%
Number of LOCed IOBs: 136 out of 136 100%
IOB Flip Flops: 36
Specific Feature Utilization:
Number of RAMB16BWERs: 11 out of 116 9%
Number of RAMB8BWERs: 1 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 34 out of 376 9%
Number used as ILOGIC2s: 14
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 8 out of 376 2%
Number used as IODELAY2s: 8
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 42 out of 376 11%
Number used as OLOGIC2s: 22
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.43
Peak Memory Usage: 932 MB
Total REAL time to MAP completion: 3 mins 11 secs
Total CPU time to MAP completion: 5 mins 47 secs
Mapping completed.
See MAP report file "syn_tdc.mrp" for details.
This diff is collapsed.
This diff is collapsed.
#
# Constraints generated by Synplify Pro map510rc, Build 068R
#
# Location Constraints
NET "rst_n_a_i" LOC="N20" ;
NET "p2l_clk_p_i" LOC="M20" ;
NET "p2l_clk_n_i" LOC="M19" ;
NET "p2l_data_i(0)" LOC="K20" ;
NET "p2l_data_i(1)" LOC="H22" ;
NET "p2l_data_i(2)" LOC="H21" ;
NET "p2l_data_i(3)" LOC="L17" ;
NET "p2l_data_i(4)" LOC="K17" ;
NET "p2l_data_i(5)" LOC="G22" ;
NET "p2l_data_i(6)" LOC="G20" ;
NET "p2l_data_i(7)" LOC="K18" ;
NET "p2l_data_i(8)" LOC="K19" ;
NET "p2l_data_i(9)" LOC="H20" ;
NET "p2l_data_i(10)" LOC="J19" ;
NET "p2l_data_i(11)" LOC="E22" ;
NET "p2l_data_i(12)" LOC="E20" ;
NET "p2l_data_i(13)" LOC="F22" ;
NET "p2l_data_i(14)" LOC="F21" ;
NET "p2l_data_i(15)" LOC="H19" ;
NET "p2l_dframe_i" LOC="J22" ;
NET "p2l_valid_i" LOC="L19" ;
NET "p2l_rdy_o" LOC="J16" ;
#(pad missing) NET "p_wr_req_i[0]" LOC="M22" ;
#(pad missing) NET "p_wr_req_i[1]" LOC="M21" ;
NET "p_wr_rdy_o(0)" LOC="L15" ;
NET "p_wr_rdy_o(1)" LOC="K16" ;
NET "rx_error_o" LOC="J17" ;
#(pad missing) NET "vc_rdy_i[0]" LOC="B21" ;
#(pad missing) NET "vc_rdy_i[1]" LOC="B22" ;
NET "l2p_clk_p_o" LOC="K21" ;
NET "l2p_clk_n_o" LOC="K22" ;
NET "l2p_data_o(0)" LOC="P16" ;
NET "l2p_data_o(1)" LOC="P21" ;
NET "l2p_data_o(2)" LOC="P18" ;
NET "l2p_data_o(3)" LOC="T20" ;
NET "l2p_data_o(4)" LOC="V21" ;
NET "l2p_data_o(5)" LOC="V19" ;
NET "l2p_data_o(6)" LOC="W22" ;
NET "l2p_data_o(7)" LOC="Y22" ;
NET "l2p_data_o(8)" LOC="P22" ;
NET "l2p_data_o(9)" LOC="R22" ;
NET "l2p_data_o(10)" LOC="T21" ;
NET "l2p_data_o(11)" LOC="T19" ;
NET "l2p_data_o(12)" LOC="V22" ;
NET "l2p_data_o(13)" LOC="V20" ;
NET "l2p_data_o(14)" LOC="W20" ;
NET "l2p_data_o(15)" LOC="Y21" ;
NET "l2p_dframe_o" LOC="U22" ;
NET "l2p_valid_o" LOC="T18" ;
NET "l2p_edb_o" LOC="U20" ;
NET "l2p_rdy_i" LOC="U19" ;
NET "l_wr_rdy_i(0)" LOC="R20" ;
NET "l_wr_rdy_i(1)" LOC="T22" ;
NET "p_rd_d_rdy_i(0)" LOC="N16" ;
NET "p_rd_d_rdy_i(1)" LOC="P19" ;
#(pad missing) NET "tx_error_i" LOC="M17" ;
NET "irq_p_o" LOC="U16" ;
NET "spare_o" LOC="AB19" ;
NET "acam_refclk_i" LOC="E16" ;
NET "pll_ld_i" LOC="C18" ;
#(pad missing) NET "pll_refmon_i" LOC="D17" ;
#(pad missing) NET "pll_sdo_i" LOC="AB18" ;
#(pad missing) NET "pll_status_i" LOC="Y18" ;
NET "tdc_clk_p_i" LOC="L20" ;
NET "tdc_clk_n_i" LOC="L22" ;
NET "pll_cs_o" LOC="Y17" ;
NET "pll_dac_sync_o" LOC="AB16" ;
NET "pll_sdi_o" LOC="AA18" ;
NET "pll_sclk_o" LOC="AB17" ;
#(pad missing) NET "err_flag_i" LOC="V11" ;
NET "int_flag_i" LOC="W11" ;
NET "start_dis_o" LOC="T15" ;
NET "start_from_fpga_o" LOC="W17" ;
NET "stop_dis_o" LOC="U15" ;
NET "data_bus_io(0)" LOC="W6" ;
NET "data_bus_io(1)" LOC="Y6" ;
NET "data_bus_io(2)" LOC="V7" ;
NET "data_bus_io(3)" LOC="W8" ;
NET "data_bus_io(4)" LOC="T8" ;
NET "data_bus_io(5)" LOC="AA12" ;
NET "data_bus_io(6)" LOC="U8" ;
NET "data_bus_io(7)" LOC="AB12" ;
NET "data_bus_io(8)" LOC="Y5" ;
NET "data_bus_io(9)" LOC="AB5" ;
NET "data_bus_io(10)" LOC="R9" ;
NET "data_bus_io(11)" LOC="R8" ;
NET "data_bus_io(12)" LOC="AA6" ;
NET "data_bus_io(13)" LOC="AB6" ;
NET "data_bus_io(14)" LOC="U9" ;
NET "data_bus_io(15)" LOC="V9" ;
NET "data_bus_io(16)" LOC="Y7" ;
NET "data_bus_io(17)" LOC="AB7" ;
NET "data_bus_io(18)" LOC="AA8" ;
NET "data_bus_io(19)" LOC="AB8" ;
NET "data_bus_io(20)" LOC="T10" ;
NET "data_bus_io(21)" LOC="U10" ;
NET "data_bus_io(22)" LOC="W10" ;
NET "data_bus_io(23)" LOC="Y10" ;
NET "data_bus_io(24)" LOC="Y9" ;
NET "data_bus_io(25)" LOC="AB9" ;
NET "data_bus_io(26)" LOC="AA4" ;
NET "data_bus_io(27)" LOC="AB4" ;
NET "ef1_i" LOC="W12" ;
NET "ef2_i" LOC="R11" ;
NET "lf1_i" LOC="Y12" ;
NET "lf2_i" LOC="T11" ;
NET "address_o(0)" LOC="T12" ;
NET "address_o(1)" LOC="U12" ;
NET "address_o(2)" LOC="Y15" ;
NET "address_o(3)" LOC="AB15" ;
NET "cs_n_o" LOC="T14" ;
NET "oe_n_o" LOC="V13" ;
NET "rd_n_o" LOC="AB13" ;
NET "wr_n_o" LOC="Y13" ;
#(pad missing) NET "tdc_in_fpga_5_i" LOC="AA14" ;
NET "mute_inputs_o" LOC="C19" ;
NET "tdc_led_status_o" LOC="W13" ;
NET "tdc_led_trig1_o" LOC="W14" ;
NET "tdc_led_trig2_o" LOC="Y14" ;
NET "tdc_led_trig3_o" LOC="Y16" ;
NET "tdc_led_trig4_o" LOC="W15" ;
NET "tdc_led_trig5_o" LOC="V17" ;
NET "term_en_1_o" LOC="W18" ;
NET "term_en_2_o" LOC="B20" ;
NET "term_en_3_o" LOC="A20" ;
NET "term_en_4_o" LOC="H10" ;
NET "term_en_5_o" LOC="E6" ;
NET "spec_aux0_i" LOC="C22" ;
NET "spec_aux1_i" LOC="D21" ;
NET "spec_aux2_o" LOC="G19" ;
NET "spec_aux3_o" LOC="F20" ;
NET "spec_aux4_o" LOC="F18" ;
NET "spec_aux5_o" LOC="C20" ;
NET "spec_led_green_o" LOC="E5" ;
NET "spec_led_red_o" LOC="D5" ;
NET "spec_clk_i" LOC="H12" ;
# End of generated constraints
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="2">
<CmdHistory>
</CmdHistory>
</DesignSummary>
This diff is collapsed.
This diff is collapsed.
Release 13.3 - Bitgen O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
/afs/cern.ch/project/parc/elec/xilinx/xilinx133/ISE_DS/ISE/.
"top_tdc" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
Wed Nov 16 18:06:54 2011
/afs/cern.ch/project/parc/elec/xilinx/xilinx133/ISE_DS/ISE/bin/lin64/unwrapped/bitgen par_tdc.ncd tdc
INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER).
9K Block RAM initialization data, both user defined and default, requires a
special bit stream format. For more information, please reference Xilinx
Answer Record 39999.
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable* |
+----------------------+----------------------+
| DebugBitstream | No* |
+----------------------+----------------------+
| ConfigRate | 2* |
+----------------------+----------------------+
| StartupClk | Cclk* |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup* |
+----------------------+----------------------+
| TckPin | Pullup* |
+----------------------+----------------------+
| TdiPin | Pullup* |
+----------------------+----------------------+
| TdoPin | Pullup* |
+----------------------+----------------------+
| TmsPin | Pullup* |
+----------------------+----------------------+
| UnusedPin | Pulldown* |
+----------------------+----------------------+
| GWE_cycle | 6* |
+----------------------+----------------------+
| GTS_cycle | 5* |
+----------------------+----------------------+
| LCK_cycle | NoWait* |
+----------------------+----------------------+
| DONE_cycle | 4* |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No* |
+----------------------+----------------------+
| DonePipe | No* |
+----------------------+----------------------+
| Security | None* |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No* |
+----------------------+----------------------+
| Reset_on_err | No* |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No* |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk* |
+----------------------+----------------------+
| sw_gwe_cycle | 5* |
+----------------------+----------------------+
| sw_gts_cycle | 4* |
+----------------------+----------------------+
| multipin_wakeup | No* |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No* |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| MaskVectorFile | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | None* |
+----------------------+----------------------+
| spi_buswidth | 1* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No* |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
No constraints file was processed.
Running DRC.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
DRC detected 0 errors and 1 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "tdc.bit".
Bitstream generation is complete.
Release 13.3 Drc O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Wed Nov 16 18:06:54 2011
drc -z par_tdc.ncd
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
DRC detected 0 errors and 1 warnings. Please see the previously displayed
individual error or warning messages for more details.
INFILE=/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/par_tdc.ncd
OUTFILE=/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc.bit
FAMILY=Spartan6
PART=xc6slx45t-3fgg484
WORKINGDIR=/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn
LICENSE=ISE
USER_INFO=174122087_174122088_206270080_700
ngdbuild -uc synplicity.ucf syn_tdc.edf
map -detail -w -timing -ol high syn_tdc.ngd
par -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
bitgen par_tdc.ncd tdc
This diff is collapsed.
This diff is collapsed.
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000E02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 02000064
rrcmd w 0:80014 080003E8
rrcmd w 0:80018 000000FF
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
This diff is collapsed.
This diff is collapsed.
#Build: Synplify Pro D-2010.03, Build 093R, Feb 19 2010
#install: /afs/cern.ch/project/parc/elec/synplify/D-2010.03
#OS: Linux
#Hostname: lxparc41.cern.ch
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/syn_tdc.edf 1311271086
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_64x512.ngc 1311271059
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/fifo_32x512.ngc 1311271059
OK
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Thu Jul 21 20:02:16 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
err_flag_i_IBUF
int_flag_i_IBUF
p_wr_req_i(0)_IBUF
p_wr_req_i(1)_IBUF
pll_refmon_i_IBUF
pll_sdo_i_IBUF
pll_status_i_IBUF
tx_error_i_IBUF
vc_rdy_i(0)_IBUF
vc_rdy_i(1)_IBUF
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment