Commits · cd6e955a4f9adb2acd3bd23680b1ab77e5a68b6d · Projects / FMC TDC 1ns 5cha

11 Nov, 2011 2 commits

serrano authored Nov 11, 2011


git-svn-id: http://svn.ohwr.org/fmc-tdc@68 85dfdc96-de2c-444c-878d-45b388be74a9

cd6e955a

First quick assessment of some of the files. · 3f142deb
serrano authored Nov 11, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@67 85dfdc96-de2c-444c-878d-45b388be74a9
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3f142deb

08 Nov, 2011 7 commits
- Comments added on the VHDL code · 49fc1bea
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@66 85dfdc96-de2c-444c-878d-45b388be74a9
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  49fc1bea
- Missing files from the acam test · 10895a83
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@65 85dfdc96-de2c-444c-878d-45b388be74a9
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  10895a83
- Synthesis results · 1216d1c6
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@64 85dfdc96-de2c-444c-878d-45b388be74a9
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  1216d1c6
- Simulation folder updated · 7bc6f27d
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@63 85dfdc96-de2c-444c-878d-45b388be74a9
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  7bc6f27d
- Timing problems solved by adding registers on the Term En outputs · 7f3e7a0e
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@59 85dfdc96-de2c-444c-878d-45b388be74a9
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  7f3e7a0e
- Completion of the Coregen files from the new version of the Xilin 13.3 software · d4b1ca52
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@58 85dfdc96-de2c-444c-878d-45b388be74a9
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  d4b1ca52
- New versions of the core from Coregen to instantiate the RAM block for the Circular Buffer · f33ef0bc
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@57 85dfdc96-de2c-444c-878d-45b388be74a9
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  f33ef0bc
01 Nov, 2011 1 commit
- Operational version with full timestamps and no timing errors · 07d08c43
  penacoba authored Nov 01, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@56 85dfdc96-de2c-444c-878d-45b388be74a9
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  07d08c43
24 Oct, 2011 2 commits
- Testbench adapted to new values for start retrigger · 9800f270
  penacoba authored Oct 24, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@55 85dfdc96-de2c-444c-878d-45b388be74a9
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  9800f270
- First complete version. Simulation ok. Pending from synthesis. · 57ec601c
  penacoba authored Oct 24, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@54 85dfdc96-de2c-444c-878d-45b388be74a9
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  57ec601c
20 Oct, 2011 1 commit

Raw_timestamps version · 8250f67c

penacoba authored Oct 20, 2011


git-svn-id: http://svn.ohwr.org/fmc-tdc@53 85dfdc96-de2c-444c-878d-45b388be74a9

8250f67c

18 Oct, 2011 3 commits
- Improved models for testbench · 757b8fff
  penacoba authored Oct 18, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@52 85dfdc96-de2c-444c-878d-45b388be74a9
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  757b8fff
- Operational version of the data engine FSM · 320d75f0
  penacoba authored Oct 18, 2011
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+ corrected bug of start_from_fpga generation after reset


git-svn-id: http://svn.ohwr.org/fmc-tdc@51 85dfdc96-de2c-444c-878d-45b388be74a9
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  320d75f0
- git-svn-id: http://svn.ohwr.org/fmc-tdc@50 85dfdc96-de2c-444c-878d-45b388be74a9 · dc894263
  penacoba authored Oct 18, 2011
  
  dc894263
11 Oct, 2011 1 commit
- New Register Control module for the core based in RAM block · fbdc4006
  penacoba authored Oct 11, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@49 85dfdc96-de2c-444c-878d-45b388be74a9
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  fbdc4006
06 Oct, 2011 3 commits

Version synthesised and tried on hardware, that allows read/write on the memory… · 8c49a6d8

penacoba authored Oct 06, 2011

Version synthesised and tried on hardware, that allows read/write on the memory through the CSR port.


git-svn-id: http://svn.ohwr.org/fmc-tdc@48 85dfdc96-de2c-444c-878d-45b388be74a9

8c49a6d8

Memory core generated by coregen. · b5af3b6c

penacoba authored Oct 06, 2011


git-svn-id: http://svn.ohwr.org/fmc-tdc@47 85dfdc96-de2c-444c-878d-45b388be74a9

b5af3b6c

Generated circular buffer with RAM block. · 4af69194
penacoba authored Oct 06, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@46 85dfdc96-de2c-444c-878d-45b388be74a9
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4af69194

04 Oct, 2011 4 commits
- First version of binary file that obtains correct timestamps from the ACAM for any delay. · 07fa5b23
  penacoba authored Oct 04, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@45 85dfdc96-de2c-444c-878d-45b388be74a9
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  07fa5b23
- Udpated simulations · e4bc3c96
  penacoba authored Oct 04, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@44 85dfdc96-de2c-444c-878d-45b388be74a9
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  e4bc3c96
- Adjusted test_bench · 4a2b9391
  penacoba authored Oct 04, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@43 85dfdc96-de2c-444c-878d-45b388be74a9
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  4a2b9391
- Modifications of the Acam enable and start from FPGA for correct operation · 442adcb5
  penacoba authored Oct 04, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@42 85dfdc96-de2c-444c-878d-45b388be74a9
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  442adcb5
23 Sep, 2011 1 commit

Modifications for large Tstart pulse · d7077e06

penacoba authored Sep 23, 2011


git-svn-id: http://svn.ohwr.org/fmc-tdc@41 85dfdc96-de2c-444c-878d-45b388be74a9

d7077e06

03 Aug, 2011 1 commit
- Top reorganized, and outputs for the Acam properly registered. · 8d74d3fa
  penacoba authored Aug 03, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@40 85dfdc96-de2c-444c-878d-45b388be74a9
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  8d74d3fa
29 Jul, 2011 5 commits
- New preliminary modules after design specification review · 552710a7
  penacoba authored Jul 29, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@39 85dfdc96-de2c-444c-878d-45b388be74a9
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  552710a7
- simulation files clean-up · a4e6cbd1
  penacoba authored Jul 29, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@38 85dfdc96-de2c-444c-878d-45b388be74a9
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  a4e6cbd1
- Synthesis scripts after the ACAM TDC test · ab7af5fd
  penacoba authored Jul 29, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@37 85dfdc96-de2c-444c-878d-45b388be74a9
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  ab7af5fd
- cleaned up version of the ACAM TDC synthesis results · d13db7b9
  penacoba authored Jul 29, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@36 85dfdc96-de2c-444c-878d-45b388be74a9
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  d13db7b9
- cleaned up version of the PLL test synthesis results · cb30b5d1
  penacoba authored Jul 29, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@35 85dfdc96-de2c-444c-878d-45b388be74a9
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  cb30b5d1
21 Jul, 2011 1 commit
- Improved version of PLL test + first operating version of ACAM test · b5ae1362
  penacoba authored Jul 21, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@34 85dfdc96-de2c-444c-878d-45b388be74a9
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  b5ae1362
18 Jul, 2011 1 commit
- First operating .bit for the test of the mezzaning pll inside syn/test_tdc_pll · c86fe33b
  penacoba authored Jul 18, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@33 85dfdc96-de2c-444c-878d-45b388be74a9
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  c86fe33b
11 Jul, 2011 1 commit

First versions for hardware test · b4d12c32

penacoba authored Jul 11, 2011



git-svn-id: http://svn.ohwr.org/fmc-tdc@32 85dfdc96-de2c-444c-878d-45b388be74a9

b4d12c32

09 Mar, 2011 1 commit
- git-svn-id: http://svn.ohwr.org/fmc-tdc@1 85dfdc96-de2c-444c-878d-45b388be74a9 · 4c9264e1
  nvoumard authored Mar 09, 2011
  
  4c9264e1