Commits · f5d073519465fb60717fd3f92dc4d99fa43ecdd8 · Projects / FMC TDC 1ns 5cha

08 Aug, 2012 3 commits

temp storage of pts pythin tests · f5d07351

egousiou authored Aug 08, 2012

git-svn-id: http://svn.ohwr.org/fmc-tdc@83 85dfdc96-de2c-444c-878d-45b388be74a9

f5d07351

documentation cleanup · c0124fd7

egousiou authored Aug 08, 2012

git-svn-id: http://svn.ohwr.org/fmc-tdc@82 85dfdc96-de2c-444c-878d-45b388be74a9

c0124fd7

documentation added · 8de6a101

egousiou authored Aug 08, 2012

git-svn-id: http://svn.ohwr.org/fmc-tdc@81 85dfdc96-de2c-444c-878d-45b388be74a9

8de6a101

21 Jun, 2012 2 commits
- added folder with just the .bit files · f1811356
  egousiou authored Jun 21, 2012
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git-svn-id: http://svn.ohwr.org/fmc-tdc@80 85dfdc96-de2c-444c-878d-45b388be74a9
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  f1811356
- synthesis and par files for tdc v2 · 8acb2ee2
  egousiou authored Jun 21, 2012
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git-svn-id: http://svn.ohwr.org/fmc-tdc@79 85dfdc96-de2c-444c-878d-45b388be74a9
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  8acb2ee2
20 Jun, 2012 1 commit
- temp storage of test production suite python scripts · c95ba653
  egousiou authored Jun 20, 2012
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git-svn-id: http://svn.ohwr.org/fmc-tdc@78 85dfdc96-de2c-444c-878d-45b388be74a9
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  c95ba653
14 Jun, 2012 1 commit
- changes for new version (v2) of TDC mezz · 84739413
  egousiou authored Jun 14, 2012
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git-svn-id: http://svn.ohwr.org/fmc-tdc@77 85dfdc96-de2c-444c-878d-45b388be74a9
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  84739413
11 Jun, 2012 1 commit

added logic for controlling the mezzanine DAC that controls the OSC1 that controls the PLL! · d34e1405

egousiou authored Jun 11, 2012

added leds_manager unit to remove logic from top level
/!\treatment of 2 bugs in data_formatting (not completed though, check top_tdc.vhd comments) 


git-svn-id: http://svn.ohwr.org/fmc-tdc@76 85dfdc96-de2c-444c-878d-45b388be74a9

d34e1405

18 May, 2012 1 commit

I) Use of latest gn4124_core version (with pipelined CSR) · 14637348

egousiou authored May 18, 2012

II) Use of wb_addr_decoder.vhd
III) Added I2C for mezzanine, 1-wire for mezzanine and 1-wire for carrier 
IV) Implemented irq_generator.vhd
V) Use of irq_controller.vhd
VI) clks_rsts_manager.vhd: Changed the internal reset generation; added DFFs to pll_sdi_o, pll_cs_o outputs
VII) General revamping, comments added, units and signals renamed

git-svn-id: http://svn.ohwr.org/fmc-tdc@75 85dfdc96-de2c-444c-878d-45b388be74a9

14637348

16 Nov, 2011 3 commits
- Syn folder after manual cleanup to remove svn lock · fea36da1
  penacoba authored Nov 16, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@74 85dfdc96-de2c-444c-878d-45b388be74a9
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  fea36da1
- trying to cleanup svn · a03c43a2
  penacoba authored Nov 16, 2011
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  a03c43a2
- Most of the comments from the code review have been integrated · 17667554
  penacoba authored Nov 16, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@72 85dfdc96-de2c-444c-878d-45b388be74a9
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  17667554
11 Nov, 2011 5 commits
- Comments gathered in summary · a86d35bc
  penacoba authored Nov 11, 2011
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  a86d35bc
- Uploaded Tom's comments for the review · 6c090d60
  twlostow authored Nov 11, 2011
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  6c090d60
- git-svn-id: http://svn.ohwr.org/fmc-tdc@69 85dfdc96-de2c-444c-878d-45b388be74a9 · 9eebe296
  egousiou authored Nov 11, 2011
  
  9eebe296
- One more file reviewed. · cd6e955a
  serrano authored Nov 11, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@68 85dfdc96-de2c-444c-878d-45b388be74a9
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  cd6e955a
- First quick assessment of some of the files. · 3f142deb
  serrano authored Nov 11, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@67 85dfdc96-de2c-444c-878d-45b388be74a9
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  3f142deb
08 Nov, 2011 7 commits
- Comments added on the VHDL code · 49fc1bea
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@66 85dfdc96-de2c-444c-878d-45b388be74a9
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  49fc1bea
- Missing files from the acam test · 10895a83
  penacoba authored Nov 08, 2011
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  10895a83
- Synthesis results · 1216d1c6
  penacoba authored Nov 08, 2011
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  1216d1c6
- Simulation folder updated · 7bc6f27d
  penacoba authored Nov 08, 2011
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  7bc6f27d
- Timing problems solved by adding registers on the Term En outputs · 7f3e7a0e
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@59 85dfdc96-de2c-444c-878d-45b388be74a9
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  7f3e7a0e
- Completion of the Coregen files from the new version of the Xilin 13.3 software · d4b1ca52
  penacoba authored Nov 08, 2011
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  d4b1ca52
- New versions of the core from Coregen to instantiate the RAM block for the Circular Buffer · f33ef0bc
  penacoba authored Nov 08, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@57 85dfdc96-de2c-444c-878d-45b388be74a9
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  f33ef0bc
01 Nov, 2011 1 commit
- Operational version with full timestamps and no timing errors · 07d08c43
  penacoba authored Nov 01, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@56 85dfdc96-de2c-444c-878d-45b388be74a9
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  07d08c43
24 Oct, 2011 2 commits
- Testbench adapted to new values for start retrigger · 9800f270
  penacoba authored Oct 24, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@55 85dfdc96-de2c-444c-878d-45b388be74a9
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  9800f270
- First complete version. Simulation ok. Pending from synthesis. · 57ec601c
  penacoba authored Oct 24, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@54 85dfdc96-de2c-444c-878d-45b388be74a9
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  57ec601c
20 Oct, 2011 1 commit

Raw_timestamps version · 8250f67c

penacoba authored Oct 20, 2011


git-svn-id: http://svn.ohwr.org/fmc-tdc@53 85dfdc96-de2c-444c-878d-45b388be74a9

8250f67c

18 Oct, 2011 3 commits
- Improved models for testbench · 757b8fff
  penacoba authored Oct 18, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@52 85dfdc96-de2c-444c-878d-45b388be74a9
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  757b8fff
- Operational version of the data engine FSM · 320d75f0
  penacoba authored Oct 18, 2011
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+ corrected bug of start_from_fpga generation after reset


git-svn-id: http://svn.ohwr.org/fmc-tdc@51 85dfdc96-de2c-444c-878d-45b388be74a9
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  320d75f0
- git-svn-id: http://svn.ohwr.org/fmc-tdc@50 85dfdc96-de2c-444c-878d-45b388be74a9 · dc894263
  penacoba authored Oct 18, 2011
  
  dc894263
11 Oct, 2011 1 commit
- New Register Control module for the core based in RAM block · fbdc4006
  penacoba authored Oct 11, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@49 85dfdc96-de2c-444c-878d-45b388be74a9
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  fbdc4006
06 Oct, 2011 3 commits

Version synthesised and tried on hardware, that allows read/write on the memory… · 8c49a6d8

penacoba authored Oct 06, 2011

Version synthesised and tried on hardware, that allows read/write on the memory through the CSR port.


git-svn-id: http://svn.ohwr.org/fmc-tdc@48 85dfdc96-de2c-444c-878d-45b388be74a9

8c49a6d8

Memory core generated by coregen. · b5af3b6c

penacoba authored Oct 06, 2011


git-svn-id: http://svn.ohwr.org/fmc-tdc@47 85dfdc96-de2c-444c-878d-45b388be74a9

b5af3b6c

Generated circular buffer with RAM block. · 4af69194
penacoba authored Oct 06, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@46 85dfdc96-de2c-444c-878d-45b388be74a9
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4af69194

04 Oct, 2011 4 commits
- First version of binary file that obtains correct timestamps from the ACAM for any delay. · 07fa5b23
  penacoba authored Oct 04, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@45 85dfdc96-de2c-444c-878d-45b388be74a9
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  07fa5b23
- Udpated simulations · e4bc3c96
  penacoba authored Oct 04, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@44 85dfdc96-de2c-444c-878d-45b388be74a9
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  e4bc3c96
- Adjusted test_bench · 4a2b9391
  penacoba authored Oct 04, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@43 85dfdc96-de2c-444c-878d-45b388be74a9
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  4a2b9391
- Modifications of the Acam enable and start from FPGA for correct operation · 442adcb5
  penacoba authored Oct 04, 2011
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git-svn-id: http://svn.ohwr.org/fmc-tdc@42 85dfdc96-de2c-444c-878d-45b388be74a9
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  442adcb5
23 Sep, 2011 1 commit

Modifications for large Tstart pulse · d7077e06

penacoba authored Sep 23, 2011


git-svn-id: http://svn.ohwr.org/fmc-tdc@41 85dfdc96-de2c-444c-878d-45b388be74a9

d7077e06