Programming languages used in this repository

  •   VHDL
    86.26 %
  •   Stata
    5.04 %
  •   SystemVerilog
    4.06 %
  •   Makefile
    3.7 %
  •   Python
    0.66 %
  •   Lua
    0.16 %
  •   Verilog
    0.11 %

Commit statistics for cd6e955a4f9adb2acd3bd23680b1ab77e5a68b6d Mar 09 - Nov 11

  • Total: 35 commits
  • Average per day: 0.1 commits
  • Authors: 3

Commits per day of month

Commits per weekday

Commits per day hour (UTC)