Programming languages used in this repository

  •   VHDL
    86.26 %
  •   Stata
    5.04 %
  •   SystemVerilog
    4.06 %
  •   Makefile
    3.7 %
  •   Python
    0.66 %
  •   Lua
    0.16 %
  •   Verilog
    0.11 %

Commit statistics for d13db7b9c3db7a87d96ae1ffe9e3f5a70bd95ce6 Mar 09 - Jul 29

  • Total: 6 commits
  • Average per day: 0.0 commits
  • Authors: 2

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