WARNING. Release in progress. Do not download anything.
SPEC TDC Release 7.0
Binary
Memory map
See the "SVEC Memory Map" section of the Gateware Architecture Manual
Sources
Release date
22.05.2015
Release notes
Important changes:
- Redesigned clock tree. Now the Wishbone port of the TDC core is operating in the common system clock domain (no cross-clock transfer needed).
- Redesigned readout: separate per-channel FIFO instead of a circular buffer.
- Added last received pulse timestamp registers.
- Added hardware timestamp sequencing.
- Added per-channel input enable.
- Updated the WR Core to the latest version (with Heisenbug fix).
- Dropped the non-WR version of the firmware.
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T.Wlostowski, May 2015