Commit 7a8148c5 authored by Evangelia Gousiou's avatar Evangelia Gousiou

repo cleaned-up

parent d15e4f02
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
#include <linux/module.h>
#include <linux/vermagic.h>
#include <linux/compiler.h>
MODULE_INFO(vermagic, VERMAGIC_STRING);
struct module __this_module
__attribute__((section(".gnu.linkonce.this_module"))) = {
.name = KBUILD_MODNAME,
.init = init_module,
#ifdef CONFIG_MODULE_UNLOAD
.exit = cleanup_module,
#endif
.arch = MODULE_ARCH_INIT,
};
static const struct modversion_info ____versions[]
__used
__attribute__((section("__versions"))) = {
{ 0x35ec255d, "module_layout" },
{ 0x1976aa06, "param_ops_bool" },
{ 0x3539443, "usb_serial_deregister_drivers" },
{ 0xdf6a71a4, "usb_serial_register_drivers" },
{ 0x73c9cdb0, "usb_serial_generic_open" },
{ 0x6143a69d, "dev_warn" },
{ 0x53662107, "tty_encode_baud_rate" },
{ 0x6339a8bc, "mutex_unlock" },
{ 0xcf510c4a, "mutex_lock" },
{ 0x41b8c132, "usb_serial_generic_close" },
{ 0xcea0a119, "kmalloc_caches" },
{ 0x41ad0272, "kmem_cache_alloc_trace" },
{ 0xd44c22ec, "usb_reset_device" },
{ 0x93d085b2, "dev_set_drvdata" },
{ 0x50eedeb8, "printk" },
{ 0x37a0cba, "kfree" },
{ 0x64d0da33, "usb_control_msg" },
{ 0x12da5bb2, "__kmalloc" },
{ 0x35af9caf, "dev_err" },
{ 0xddffa24, "dev_get_drvdata" },
{ 0xb4390f9a, "mcount" },
};
static const char __module_depends[]
__used
__attribute__((section(".modinfo"))) =
"depends=usbserial";
MODULE_ALIAS("usb:v045Bp0053d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0471p066Ad*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0489pE000d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0489pE003d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0745p1000d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v08E6p5501d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v08FDp000Ad*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0BEDp1100d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0BEDp1101d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0FCFp1003d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0FCFp1004d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v0FCFp1006d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10A6pAA26d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10ABp10C5d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10B5pAC70d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p0F91d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p1101d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p1601d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p800Ad*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p803Bd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8044d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p804Ed*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8053d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8054d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8066d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p806Fd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p807Ad*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p80CAd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p80DDd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p80F6d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8115d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p813Dd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p813Fd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p814Ad*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p814Bd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8156d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p815Ed*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p818Bd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p819Fd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81A6d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81A9d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81ACd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81ADd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81C8d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81E2d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81E7d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81E8d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p81F2d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8218d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p822Bd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p826Bd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8293d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p82F9d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8341d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8382d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p83A8d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p83D8d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8411d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8418d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p846Ed*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8477d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p85EAd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p85EBd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8664d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4p8665d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pEA60d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pEA61d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pEA70d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pEA80d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pEA71d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pF001d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pF002d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pF003d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C4pF004d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10C5pEA61d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v10CEpEA6Ad*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v13ADp9999d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v1555p0004d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v166Ap0303d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v16D6p0001d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v16DCp0010d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v16DCp0011d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v16DCp0012d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v16DCp0015d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v17A8p0001d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v17A8p0005d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v17F4pAAAAd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v1843p0200d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v18EFpE00Fd*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v1BE3p07A6d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v3195pF190d*dc*dsc*dp*ic*isc*ip*");
MODULE_ALIAS("usb:v413Cp9500d*dc*dsc*dp*ic*isc*ip*");
MODULE_INFO(srcversion, "FF7E88FED57F3623F48F6A3");
File mode changed from 100644 to 100755
......@@ -6,7 +6,7 @@
# Website: http://www.ohwr.org
sudo rmmod cp210x
cd ~/pts
cd ~/fmc-tdc-1ns-5cha-tst
sudo insmod ./cp210x-driver/cp210x.ko
cd usbdriver
sudo ./usbtmc_load
......@@ -16,7 +16,7 @@ cd ..
LOGDIR=./log_fmctdc1ns5cha_calib
mkdir -p $LOGDIR
sudo rm -fr $LOGDIR/pts*
sudo rm -fr $LOGDIR/fmc-tdc-1ns-5cha-tst*
serial=$1
if [ x$1 = x"" ]; then
......
No preview for this file type
File mode changed from 100644 to 100755
......@@ -34,6 +34,7 @@ original_raw_input = raw_input
sys.path.append('gnurabbit/python/')
sys.path.append('common/')
sys.path.append('common/fmc_delay/software/python/')
sys.path.append('common/usb_box')
sys.path.append('common/cp210x')
sys.path.append('test/fmceeprom/python')
......
File mode changed from 100644 to 100755
......@@ -80,8 +80,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
# Add common modules location tp path
......@@ -161,7 +159,7 @@ def newline():
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc.bin'
FPGA_LOADER_PATH = '../../../../gnurabbit/user/fpga_loader'
......@@ -262,6 +260,7 @@ def main (default_directory='.'):
box.select_trigger_loopback(0)
"""
print "\n\n________________TDC board temperature stablilization_______________\n"
# Access Temperature-and-Unique-ID chip
try:
......@@ -325,7 +324,7 @@ def main (default_directory='.'):
t2 = time.time()
print "FMC temperature is stable after %10.3fs\n"%(t2-t0)
"""
# Enable timestamps aquisition (TDC_START_FPGA pulse sent at this step)
print "\n______________________ACAM aquisition start________________________\n"
# Enable channels and terminations of all channels
......
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
......@@ -56,7 +56,6 @@ import os
import math
from numpy import *
from ctypes import *
from pylab import *
from datetime import datetime
# Add common modules location tp path
......@@ -91,8 +90,8 @@ BOX_USB_DEVICE_ID = 0xea60 # CP210x Composite Device
def pendulum_output_on(meas):
meas.write("OUTP:TYPE PULS")
meas.write("SOUR:PULS:PER 0.001")
meas.write("SOUR:PULS:WIDT 0.0001")
meas.write("SOUR:PULS:PER 0.002")
meas.write("SOUR:PULS:WIDT 0.0002")
return (1)
def pendulum_output_off(meas):
......@@ -106,11 +105,11 @@ def pendulum_output_off(meas):
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc.bin'
FPGA_LOADER_PATH = '../../../../gnurabbit/user/fpga_loader'
CH_CALIBR_FILENAME = "ch_calibration_data.txt"
CH_CALIBR_FILENAME = "ch_calib_data.txt"
CH_CALIBR_FILENAME = os.path.join(default_directory, CH_CALIBR_FILENAME)
f_out = open(CH_CALIBR_FILENAME, 'w')
start_test_time = time.time()
......@@ -218,6 +217,9 @@ def main (default_directory='.'):
raise PtsError('CNT-91 is not switched on or badly connected, aborting.')
a = pendulum_output_off(meas)
# Enable channels and start timestamps aquisition (TDC_START_FPGA pulse sent at this step)
print "\n______________________ACAM aquisition start________________________\n"
# Enable channels and terminations of all channels
tdc.enable_channels()
tdc.channel_term(1, 1)
......@@ -226,8 +228,6 @@ def main (default_directory='.'):
tdc.channel_term(4, 1)
tdc.channel_term(5, 1)
# Enable timestamps aquisition (TDC_START_FPGA pulse sent at this step)
print "\n______________________ACAM aquisition start________________________\n"
tdc.start_acq()
print "\n-----------------------------------------------------------------\n\n\n"
......@@ -277,12 +277,6 @@ def main (default_directory='.'):
msg = ("ERROR: Unexpected error with interrupts; expected overflows: %d; received overflows: %d")%((NUM_OF_TSTAMPS*(i+1)),tdc_overflows_now)
print (msg)
raise PtsError (msg)
#timestamps, data = tdc.get_timestamps(0)
#for m in range(len(timestamps)):
# if (timestamps[m][2] == 1) and (timestamps[m][1] == 0): # rising tstamps ch1
# r_edge_timestamps_ch1.append(timestamps[m][0])
# elif (timestamps[m][2] == 1) and (timestamps[m][1] == otherch): # rising tstamps pair channel
# r_edge_timestamps_otherch.append(timestamps[m][0])
print "Ch1 tstamps : %d"%(len(r_edge_timestamps_ch1))
print "Ch%d tstamps : %d"%(i+2, len(r_edge_timestamps_otherch))
......@@ -303,7 +297,7 @@ def main (default_directory='.'):
# allign lists with rising-edge-timestamps for ch1 and the other channel
offset = 0
for l in range(10):
for l in range(100):
if (r_edge_timestamps_ch1[l] - r_edge_timestamps_otherch[0]) < 10000 and (r_edge_timestamps_ch1[l] - r_edge_timestamps_otherch[0]) > -10000:
offset= l
print "offset : %d"%(l)
......
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
......@@ -215,7 +215,7 @@ class CFMCTDC:
# Configures DAC and PLL
def configure_mezz_dac(self, dac_word):
print "Configuring mezzanine DAC 0x%4X"%dac_word
print "\nConfiguring mezzanine DAC 0x%4X"%dac_word
self.tdc_regs.wr_reg(0x98, dac_word) # default: xA8F5, max: xFFFF, min: x0000
self.tdc_regs.wr_reg(0xFC, 0x800)
time.sleep(2)
......
File mode changed from 100644 to 100755
......@@ -49,7 +49,7 @@ class CFMCTDC:
#GNUM_CSR_ADDR_DUMMY = 0x00000
# Carrier One Wire
#CARR_ONEWIRE_ADDR = 0x10000
CARR_ONEWIRE_ADDR = 0x10000
# Carrier CSR info
CARRIER_CSR_ADDR = 0x20000
......@@ -150,7 +150,7 @@ class CFMCTDC:
# Read bitstream type
def read_bitstream_type(self):
return self.carrier_csr.rd_reg(0x04)
return self.carrier_csr.rd_reg(0x00)
# Returns mezzanine unique ID
def mezz_get_unique_id(self):
......
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
......@@ -71,8 +71,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
# Add common modules location to path
......@@ -95,7 +93,6 @@ from find_usb_tty import *
import fmc_tdc_sdb
from numpy import *
from pylab import *
from ctypes import *
from fmc_eeprom import *
......@@ -148,8 +145,8 @@ def main (default_directory='.'):
sys.stdin = tmp_stdin;
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/spec-fmc-tdcDBG.bin'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/wrabbit_tdc.bin'
FPGA_LOADER_PATH = '../../../../gnurabbit/user/fpga_loader'
FAMILY_CODE = 0x28
WRABBIT_CLK_LOCK_MASK = 0x10
......@@ -193,7 +190,7 @@ def main (default_directory='.'):
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x2):
if(bitstream_type != 0x10003):
msg = ("FATAL ERROR: Wrong bitstream type loaded 0x%8X")%bitstream_type
os.close(spec.fd)
print (msg)
......
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
File mode changed from 100644 to 100755
......@@ -68,7 +68,7 @@ import fmc_tdc
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_presence.bit'#top_tdc.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......
......@@ -77,8 +77,8 @@ import fmc_tdc
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_clks.bit'#tdc_pts_presence.bit'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_clks.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
# Addressing for the retrieval of carrier csr information
......
......@@ -67,8 +67,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
......@@ -92,9 +90,9 @@ import fdelay_lib
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_input_pulse.bit'
FMC_DELAY_ADDR = '018d:0000/018d:0000@0002:0000'#'1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FMC_TDC_CHANNEL_NB = 5
......
......@@ -66,8 +66,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
......@@ -93,9 +91,9 @@ import fdelay_lib
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_input_pulse.bit'
FMC_DELAY_ADDR = '018d:0000/018d:0000@0002:0000'#'1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FMC_TDC_CHANNEL_NB = 5
......
......@@ -71,8 +71,8 @@ import fmc_tdc
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_counters.bit'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FAMILY_CODE = 0x28
......
......@@ -50,8 +50,6 @@
import sys
import time
import os
from binascii import unhexlify
import array
# Add common modules location tp path
sys.path.append('../../../')
......@@ -72,7 +70,7 @@ import fmc_tdc
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_counters.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
EEPROM_ADDR = 0x50
......@@ -154,72 +152,15 @@ def main (default_directory='.'):
raise PtsError (msg)
# Write, read back and compare
addr = 0x00
wr_data2 = [0x55, 0xAA, 0x00, 0xFF]
byte_to_write = (wr_data2[0])
print byte_to_write
print("0x%08X") %byte_to_write
print wr_data2
wr_data_float = [-15324.48, 43631.41, 34323.48, 26359.30]
wr_data_int = []
for k in range(0,len(wr_data_float),1):
print ("ch%d float: %20.2f fs")%(k+2, wr_data_float[k])
wr_data_int.append(int(wr_data_float[k]))
print ("ch%d int: %20d fs")%(k+2, wr_data_int[k])
print wr_data_int
wr_data_hex = []
for k in range(0,len(wr_data_int),1):
hex_value = (wr_data_int[k] & 0xffffffff)#hex (wr_data_int[k] & 0xffffffff)[:-1]#
wr_data_hex.append(hex_value)
print wr_data_hex
byte_to_write = (wr_data_hex[0])
print byte_to_write
print("0x%08X") %byte_to_write
if byte_to_write == 0xFFFFc424:
print("OK!!")
else:
print("notOK!")
byte_to_write_hex = hex(byte_to_write)
print byte_to_write_hex
wr_data = []
bytes = array.array('B', byte_to_write_hex.decode("hex"))
for i in range(0,len(bytes),1):
print result[i]
wr_data.append(bytes[i])
print wr_data
#wr_data = [0x55, 0xAA, 0x00, 0xFF]
#wr_data = [0xffffc424, 0xAA, 0x00, 0xFF]
#wr_data = [0xFF, 0xFF, 0xC4, 0x24]#ffffc424]#, 0xaa6f]#, 0x8613, 0x66f7]
addr = 0x2000
wr_data = [0x55, 0xAA, 0x00, 0xFF]
rd_data = []
print('EEPROM IC5: Writting data at EEPROM address 0x%.2X: ')%addr,
print wr_data
tdc.mezz_i2c_eeprom_write(addr, wr_data)
time.sleep(0.1)
tdc.mezz_i2c_eeprom_write(addr, wr_data)
time.sleep(0.1)
print('EEPROM IC5: Reading data from EEPROM address 0x%.2X:')%addr,
rd_data = tdc.mezz_i2c_eeprom_read(0x01, 4)#len(wr_data))
rd_data = tdc.mezz_i2c_eeprom_read(addr, len(wr_data))
print rd_data
if(rd_data != wr_data):
msg = ("ERROR: EEPROM IC5: Data reading/ writing failed")
......@@ -230,9 +171,7 @@ def main (default_directory='.'):
print('\nEEPROM IC5: Data comparison OK')
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
main()
......@@ -47,8 +47,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
# Add common modules location tp path
......@@ -72,7 +70,7 @@ import fmc_tdc
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......
......@@ -48,8 +48,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
# Add common modules location tp path
......@@ -75,9 +73,9 @@ import fdelay_lib
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_pllstatus.bit
FMC_DELAY_ADDR = '018d:0000/018d:0000@0002:0000'#'1a39:0004/1a39:0004@0005:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FMC_TDC_CHANNEL_NB = 5
......
......@@ -54,8 +54,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
# Add common modules location tp path
......@@ -81,9 +79,9 @@ import fdelay_lib
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_pllstatus.bit
FMC_DELAY_ADDR = '018d:0000/018d:0000@0002:0000'#'1a39:0004/1a39:0004@0005:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FMC_TDC_CHANNEL_NB = 5
......
......@@ -48,8 +48,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
# Add common modules location tp path
......@@ -75,9 +73,9 @@ import fdelay_lib
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_pllstatus.bit
FMC_DELAY_ADDR = '018d:0000/018d:0000@0002:0000'#'1a39:0004/1a39:0004@0005:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......
......@@ -53,8 +53,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
......@@ -82,9 +80,9 @@ import fdelay_lib
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_fpga_in.bit'
FMC_DELAY_ADDR = '018d:0000/018d:0000@0002:0000'#'1a39:0004/1a39:0004@0005:0000'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......
......@@ -48,8 +48,6 @@ import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
......@@ -66,7 +64,7 @@ import csr