Commit c665e3a9 authored by Evangelia Gousiou's avatar Evangelia Gousiou

rewrote all the functionality tests so as to make use of the pendulum rather…

rewrote all the functionality tests so as to make use of the pendulum rather than a Fine Delay board; like this the setup for the functionality and the calibration tests is the same
parent 58136c35
......@@ -5,10 +5,20 @@
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
LOGDIR=./log_fmctdc1ns5cha
sudo rmmod cp210x
cd ~/fmc-tdc-1ns-5cha-tst/pts
sudo insmod ./cp210x-driver/cp210x.ko
cd usbdriver
sudo ./usbtmc_load
cd ..
cd ~/fmc-tdc-1ns-5cha-tst/pts
LOGDIR=../logs/log_fmctdc1ns5cha
mkdir -p $LOGDIR
sudo rm -fr $LOGDIR/pts*
sudo rm -fr $LOGDIR/fmc-tdc-1ns-5cha-tst*
serial=$1
if [ x$1 = x"" ]; then
......@@ -47,7 +57,18 @@ do
echo "Test series run $nb_test out of $nb_test_limit"
echo " "
sudo ./pts.py -b FmcTdc1ns5cha -s $serial -e $extra_serial -t./test/fmctdc1ns5cha/python -l $LOGDIR 00 01 02 03 04 05 06 07 08 09 10 11 12
echo "--- Functionality tests ---"
sudo ./pts.py -b FmcTdc1ns5cha_funct -s $serial -e $extra_serial -t ../test/fmctdc1ns5cha/functionality/python -l $LOGDIR 00 #01 02 03 04 05 06 07 08 09 10 11 12
echo -n "Do you wish to continue with the calibration tests [y,n]? "
read reply
if [ "$reply" = "y" ]
then
echo "--- Calibration tests ---\n"
LOGDIR=../logs/log_fmctdc1ns5cha_calib
sudo ./pts.py -b FmcTdc1ns5cha_calib -s $serial -e $extra_serial -t ../test/fmctdc1ns5cha/calibration/python -l $LOGDIR 16 17 18 #13 14 15 16 17 18
fi
if [ "$nb_test" != "$nb_test_limit" ]
then
......
......@@ -56,7 +56,8 @@ do
echo "Test series run $nb_test out of $nb_test_limit"
echo " "
sudo ./pts.py -b FmcTdc1ns5cha -s $serial -e $extra_serial -t ../test/fmctdc1ns5cha/calibration/python -l $LOGDIR 00 01 02 03
echo "--- Calibration tests ---"
sudo ./pts.py -b FmcTdc1ns5cha_calib -s $serial -e $extra_serial -t ../test/fmctdc1ns5cha/calibration/python -l $LOGDIR 13 14 15 16 17 18
if [ "$nb_test" != "$nb_test_limit" ]
then
......
#!/bin/sh
# Copyright CERN, 2011
# Author: Evangelia Gousiou <egousiou@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
sudo rmmod cp210x
cd ~/pts_cleanup
sudo insmod ./cp210x-driver/cp210x.ko
cd usbdriver
sudo ./usbtmc_load
cd ..
LOGDIR=./log_fmctdc1ns5cha_wrcalib
mkdir -p $LOGDIR
sudo rm -fr $LOGDIR/pts*
serial=$1
if [ x$1 = x"" ]; then
echo -n "Please scan CERN serial number bar-code, then press [ENTER]: "
read serial
fi
if [ x$serial = x"" ]; then
serial=0000
fi
if [ -e serial.txt ]; then
sudo rm -f serial.txt
fi
echo $serial >> serial.txt
extra_serial=$2
if [ x$2 = x"" ]; then
echo -n "If needed input extra serial number and press [ENTER] OR just press [ENTER]: "
read extra_serial
fi
if [ x$extra_serial = x"" ]; then
extra_serial=0000
fi
echo " "
nb_test_limit=2
nb_test=1
while [ "$nb_test" -le "$nb_test_limit" ]
do
echo "--------------------------------------------------------------"
echo "Test series run $nb_test out of $nb_test_limit"
echo " "
sudo ./pts.py -b FmcTdc1ns5cha -s $serial -e $extra_serial -t./test/fmctdc1ns5cha/calibration/python -l $LOGDIR 00 01 02 03 04 05
if [ "$nb_test" != "$nb_test_limit" ]
then
echo " "
echo -n "Do you want to run the test series again [y,n]? "
read reply
if [ "$reply" != "y" ]
then
break
fi
fi
nb_test=$(($nb_test+1))
done
echo "--------------------------------------------------------------"
echo " "
echo -n "End of the test, do you want to switch the computer OFF? [y,n]"
read reply
if [ "$reply" = "y" ]
then
sudo poweroff
fi
......@@ -13,7 +13,7 @@ class CCP210x:
self.fd = open(device, 'wb')
def gpio_set(self, mask):
print("gpio_set %x" % mask),
#print("gpio_set %x" % mask),
f = array.array('L', [0])
f[0] = (mask << 8) | 0xff;
fcntl.ioctl(self.fd, 0x8001, f, 0)
......
......@@ -109,7 +109,7 @@ BOX_USB_DEVICE_ID = 0xea60 # CP210x Composite Device
TEMPID_FAMILY_CODE = 0x28
TEMP_THRES = 46.0
TEMP_THRES = 43.0
TEMP_RIPPLE = 0.3
FIFO_SIZE = 20
MEAS_SLEEP = 1
......
......@@ -58,7 +58,7 @@ from numpy import *
from ctypes import *
from datetime import datetime
# Add common modules location tp path
# Add common modules location to path
sys.path.append('../../../../pts/')
sys.path.append('../../../../pts/gnurabbit/python/')
sys.path.append('../../../../pts/common/')
......
#! /bin/bash
ln -s ch_calib.py test00.py
ln -s DAC_calib.py test01.py
ln -s write_eeprom.py test02.py
ln -s verify_calib.py test03.py
ln -s wrabbit_calib.py test04.py
ln -s wrabbit_write_eeprom.py test05.py
ln -s ch_calib.py test13.py
ln -s DAC_calib.py test14.py
ln -s write_eeprom.py test15.py
ln -s verify_calib.py test16.py
ln -s wrabbit_calib.py test17.py
ln -s wrabbit_write_eeprom.py test18.py
#! /bin/bash
rm -f test00.py
rm -f test01.py
rm -f test02.py
rm -f test03.py
rm -f test04.py
rm -f test05.py
rm -f test13.py
rm -f test14.py
rm -f test15.py
rm -f test16.py
rm -f test18.py
rm -f test18.py
rm -f test*.pyc
\ No newline at end of file
rm -f test*.pyc
rm -f test*.py~
......@@ -74,12 +74,12 @@ import math
from datetime import datetime
# Add common modules location to path
sys.path.append('../../../../')
sys.path.append('../../../../gnurabbit/python/')
sys.path.append('../../../../common/')
sys.path.append('../../../../common/cp210x')
sys.path.append('../../../../common/usb_box')
sys.path.append('../../../fmceeprom/python/')
sys.path.append('../../../../pts/')
sys.path.append('../../../../pts/gnurabbit/python/')
sys.path.append('../../../../pts/common/')
sys.path.append('../../../../pts/common/fmceeprom/python')
sys.path.append('../../../../pts/common/usb_box')
sys.path.append('../../../../pts/common/cp210x')
# Import common modules
......@@ -147,7 +147,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/wrabbit_tdc.bin'
FPGA_LOADER_PATH = '../../../../gnurabbit/user/fpga_loader'
FPGA_LOADER_PATH = '../../../../pts/gnurabbit/user/fpga_loader'
FAMILY_CODE = 0x28
WRABBIT_CLK_LOCK_MASK = 0x10
WRABBIT_CALIB_FILENAME = "wrabbit_calib_data.txt"
......
......@@ -58,10 +58,12 @@ import os
import numpy as np
# Add common modules and libraries location to path
sys.path.append('../../../../')
sys.path.append('../../../../gnurabbit/python/')
sys.path.append('../../../../common/')
sys.path.append('../../../fmceeprom/python/')
sys.path.append('../../../../pts/')
sys.path.append('../../../../pts/gnurabbit/python/')
sys.path.append('../../../../pts/common/')
sys.path.append('../../../../pts/common/fmceeprom/python')
sys.path.append('../../../../pts/common/usb_box')
sys.path.append('../../../../pts/common/cp210x')
# Import common modules
from ptsexcept import *
......@@ -106,9 +108,9 @@ def main (default_directory='.'):
start_test_time = time.time()
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@0001:0000'#'1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc.bin'#spec-fmc-tdcDBG.bin'
FPGA_LOADER_PATH = '../../../../gnurabbit/user/fpga_loader'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc.bin'
FPGA_LOADER_PATH = '../../../../pts/gnurabbit/user/fpga_loader'
# SPEC object declaration
spec = rr.Gennum()
......
......@@ -15,11 +15,11 @@
## |
## Description Testing of the communication with the ACAM chip IC8 of the TDC board. |
## The test configures the ACAM chip and then checks the status of all its registers.|
## In detal these lines are tested: TDC_D[27..0], TDC_ADR[3..0], RESET_N, TDC_WRN, |
## In detail these lines are tested: TDC_D[27..0], TDC_ADR[3..0], RESET_N, TDC_WRN, |
## TDC_RDN, TDC_CSN, TDC_OEN |
## |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -50,16 +50,14 @@ import math
from datetime import datetime
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
sys.path.append('../../../../pts/')
sys.path.append('../../../../pts/gnurabbit/python/')
sys.path.append('../../../../pts/common/')
# Import common modules
from ptsexcept import *
import rr
import csr
# Import specific modules
import fmc_tdc
......@@ -69,11 +67,16 @@ import fmc_tdc
def main (default_directory='.'):
start_test_time = time.time()
#-----> PCIe address, firmware, loader constants
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FPGA_LOADER_PATH = '../../../../pts/gnurabbit/user/fpga_loader'
#-----> FPGA initializations
# SPEC object declaration
spec = rr.Gennum()
......@@ -81,8 +84,9 @@ def main (default_directory='.'):
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "-------------------- ACAM IC8 communication test ------------------\n"
print ("Testing of the communication with the ACAM chip IC8."
" The test\nconfigures the ACAM and then checks the status of its registers.\n")
print ("Testing of the communication with the ACAM chip IC8.\n"
"The test configures the ACAM and then checks the status of all\n"
"its registers.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
......@@ -121,6 +125,8 @@ def main (default_directory='.'):
else:
print('Access to TDC core OK')
#-----> TDC configuration
# TDC configuration
print "\n__________________________Configuration__________________________\n"
tdc.config_acam()
......@@ -152,8 +158,10 @@ def main (default_directory='.'):
print (msg)
raise PtsError (msg)
os.close(spec.fd)
print "\n-----------------------------------------------------------------\n\n\n"
print "\n\n--------------------------------"
end_test_time = time.time()
print "Test elapsed time: %.2f seconds\n\n\n" % (end_test_time-start_test_time)
if __name__ == '__main__' :
......
......@@ -60,27 +60,28 @@ import os
import math
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
sys.path.append('../../../../pts/')
sys.path.append('../../../../pts/gnurabbit/python/')
sys.path.append('../../../../pts/common/')
# Import common modules
from ptsexcept import *
import rr
import csr
# Import specific modules
import fmc_tdc
def main (default_directory='.'):
# Constants declaration
start_test_time = time.time()
#-----> PCIe address, firmware, loader constants
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_clks.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FPGA_LOADER_PATH = '../../../../pts/gnurabbit/user/fpga_loader'
#-----> FPGA constants
# Addressing for the retrieval of carrier csr information
CARRIER_CSR = 0x00000 # base address
CSR_TYPE_VER = 0x00
......@@ -98,7 +99,9 @@ def main (default_directory='.'):
EN_COUNTERS = 0x28
CLK_31M25_COUNTER = 0x2C
CLK_125M_COUNTER = 0x3C
#-----> FPGA initializations
# SPEC object declaration
spec = rr.Gennum()
......@@ -107,8 +110,9 @@ def main (default_directory='.'):
print "----------------------------- FMC TDC -----------------------------"
print "--------------------------- Clocks test ---------------------------\n"
print ("Test of the PLL clocks: 31.25MHz FPGA_TDC_REF_CLK and 125MHz CLK125.\n"
"The test starts by configuring the PLL IC4. Then, to verify the clock\n"
"frequencies, there are dedicated counters implemented in the carrier FPGA.\n")
"The test starts by configuring the PLL IC4. Then, to verify the\n"
"clock frequencies, there are dedicated counters implemented in the\n"
"carrier FPGA.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
......@@ -165,9 +169,9 @@ def main (default_directory='.'):
else:
print("Mezzanine present : OK")
time.sleep(3)
#-----> Check the clocks
print "\n\n___________________________PLL status____________________________\n"
pll_status = carrier_csr.rd_reg(PLL_STATUS)
if pll_status == 1:
......@@ -189,7 +193,7 @@ def main (default_directory='.'):
clk_125M = ((carrier_csr.rd_reg(CLK_125M_COUNTER))/ (2*1e6))
# FPGA_TDC_REF_CLK 31.25MHz clock evaluation
if (clk_31M25 > 32.8) or (clk_31M25 < 29.6): # 5% limits due to software inacuracies
if (clk_31M25 > 32.8) or (clk_31M25 < 29.6): # 5% limits due to software inaccuracies
msg = (("ERROR: PLL IC4: FPGA_TDC_REF_CLK: measured frequency %.2f MHz is out of accepted limits [29.6MHz..32.8MHz]") % (clk_31M25))
os.close(spec.fd)
print (msg)
......@@ -198,7 +202,7 @@ def main (default_directory='.'):
print("FPGA_TDC_REF_CLK: measured frequency: %.2f MHz OK") % (clk_31M25)
# CLK125 125MHz clock evaluation
if (clk_125M > 131) or (clk_125M < 118): # 5% limits due to software inacuracies in time measurement (time.sleep(2))
if (clk_125M > 131) or (clk_125M < 118): # 5% limits due to software inaccuracies in time measurement (time.sleep(2))
msg = (("ERROR: PLL IC4: CLK125: measured frequency %.2f MHz is out of accepted limits [118MHz..131MHz]") % (clk_125M))
os.close(spec.fd)
print (msg)
......@@ -207,8 +211,9 @@ def main (default_directory='.'):
print("CLK125: measured frequency: %.2f MHz OK") % (clk_125M)
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
print "\n\n--------------------------------"
end_test_time = time.time()
print "Test elapsed time: %.2f seconds\n\n\n" % (end_test_time-start_test_time)
if __name__ == '__main__' :
main()
......@@ -23,7 +23,7 @@
## |
## The test attempts several writings and readbacks on different EEPROM locations. |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -51,30 +51,36 @@ import sys
import time
import os
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Add common modules location to path
sys.path.append('../../../../pts/')
sys.path.append('../../../../pts/gnurabbit/python/')
sys.path.append('../../../../pts/common/')
# Import common modules
from ptsexcept import *
import rr
# Import specific modules
import fmc_tdc
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main (default_directory='.'):
start_test_time = time.time()
#-----> PCIe address, firmware, loader constants
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_counters.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FPGA_LOADER_PATH = '../../../../pts/gnurabbit/user/fpga_loader'
#-----> EEPROM chip constant
EEPROM_ADDR = 0x50
#-----> FPGA initializations
# SPEC object declaration
spec = rr.Gennum()
......@@ -92,7 +98,7 @@ def main (default_directory='.'):
# Load FMC TDC firmware
print "\n_________________________Initialisations_________________________\n"
print "Loading FMC Fine Delay firmware...",
print "Loading FMC TDC firmware...",
firmware_loader = os.path.join(default_directory, FPGA_LOADER_PATH)
bitstream = os.path.join(default_directory, FMC_TDC_BITSTREAM_PATH)
os.system(firmware_loader + ' ' + bitstream)
......@@ -121,6 +127,8 @@ def main (default_directory='.'):
else:
print('Access to TDC core OK')
#-----> Accessing the mezzanine EEPROM chip
print "\n__________________________EEPROM IC10 test_______________________\n"
# Scan FMC I2C bus
try:
......@@ -170,8 +178,10 @@ def main (default_directory='.'):
else:
print('\nEEPROM IC5: Data comparison OK')
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
print "\n\n--------------------------------"
end_test_time = time.time()
print "Test elapsed time: %.2f seconds\n\n\n" % (end_test_time-start_test_time)
if __name__ == '__main__' :
main()
......@@ -16,13 +16,13 @@
## Description Testing of the presence of the TDC board on the SPEC carrier. |
## |
## The test retrieves information on the carrier board: pcb version, carrier type, |
## status, control, mezzzanine presence. |
## status, control, mezzanine presence. |
## Note that the mezzanine presence flag comes from the FMC pin prsnt_m2c_n_i. |
## |
## The WISHBONE master can be accessed at PCIe base address xC0000. |
## |
## |
## FW to load .bin |
## FW to load tdc_pts_presence.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -52,26 +52,27 @@ import time
import os
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
sys.path.append('../../../../pts/')
sys.path.append('../../../../pts/gnurabbit/python/')
sys.path.append('../../../../pts/common/')
# Import common modules
from ptsexcept import *
import rr
import csr
# Import specific modules
import fmc_tdc
def main (default_directory='.'):
# Constants declaration
start_test_time = time.time()
#-----> PCIe address, firmware, loader constants
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_presence.bit'#top_tdc.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_presence.bit'
FPGA_LOADER_PATH = '../../../../pts/gnurabbit/user/fpga_loader'
#-----> FPGA constants
# Addressing for the retrieval of carrier csr information
CARRIER_CSR = 0x00000 # base address
CSR_TYPE_VER = 0x00
......@@ -82,14 +83,16 @@ def main (default_directory='.'):
PCB_VER_MASK = 0x000F
CARRIER_TYPE_MASK = 0xFFFF0000
STATUS_FMC_PRES = (1<<0)
#-----> FPGA initializations
# SPEC object declaration
spec = rr.Gennum()
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "---------------------------- FMC TDC ---------------------------- "
print "-------------------- Mezzanine presence test --------------------\n"
print "----------------------------- FMC TDC ----------------------------- "
print "--------------------- Mezzanine presence test ---------------------\n"
print ("Test of the presence of the mezzanine, on the SPEC carrier.\n")
print "\n_______________________________Info______________________________\n"
......@@ -113,7 +116,7 @@ def main (default_directory='.'):
# Check bitsteam type
bitstream_type = carrier_csr.rd_reg(CSR_BSTM_TYPE)
print('Bitstream type :%.8X') % bitstream_type
print('Bitstream type : %.8X') % bitstream_type
if(bitstream_type == 0xFFFFFFFF):
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
......@@ -148,8 +151,10 @@ def main (default_directory='.'):
else:
print("Mezzanine present OK\n")
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
print "\n\n--------------------------------"
end_test_time = time.time()
print "Test elapsed time: %.2f seconds\n\n\n" % (end_test_time-start_test_time)
if __name__ == '__main__' :
main()
......@@ -60,7 +60,7 @@ class CFMCTDC:
# ACAM register addresses and expected register contents
ACAM_READBACK_ADDR = [0x40, 0x44, 0x48, 0x4C, 0X50, 0x54, 0x58, 0x5C, 0x60, 0x64, 0x68, 0x6C, 0x70, 0x78]
ACAM_READBACK_REGS = [0xC1F0FC81, 0xC0000000, 0xC0000E02, 0xC0000000, 0xC200000F, 0xC00007D0, 0xC00000FC, 0xC0001FEA, 0x00000000, 0x00000000, 0x00000000, 0xC3000000, 0xC4000800, 0xC0000000]
ACAM_READBACK_REGS = [0xC1F0FC81, 0xC0000000, 0xC0000E02, 0xC0000000, 0xC200000F, 0xC00007D0, 0xC00000FC, 0xC0001FEA, 0x00000000, 0x00000000, 0x00000000, 0xC01F0000, 0xC4000800, 0xC0000000]
# DMA length in bytes
DMA_LENGTH = 4096
......@@ -175,8 +175,8 @@ class CFMCTDC:
self.tdc_regs.wr_reg(0x14, 0x7D0)
self.tdc_regs.wr_reg(0x18, 0x3)
self.tdc_regs.wr_reg(0x1C, 0x1FEA)
#self.tdc_regs.wr_reg(0x2C, 0xFF0000)
self.tdc_regs.wr_reg(0x2C, 0x03000000)
self.tdc_regs.wr_reg(0x2C, 0x1F0000)
#self.tdc_regs.wr_reg(0x2C, 0x03000000)
self.tdc_regs.wr_reg(0x30, 0x4000000)
self.tdc_regs.wr_reg(0x38, 0x0)
self.tdc_regs.wr_reg(0xFC, 0x4)
......
This diff is collapsed.
......@@ -21,7 +21,7 @@
## if all the LEDs are blinking as expected. |
## |
## |
## FW to load .bin |
## FW to load tdc_pts_leds.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -49,11 +49,13 @@
import sys
import time
import os
import math
from datetime import datetime
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
sys.path.append('../../../../pts/')
sys.path.append('../../../../pts/gnurabbit/python/')
sys.path.append('../../../../pts/common/')
# Import common modules
from ptsexcept import *
......@@ -61,24 +63,27 @@ import rr
import csr
def main (default_directory='.'):
start_test_time = time.time()
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_leds.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FPGA_LOADER_PATH = '../../../../pts/gnurabbit/user/fpga_loader'
print "\n-------------------------------------------------------------------"
print "----------------------------- TDC PTS -----------------------------"
print "---------------------------- LEDs test ----------------------------\n"
print ("Test of the front panel LEDs. For this test the operator’s intervention\n"
"is needed; when prompted, the operator should visually inspect the LEDs.\n")
print ("Test of the front panel LEDs. For this test the operator’s\n"
"intervention is needed; when prompted, the operator should visually\n"
"inspect the LEDs.\n")