SFpga.syr 90.4 KB
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Release 12.3 - xst M.70d (nt64)
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Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
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--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
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--> Reading design: SFpga.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "SFpga.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "SFpga"
Output Format                      : NGC
Target Device                      : xc6slx150t-3-fgg676

---- Source Options
Top Module Name                    : SFpga
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/VmeInterfaceWB.v\" into library work
Parsing module <VmeInterfaceWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SpiMasterWB.v\" into library work
Parsing module <SpiMasterWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Slv2SerWB.v\" into library work
Parsing module <Slv2SerWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Monostable.v\" into library work
Parsing module <Monostable>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/InterruptManagerWB.v\" into library work
Parsing module <InterruptManagerWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Generic4OutputRegs.v\" into library work
Parsing module <Generic4OutputRegs>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Generic4InputRegs.v\" into library work
Parsing module <Generic4InputRegs>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Debouncer.v\" into library work
Parsing module <Debouncer>.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Debouncer.v" Line 14: Macro <dly> is redefined.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Debouncer.v" Line 21: Macro <s_Idle> is redefined.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/AddrDecoderWBSys.v\" into library work
Parsing module <AddressDecoderWBSys>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v\" into library work
Parsing module <SystemFpga>.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro <dly> is redefined.
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WARNING:HDLCompiler:224 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to input AFpgaProgDone_io
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Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v\" into library work
Parsing module <SFpga>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <SFpga>.
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WARNING:HDLCompiler:1016 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 507: Port osc_clk is not connected to this instance
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Elaborating module <SystemFpga>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 325: Assignment to DdrLDQS_io ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 326: Assignment to DdrUDQS_io ignored, since the identifier is never used

Elaborating module <Monostable>.

Elaborating module <Debouncer(g_CounterWidth=16,g_SynchDepth=3)>.

Elaborating module <VmeInterfaceWB>.

Elaborating module <InterruptManagerWB>.

Elaborating module <AddressDecoderWBSys>.

Elaborating module <Generic4OutputRegs(Reg2Default=32'b01000100010001000)>.
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WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 568: Assignment to GenericOutputReg3 ignored, since the identifier is never used
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Elaborating module <Generic4InputRegs>.

Elaborating module <Slv2SerWB>.
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WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to AFpgaProgDone_io ignored, since the identifier is never used
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Elaborating module <SpiMasterWB>.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net <GenericInputReg1[31]> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 273: Net <SpiMiSo_b32[30]> does not have a driver.
WARNING:HDLCompiler:189 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Size mismatch in connection of port <VmeDs_inb2>. Formal port size is 2-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 439: Assignment to WRGBitOut_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 442: Assignment to Sfp2GBitOut_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 444: Assignment to SataTx_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 446: Assignment to Gbit1Sys2App_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 448: Assignment to Gbit2Sys2App_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 451: Assignment to Gbit3Sys2App_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 453: Assignment to Gbit4Sys2App_o ignored, since the identifier is never used

Elaborating module <IBUFGDS(DIFF_TERM="TRUE",IOSTANDARD="DEFAULT")>.

Elaborating module <OBUFDS(IOSTANDARD="DEFAULT")>.

Elaborating module <IOBUFDS(IOSTANDARD="DEFAULT")>.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Net <VmeDs_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 440: Net <WRGbitIn_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 441: Net <WRRefClk_ik> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 443: Net <Sfp2GbitIn_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 445: Net <SataRx_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 447: Net <Gbit1App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 449: Net <Gbit2App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 450: Net <Gbit12RefClk_ik> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 452: Net <Gbit3App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 454: Net <Gbit4App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 455: Net <Gbit34RefClk_ik> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <SFpga>.
    Related source file is "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v".
WARNING:Xst:647 - Input <VmeDs_inb2<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <WRGBitOut_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Sfp2GBitOut_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <SataTx_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit1Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit2Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit3Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit4Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <VmeDs_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WRGbitIn_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WRRefClk_ik> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Sfp2GbitIn_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <SataRx_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit1App2Sys_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit2App2Sys_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit12RefClk_ik> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit3App2Sys_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit4App2Sys_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit34RefClk_ik> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <SFpga> synthesized.

Synthesizing Unit <SystemFpga>.
    Related source file is "/vfc_svn/hdl/design/systemfpga.v".
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WARNING:Xst:647 - Input <Switch_ib2<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <PcbRev_ib8<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTck_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTrst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTdi_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTms_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <AFpgaProgDone_io> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <PllFmc12SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllFmc22SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllSys2SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllDds2SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllDacDout_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsSyncSmpErr_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsPllLock_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsSDo_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsRamSwpOvr_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsDrOver_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsSyncClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsPdClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsSyncOut_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeP0LvdsBunchClkIn_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeP0LvdsTClkIn_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdrLDQS_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdrUDQS_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRModeDef0_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRTxFault_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRLoS_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sfp2ModeDef0_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sfp2LoS_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sfp2TxFault_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Fmc1PrsntM2C_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Fmc2PrsntM2C_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRGbitIn_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRRefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sfp2GbitIn_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SataRx_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit1App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit2App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit12RefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit3App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit4App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit34RefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 507: Output port <osc_clk> of the instance <i_InterruptManager> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 555: Output port <Reg3Value_ob32> of the instance <i_Generic4OutputRegs> is unconnected or connected to loadless signal.
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WARNING:Xst:653 - Signal <GenericInputReg1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <SpiMiSo_b32<30:9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WRGBitOut_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Sfp2GBitOut_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <SataTx_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit1Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit2Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit3Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
280 281
    Found 24-bit register for signal <VcTcXoDivider_c>.
    Found 24-bit register for signal <VmeSysClkDivider_c>.
282
    Found 1-bit register for signal <WriteCycle>.
283 284
    Found 2-bit register for signal <VmeSysReset_dx>.
    Found 1-bit register for signal <Rst_rq>.
285
    Found 24-bit register for signal <Si57xDivider_c>.
286 287 288
    Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_7_OUT> created at line 376.
    Found 24-bit adder for signal <VcTcXoDivider_c[23]_GND_2_o_add_10_OUT> created at line 379.
    Found 24-bit adder for signal <VmeSysClkDivider_c[23]_GND_2_o_add_13_OUT> created at line 382.
289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310
    Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 296
    Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 300
    Found 1-bit tristate buffer for signal <Fmc1SDa_io> created at line 305
    Found 1-bit tristate buffer for signal <Fmc2SDa_io> created at line 307
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<15>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<14>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<13>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<12>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<11>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<10>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<9>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<8>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<7>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<6>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<5>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<4>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<3>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<2>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<1>> created at line 315
    Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315
    Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338
    Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347
311 312 313 314 315 316 317 318 319 320
    Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 408
    Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 409
    Found 1-bit tristate buffer for signal <FpLed_onb8<2>> created at line 410
    Found 1-bit tristate buffer for signal <FpLed_onb8<3>> created at line 411
    Found 1-bit tristate buffer for signal <FpLed_onb8<4>> created at line 412
    Found 1-bit tristate buffer for signal <FpLed_onb8<5>> created at line 413
    Found 1-bit tristate buffer for signal <FpLed_onb8<6>> created at line 414
    Found 1-bit tristate buffer for signal <FpLed_onb8<7>> created at line 418
    Found 1-bit tristate buffer for signal <AFpgaProgProgram_o> created at line 609
    Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 656
321 322
    Summary:
	inferred   3 Adder/Subtractor(s).
323 324
	inferred  76 D-type flip-flop(s).
	inferred  32 Tristate(s).
325 326 327 328
Unit <SystemFpga> synthesized.

Synthesizing Unit <Monostable>.
    Related source file is "/vfc_svn/hdl/design/monostable.v".
329
        g_CounterBits = 23
330
    Found 4-bit register for signal <AsynchInAX_db4>.
331
    Found 23-bit register for signal <Counter_c>.
332 333
    Found 1-bit register for signal <SynchOutput_oq>.
    Found 1-bit register for signal <AsynchIn_ax>.
334
    Found 23-bit adder for signal <Counter_c[22]_GND_25_o_add_6_OUT> created at line 20.
335 336
    Summary:
	inferred   1 Adder/Subtractor(s).
337
	inferred  29 D-type flip-flop(s).
338 339 340 341 342 343 344 345 346 347
Unit <Monostable> synthesized.

Synthesizing Unit <Debouncer>.
    Related source file is "/vfc_svn/hdl/design/debouncer.v".
        g_CounterWidth = 16
        g_SynchDepth = 3
    Found 1-bit register for signal <State_q>.
    Found 16-bit register for signal <Counter_c>.
    Found 1-bit register for signal <DebouncedSignal_oq>.
    Found 3-bit register for signal <BouncingSignal_x>.
348
    Found 16-bit adder for signal <Counter_c[15]_GND_34_o_add_7_OUT> created at line 38.
349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397
    Found 1-bit comparator equal for signal <n0003> created at line 31
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  21 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <Debouncer> synthesized.

Synthesizing Unit <VmeInterfaceWB>.
    Related source file is "/vfc_svn/hdl/design/vmeinterfacewb.v".
        dly = 1
        s_idle = 3'b000
        s_read = 3'b001
        s_write = 3'b010
        s_ack_int = 3'b011
    Found 1-bit register for signal <ack_d>.
    Found 1-bit register for signal <stb_d>.
    Found 9-bit register for signal <AckTimeout_c>.
    Found 32-bit register for signal <DataReg>.
    Found 2-bit register for signal <as_shr>.
    Found 2-bit register for signal <ds1_shr>.
    Found 2-bit register for signal <ds2_shr>.
    Found 7-bit register for signal <vme_irqn>.
    Found 3-bit register for signal <state>.
    Found 1-bit register for signal <oe_vme_data>.
    Found 1-bit register for signal <vme_dtack>.
    Found 1-bit register for signal <vme_iack_outn>.
    Found 1-bit register for signal <clear_int>.
    Found 1-bit register for signal <VmeDOe_o>.
    Found 1-bit register for signal <VmeDDirFpgaToVme_o>.
    Found 1-bit register for signal <SendIrqVector>.
    Found 22-bit register for signal <adr_o>.
    Found 32-bit register for signal <dat_o>.
    Found 1-bit register for signal <we_o>.
    Found 1-bit register for signal <stb_o>.
    Found 1-bit register for signal <cyc_o>.
    Found 8-bit register for signal <VmeBaseAddr>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 50                                             |
    | Inputs             | 12                                             |
    | Outputs            | 6                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_i (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
398 399 400
    Found 9-bit adder for signal <AckTimeout_c[8]_GND_35_o_add_16_OUT> created at line 100.
    Found 22-bit adder for signal <adr_o[21]_GND_35_o_add_48_OUT> created at line 200.
    Found 1-bit 4-to-1 multiplexer for signal <_n0284> created at line 148.
401
    Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148.
402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433
    Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<29>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<28>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<27>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<26>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<25>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<24>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<23>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<22>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<21>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<20>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<19>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<18>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<17>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<16>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<15>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<14>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<13>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<12>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<11>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<10>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<9>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<8>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<7>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<6>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<5>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<4>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<3>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<2>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<1>> created at line 110
    Found 1-bit tristate buffer for signal <vme_data<0>> created at line 110
434
    Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_35_o_equal_12_o> created at line 75
435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465
    Found 3-bit comparator equal for signal <vme_addr[3]_intlev_reg[2]_equal_43_o> created at line 178
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 128 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  28 Multiplexer(s).
	inferred  32 Tristate(s).
	inferred   1 Finite State Machine(s).
Unit <VmeInterfaceWB> synthesized.

Synthesizing Unit <InterruptManagerWB>.
    Related source file is "/vfc_svn/hdl/design/interruptmanagerwb.v".
        dly = 1
        int_reg_addr = 2'b00
        mask_reg_addr = 2'b01
        fpga_status_reg_addr = 2'b10
        new_int_mode_addr = 2'b11
WARNING:Xst:647 - Input <Dat_ib32<30:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 8x8-bit dual-port RAM <Mram_int_fifo> for signal <int_fifo>.
    Found 8-bit register for signal <mask_reg>.
    Found 1-bit register for signal <rora_roak>.
    Found 1-bit register for signal <ready4int>.
    Found 1-bit register for signal <hs_int_mode>.
    Found 8-bit register for signal <int_masked_old>.
    Found 4-bit register for signal <int_counter>.
    Found 3-bit register for signal <int_pointer_r>.
    Found 3-bit register for signal <int_pointer_w>.
    Found 1-bit register for signal <fifo_full>.
    Found 1-bit register for signal <fifo_empty>.
    Found 1-bit register for signal <Stb_d>.
    Found 1-bit register for signal <osc_clk>.
466 467 468 469
    Found 4-bit subtractor for signal <int_counter[3]_GND_68_o_sub_23_OUT> created at line 101.
    Found 4-bit adder for signal <int_counter[3]_GND_68_o_add_20_OUT> created at line 99.
    Found 3-bit adder for signal <int_pointer_w[2]_GND_68_o_add_29_OUT> created at line 115.
    Found 3-bit adder for signal <int_pointer_r[2]_GND_68_o_add_31_OUT> created at line 118.
470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
    Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 165.
    Found 3-bit comparator equal for signal <int_pointer_w[2]_int_pointer_r[2]_equal_42_o> created at line 132
    Found 3-bit comparator equal for signal <n0078> created at line 134
    Found 3-bit comparator equal for signal <int_pointer_r[2]_int_pointer_w[2]_equal_45_o> created at line 137
    Summary:
	inferred   1 RAM(s).
	inferred   3 Adder/Subtractor(s).
	inferred  33 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <InterruptManagerWB> synthesized.

Synthesizing Unit <AddressDecoderWBSys>.
    Related source file is "/vfc_svn/hdl/design/addrdecoderwbsys.v".
WARNING:Xst:647 - Input <Adr_ib22<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AckGenericInputRegs_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit 4-to-1 multiplexer for signal <_n0045> created at line 4.
    Summary:
	inferred  14 Multiplexer(s).
Unit <AddressDecoderWBSys> synthesized.

Synthesizing Unit <Generic4OutputRegs>.
    Related source file is "/vfc_svn/hdl/design/generic4outputregs.v".
        Reg0Default = 32'b00000000000000000000000000000000
        Reg1Default = 32'b00000000000000000000000000000000
        Reg2Default = 32'b00000000000000001000100010001000
        Reg3Default = 32'b00000000000000000000000000000000
    Found 32-bit register for signal <Reg1Value_ob32>.
    Found 32-bit register for signal <Reg2Value_ob32>.
    Found 32-bit register for signal <Reg3Value_ob32>.
    Found 32-bit register for signal <Reg0Value_ob32>.
501
    Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 40.
502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591
    Summary:
	inferred 128 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <Generic4OutputRegs> synthesized.

Synthesizing Unit <Generic4InputRegs>.
    Related source file is "/vfc_svn/hdl/design/generic4inputregs.v".
WARNING:Xst:647 - Input <Rst_irq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred   1 Multiplexer(s).
Unit <Generic4InputRegs> synthesized.

Synthesizing Unit <Slv2SerWB>.
    Related source file is "/vfc_svn/hdl/design/slv2serwb.v".
    Found 32-bit register for signal <DatOutShReg_b32>.
    Found 32-bit register for signal <CntrlShReg_b32>.
    Found 31-bit register for signal <StbShReg_b32<30:0>>.
    Found 3-bit register for signal <AckI_d3>.
    Found 32-bit register for signal <DatInShReg_b32>.
    Found 32-bit register for signal <Dat_xb32>.
    Found 1-bit register for signal <AckI_xb3<2>>.
    Found 1-bit register for signal <AckI_xb3<1>>.
    Found 1-bit register for signal <AckI_xb3<0>>.
    Found 32-bit register for signal <Dat_ob32>.
    Found 1-bit register for signal <Ack_o>.
    Found 1-bit register for signal <StbI_d>.
    Summary:
	inferred 199 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <Slv2SerWB> synthesized.

Synthesizing Unit <SpiMasterWB>.
    Related source file is "/vfc_svn/hdl/design/spimasterwb.v".
    Found 1-bit register for signal <WriteAck_q>.
    Found 1-bit register for signal <ModuleIdle_o>.
    Found 1-bit register for signal <WaitingNewData_o>.
    Found 1-bit register for signal <StartTx_q>.
    Found 1-bit register for signal <SClk_o>.
    Found 1-bit register for signal <SS_onb32<31>>.
    Found 1-bit register for signal <SS_onb32<30>>.
    Found 1-bit register for signal <SS_onb32<29>>.
    Found 1-bit register for signal <SS_onb32<28>>.
    Found 1-bit register for signal <SS_onb32<27>>.
    Found 1-bit register for signal <SS_onb32<26>>.
    Found 1-bit register for signal <SS_onb32<25>>.
    Found 1-bit register for signal <SS_onb32<24>>.
    Found 1-bit register for signal <SS_onb32<23>>.
    Found 1-bit register for signal <SS_onb32<22>>.
    Found 1-bit register for signal <SS_onb32<21>>.
    Found 1-bit register for signal <SS_onb32<20>>.
    Found 1-bit register for signal <SS_onb32<19>>.
    Found 1-bit register for signal <SS_onb32<18>>.
    Found 1-bit register for signal <SS_onb32<17>>.
    Found 1-bit register for signal <SS_onb32<16>>.
    Found 1-bit register for signal <SS_onb32<15>>.
    Found 1-bit register for signal <SS_onb32<14>>.
    Found 1-bit register for signal <SS_onb32<13>>.
    Found 1-bit register for signal <SS_onb32<12>>.
    Found 1-bit register for signal <SS_onb32<11>>.
    Found 1-bit register for signal <SS_onb32<10>>.
    Found 1-bit register for signal <SS_onb32<9>>.
    Found 1-bit register for signal <SS_onb32<8>>.
    Found 1-bit register for signal <SS_onb32<7>>.
    Found 1-bit register for signal <SS_onb32<6>>.
    Found 1-bit register for signal <SS_onb32<5>>.
    Found 1-bit register for signal <SS_onb32<4>>.
    Found 1-bit register for signal <SS_onb32<3>>.
    Found 1-bit register for signal <SS_onb32<2>>.
    Found 1-bit register for signal <SS_onb32<1>>.
    Found 1-bit register for signal <SS_onb32<0>>.
    Found 16-bit register for signal <TimeCounter_cb16>.
    Found 12-bit register for signal <TxCounter_cb12>.
    Found 32-bit register for signal <Config1_qb32>.
    Found 32-bit register for signal <Config2_qb32>.
    Found 32-bit register for signal <ShiftOut_qb32>.
    Found 32-bit register for signal <ShiftIn_qb32>.
    Found 3-bit register for signal <State_q>.
    Found finite state machine <FSM_1> for signal <State_q>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 40                                             |
    | Clock              | Clk_ik (rising_edge)                           |
    | Reset              | Rst_irq (positive)                             |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
592 593
    Found 12-bit adder for signal <TxCounter_cb12[11]_GND_76_o_add_40_OUT> created at line 138.
    Found 16-bit adder for signal <TimeCounter_cb16[15]_GND_76_o_add_67_OUT> created at line 163.
594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612
    Found 1-bit 32-to-1 multiplexer for signal <a_SpiChannel_b5[4]_MiSo_ib32[31]_Mux_56_o> created at line 150.
    Found 32-bit 7-to-1 multiplexer for signal <Dat_oab32> created at line 185.
    Found 16-bit comparator equal for signal <TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o> created at line 77
    Found 12-bit comparator equal for signal <TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o> created at line 80
    Found 16-bit comparator equal for signal <TimeCounter_cb16[15]_a_ClkSemiPeriod_b16[15]_equal_20_o> created at line 84
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 193 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred  35 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <SpiMasterWB> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 8x8-bit dual-port RAM                                 : 1
613
# Adders/Subtractors                                   : 14
614 615
 12-bit adder                                          : 1
 16-bit adder                                          : 2
616
 22-bit adder                                          : 1
617
 23-bit adder                                          : 3
618
 24-bit adder                                          : 3
619 620 621
 3-bit adder                                           : 2
 4-bit addsub                                          : 1
 9-bit adder                                           : 1
622 623
# Registers                                            : 114
 1-bit register                                        : 71
624 625 626
 12-bit register                                       : 1
 16-bit register                                       : 2
 2-bit register                                        : 4
627
 22-bit register                                       : 1
628
 23-bit register                                       : 3
629 630
 24-bit register                                       : 3
 3-bit register                                        : 4
631 632
 31-bit register                                       : 1
 32-bit register                                       : 15
633
 4-bit register                                        : 4
634 635 636 637 638 639 640 641 642
 7-bit register                                        : 1
 8-bit register                                        : 3
 9-bit register                                        : 1
# Comparators                                          : 9
 1-bit comparator equal                                : 1
 12-bit comparator equal                               : 1
 16-bit comparator equal                               : 2
 3-bit comparator equal                                : 4
 8-bit comparator equal                                : 1
643
# Multiplexers                                         : 86
644 645
 1-bit 2-to-1 multiplexer                              : 44
 1-bit 32-to-1 multiplexer                             : 1
646
 1-bit 4-to-1 multiplexer                              : 2
647 648 649 650 651 652 653 654 655
 12-bit 2-to-1 multiplexer                             : 2
 16-bit 2-to-1 multiplexer                             : 8
 22-bit 2-to-1 multiplexer                             : 2
 32-bit 2-to-1 multiplexer                             : 20
 32-bit 4-to-1 multiplexer                             : 3
 32-bit 7-to-1 multiplexer                             : 1
 5-bit 2-to-1 multiplexer                              : 1
 7-bit 2-to-1 multiplexer                              : 1
 9-bit 2-to-1 multiplexer                              : 1
656 657
# Tristates                                            : 64
 1-bit tristate buffer                                 : 64
658
# FSMs                                                 : 2
659 660
# Xors                                                 : 5
 1-bit xor2                                            : 3
661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706
 1-bit xor6                                            : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1710 - FF/Latch <ds1_shr_0> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ds2_shr_0> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds1_shr_1> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds2_shr_1> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.

Synthesizing (advanced) Unit <Debouncer>.
The following registers are absorbed into counter <Counter_c>: 1 register on signal <Counter_c>.
Unit <Debouncer> synthesized (advanced).

Synthesizing (advanced) Unit <InterruptManagerWB>.
The following registers are absorbed into counter <int_counter>: 1 register on signal <int_counter>.
The following registers are absorbed into counter <int_pointer_r>: 1 register on signal <int_pointer_r>.
The following registers are absorbed into counter <int_pointer_w>: 1 register on signal <int_pointer_w>.
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_int_fifo> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 8-bit                      |          |
    |     clkA           | connected to signal <Clk_ik>        | rise     |
    |     weA            | connected to internal node          | high     |
    |     addrA          | connected to signal <int_pointer_w> |          |
    |     diA            | connected to signal <interrupt>     |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 8-word x 8-bit                      |          |
    |     addrB          | connected to signal <int_pointer_r> |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <InterruptManagerWB> synthesized (advanced).

Synthesizing (advanced) Unit <Monostable>.
The following registers are absorbed into counter <Counter_c>: 1 register on signal <Counter_c>.
Unit <Monostable> synthesized (advanced).

Synthesizing (advanced) Unit <SystemFpga>.
The following registers are absorbed into counter <VmeSysClkDivider_c>: 1 register on signal <VmeSysClkDivider_c>.
The following registers are absorbed into counter <Si57xDivider_c>: 1 register on signal <Si57xDivider_c>.
707
The following registers are absorbed into counter <VcTcXoDivider_c>: 1 register on signal <VcTcXoDivider_c>.
708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724
Unit <SystemFpga> synthesized (advanced).

Synthesizing (advanced) Unit <VmeInterfaceWB>.
The following registers are absorbed into counter <AckTimeout_c>: 1 register on signal <AckTimeout_c>.
Unit <VmeInterfaceWB> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 8x8-bit dual-port distributed RAM                     : 1
# Adders/Subtractors                                   : 5
 12-bit adder                                          : 1
 16-bit adder                                          : 1
 22-bit adder                                          : 1
 3-bit adder                                           : 2
725
# Counters                                             : 11
726
 16-bit up counter                                     : 1
727
 23-bit up counter                                     : 3
728
 24-bit up counter                                     : 3
729 730 731
 3-bit up counter                                      : 2
 4-bit updown counter                                  : 1
 9-bit up counter                                      : 1
732 733
# Registers                                            : 689
 Flip-Flops                                            : 689
734 735 736 737 738 739
# Comparators                                          : 9
 1-bit comparator equal                                : 1
 12-bit comparator equal                               : 1
 16-bit comparator equal                               : 2
 3-bit comparator equal                                : 4
 8-bit comparator equal                                : 1
740
# Multiplexers                                         : 116
741 742
 1-bit 2-to-1 multiplexer                              : 44
 1-bit 32-to-1 multiplexer                             : 1
743
 1-bit 4-to-1 multiplexer                              : 34
744 745 746 747 748 749 750 751 752
 12-bit 2-to-1 multiplexer                             : 2
 16-bit 2-to-1 multiplexer                             : 8
 22-bit 2-to-1 multiplexer                             : 2
 32-bit 2-to-1 multiplexer                             : 20
 32-bit 4-to-1 multiplexer                             : 2
 32-bit 7-to-1 multiplexer                             : 1
 5-bit 2-to-1 multiplexer                              : 1
 7-bit 2-to-1 multiplexer                              : 1
# FSMs                                                 : 2
753 754
# Xors                                                 : 5
 1-bit xor2                                            : 3
755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838
 1-bit xor6                                            : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <ds1_shr_0> in Unit <VmeInterfaceWB> is equivalent to the following FF/Latch, which will be removed : <ds2_shr_0> 
WARNING:Xst:1710 - FF/Latch <ds1_shr_0> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds1_shr_1> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds2_shr_1> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <i_Core/i_VmeInterface/FSM_0> on signal <state[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 00
 011   | 01
 010   | 10
 001   | 11
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <i_Core/i_SpiMasterWB/FSM_1> on signal <State_q[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 011
 100   | 100
 101   | 101
-------------------
WARNING:Xst:1293 - FF/Latch <CntrlShReg_b32_31> has a constant value of 0 in block <Slv2SerWB>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <SFpga> ...

Optimizing unit <Monostable> ...

Optimizing unit <Debouncer> ...

Optimizing unit <InterruptManagerWB> ...

Optimizing unit <Generic4OutputRegs> ...

Optimizing unit <Slv2SerWB> ...

Optimizing unit <SpiMasterWB> ...

Optimizing unit <AddressDecoderWBSys> ...
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_9> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_10> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_11> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_12> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_14> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_15> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_13> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_16> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_17> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_19> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_20> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_18> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_22> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_23> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_21> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_25> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_26> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_24> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_27> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_28> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_30> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_31> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_29> of sequential type is unconnected in block <SFpga>.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SFpga, actual ratio is 1.
FlipFlop i_Core/i_VmeInterface/adr_o_21 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/adr_o_3 has been replicated 1 time(s)

Final Macro Processing ...

Processing Unit <SFpga> :
	Found 2-bit shift register for signal <i_Core/VmeSysReset_dx_1>.
839 840
	Found 3-bit shift register for signal <i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2>.
	Found 3-bit shift register for signal <i_Core/i_ClearMonostable/AsynchInAX_db4_2>.
841
	Found 3-bit shift register for signal <i_Core/i_WriteCycleMonostable/AsynchInAX_db4_2>.
842 843 844 845 846 847 848 849
	Found 3-bit shift register for signal <i_Core/i_Debouncer/BouncingSignal_x_2>.
	Found 2-bit shift register for signal <i_Core/i_Slv2SerWB/AckI_xb3_0>.
Unit <SFpga> processed.

=========================================================================
Final Register Report

Macro Statistics
850 851
# Registers                                            : 828
 Flip-Flops                                            : 828
852
# Shift Registers                                      : 6
853
 2-bit shift register                                  : 2
854
 3-bit shift register                                  : 4
855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : SFpga.ngc

Primitive and Black Box Usage:
------------------------------
877
# BELS                             : 1555
878
#      GND                         : 1
879
#      INV                         : 32
880
#      LUT1                        : 197
881
#      LUT2                        : 168
882
#      LUT3                        : 130
883 884 885 886
#      LUT4                        : 116
#      LUT5                        : 148
#      LUT6                        : 298
#      MUXCY                       : 220
887
#      MUXF7                       : 28
888
#      VCC                         : 1
889 890
#      XORCY                       : 216
# FlipFlops/Latches                : 834
891 892
#      FD                          : 195
#      FDE                         : 102
893 894
#      FDPE                        : 1
#      FDR                         : 135
895
#      FDRE                        : 342
896 897 898 899 900
#      FDS                         : 26
#      FDSE                        : 33
# RAMS                             : 3
#      RAM16X1D                    : 2
#      RAM32M                      : 1
901 902
# Shift Registers                  : 6
#      SRLC16E                     : 6
903
# Clock Buffers                    : 4
904 905 906 907
#      BUFG                        : 2
#      BUFGP                       : 2
# IO Buffers                       : 303
#      IBUF                        : 76
908 909 910
#      IBUFGDS                     : 6
#      IOBUF                       : 32
#      IOBUFDS                     : 2
911
#      OBUF                        : 152
912
#      OBUFDS                      : 3
913
#      OBUFT                       : 32
914 915 916 917 918 919 920 921

Device utilization summary:
---------------------------

Selected Device : 6slx150tfgg676-3 


Slice Logic Utilization: 
922 923 924
 Number of Slice Registers:             834  out of  184304     0%  
 Number of Slice LUTs:                 1103  out of  92152     1%  
    Number used as Logic:              1089  out of  92152     1%  
925
    Number used as Memory:               14  out of  21680     0%  
926
       Number used as RAM:                8
927
       Number used as SRL:                6
928 929

Slice Logic Distribution: 
930 931 932 933
 Number of LUT Flip Flop pairs used:   1319
   Number with an unused Flip Flop:     485  out of   1319    36%  
   Number with an unused LUT:           216  out of   1319    16%  
   Number of fully used LUT-FF pairs:   618  out of   1319    46%  
934
   Number of unique control sets:        34
935 936 937

IO Utilization: 
 Number of IOs:                         365
938
 Number of bonded IOBs:                 316  out of    396    79%  
939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                4  out of     16    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
961 962 963
-----------------------------------+------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                          | Load  |
-----------------------------------+------------------------------------------------+-------+
964 965
VcTcXo_ik                          | IBUF+BUFG                                      | 724   |
Si57x_ik                           | IBUFGDS+BUFG                                   | 24    |
966 967 968 969 970 971
VmeSysClk_ik                       | BUFGP                                          | 24    |
i_Core/i_VmeInterface/stb_o        | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax) | 1     |
i_Core/Rst_rq                      | NONE(i_Core/i_ClearMonostable/AsynchIn_ax)     | 1     |
i_Core/WriteCycle                  | NONE(i_Core/i_WriteCycleMonostable/AsynchIn_ax)| 1     |
SysAppClk_ik                       | BUFGP                                          | 68    |
-----------------------------------+------------------------------------------------+-------+
972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 8.328ns (Maximum Frequency: 120.083MHz)
   Minimum input arrival time before clock: 8.362ns
   Maximum output required time after clock: 6.030ns
   Maximum combinational path delay: 6.896ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
992
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
993
  Clock period: 8.328ns (frequency: 120.083MHz)
994
  Total number of paths / destination ports: 45868 / 1672
995 996 997 998
-------------------------------------------------------------------------
Delay:               8.328ns (Levels of Logic = 5)
  Source:            i_Core/i_VmeInterface/adr_o_21_1 (FF)
  Destination:       i_Core/i_VmeInterface/DataReg_31 (FF)
999 1000
  Source Clock:      VcTcXo_ik rising
  Destination Clock: VcTcXo_ik rising
1001 1002 1003 1004 1005 1006

  Data Path: i_Core/i_VmeInterface/adr_o_21_1 to i_Core/i_VmeInterface/DataReg_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   0.525   1.047  i_Core/i_VmeInterface/adr_o_21_1 (i_Core/i_VmeInterface/adr_o_21_1)
1007 1008
     LUT6:I1->O            4   0.254   0.912  i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12)
     LUT4:I1->O            1   0.235   0.688  i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1)
1009 1010
     LUT5:I3->O            5   0.250   0.715  i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster)
     LUT6:I5->O           58   0.254   1.601  i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster)
1011
     LUT3:I2->O           32   0.254   1.291  i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_33_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_33_o)
1012 1013 1014 1015 1016 1017
     FDSE:CE                   0.302          i_Core/i_VmeInterface/DataReg_0
    ----------------------------------------
    Total                      8.328ns (2.074ns logic, 6.254ns route)
                                       (24.9% logic, 75.1% route)

=========================================================================
1018
Timing constraint: Default period analysis for Clock 'Si57x_ik'
1019 1020
  Clock period: 2.365ns (frequency: 422.770MHz)
  Total number of paths / destination ports: 300 / 24
1021
-------------------------------------------------------------------------
1022
Delay:               2.365ns (Levels of Logic = 25)
1023 1024 1025 1026
  Source:            i_Core/Si57xDivider_c_0 (FF)
  Destination:       i_Core/Si57xDivider_c_23 (FF)
  Source Clock:      Si57x_ik rising
  Destination Clock: Si57x_ik rising
1027

1028
  Data Path: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_23
1029 1030 1031
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058
     FD:C->Q               1   0.525   0.579  i_Core/Si57xDivider_c_0 (i_Core/Si57xDivider_c_0)
     INV:I->O              1   0.255   0.000  i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0 (i_Core/Mcount_Si57xDivider_c_lut<0>)
     MUXCY:S->O            1   0.215   0.000  i_Core/Mcount_Si57xDivider_c_cy<0> (i_Core/Mcount_Si57xDivider_c_cy<0>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<1> (i_Core/Mcount_Si57xDivider_c_cy<1>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<2> (i_Core/Mcount_Si57xDivider_c_cy<2>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<3> (i_Core/Mcount_Si57xDivider_c_cy<3>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<4> (i_Core/Mcount_Si57xDivider_c_cy<4>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<5> (i_Core/Mcount_Si57xDivider_c_cy<5>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<6> (i_Core/Mcount_Si57xDivider_c_cy<6>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<7> (i_Core/Mcount_Si57xDivider_c_cy<7>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<8> (i_Core/Mcount_Si57xDivider_c_cy<8>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<9> (i_Core/Mcount_Si57xDivider_c_cy<9>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<10> (i_Core/Mcount_Si57xDivider_c_cy<10>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<11> (i_Core/Mcount_Si57xDivider_c_cy<11>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<12> (i_Core/Mcount_Si57xDivider_c_cy<12>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<13> (i_Core/Mcount_Si57xDivider_c_cy<13>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<14> (i_Core/Mcount_Si57xDivider_c_cy<14>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<15> (i_Core/Mcount_Si57xDivider_c_cy<15>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<16> (i_Core/Mcount_Si57xDivider_c_cy<16>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<17> (i_Core/Mcount_Si57xDivider_c_cy<17>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<18> (i_Core/Mcount_Si57xDivider_c_cy<18>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<19> (i_Core/Mcount_Si57xDivider_c_cy<19>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<20> (i_Core/Mcount_Si57xDivider_c_cy<20>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<21> (i_Core/Mcount_Si57xDivider_c_cy<21>)
     MUXCY:CI->O           0   0.023   0.000  i_Core/Mcount_Si57xDivider_c_cy<22> (i_Core/Mcount_Si57xDivider_c_cy<22>)
     XORCY:CI->O           1   0.206   0.000  i_Core/Mcount_Si57xDivider_c_xor<23> (i_Core/Result<23>1)
     FD:D                      0.074          i_Core/Si57xDivider_c_23
1059
    ----------------------------------------
1060 1061
    Total                      2.365ns (1.787ns logic, 0.579ns route)
                                       (75.5% logic, 24.5% route)
1062 1063 1064

=========================================================================
Timing constraint: Default period analysis for Clock 'VmeSysClk_ik'
1065 1066
  Clock period: 2.365ns (frequency: 422.770MHz)
  Total number of paths / destination ports: 300 / 24
1067
-------------------------------------------------------------------------
1068
Delay:               2.365ns (Levels of Logic = 25)
1069
  Source:            i_Core/VmeSysClkDivider_c_0 (FF)
1070
  Destination:       i_Core/VmeSysClkDivider_c_23 (FF)
1071 1072 1073
  Source Clock:      VmeSysClk_ik rising
  Destination Clock: VmeSysClk_ik rising

1074
  Data Path: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_23
1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.525   0.579  i_Core/VmeSysClkDivider_c_0 (i_Core/VmeSysClkDivider_c_0)
     INV:I->O              1   0.255   0.000  i_Core/Mcount_VmeSysClkDivider_c_lut<0>_INV_0 (i_Core/Mcount_VmeSysClkDivider_c_lut<0>)
     MUXCY:S->O            1   0.215   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<0> (i_Core/Mcount_VmeSysClkDivider_c_cy<0>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<1> (i_Core/Mcount_VmeSysClkDivider_c_cy<1>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<2> (i_Core/Mcount_VmeSysClkDivider_c_cy<2>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<3> (i_Core/Mcount_VmeSysClkDivider_c_cy<3>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<4> (i_Core/Mcount_VmeSysClkDivider_c_cy<4>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<5> (i_Core/Mcount_VmeSysClkDivider_c_cy<5>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<6> (i_Core/Mcount_VmeSysClkDivider_c_cy<6>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<7> (i_Core/Mcount_VmeSysClkDivider_c_cy<7>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<8> (i_Core/Mcount_VmeSysClkDivider_c_cy<8>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<9> (i_Core/Mcount_VmeSysClkDivider_c_cy<9>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<10> (i_Core/Mcount_VmeSysClkDivider_c_cy<10>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<11> (i_Core/Mcount_VmeSysClkDivider_c_cy<11>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<12> (i_Core/Mcount_VmeSysClkDivider_c_cy<12>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<13> (i_Core/Mcount_VmeSysClkDivider_c_cy<13>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<14> (i_Core/Mcount_VmeSysClkDivider_c_cy<14>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<15> (i_Core/Mcount_VmeSysClkDivider_c_cy<15>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<16> (i_Core/Mcount_VmeSysClkDivider_c_cy<16>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<17> (i_Core/Mcount_VmeSysClkDivider_c_cy<17>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<18> (i_Core/Mcount_VmeSysClkDivider_c_cy<18>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<19> (i_Core/Mcount_VmeSysClkDivider_c_cy<19>)
1100 1101 1102 1103 1104
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<20> (i_Core/Mcount_VmeSysClkDivider_c_cy<20>)
     MUXCY:CI->O           1   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<21> (i_Core/Mcount_VmeSysClkDivider_c_cy<21>)
     MUXCY:CI->O           0   0.023   0.000  i_Core/Mcount_VmeSysClkDivider_c_cy<22> (i_Core/Mcount_VmeSysClkDivider_c_cy<22>)
     XORCY:CI->O           1   0.206   0.000  i_Core/Mcount_VmeSysClkDivider_c_xor<23> (i_Core/Result<23>)
     FD:D                      0.074          i_Core/VmeSysClkDivider_c_23
1105
    ----------------------------------------
1106 1107
    Total                      2.365ns (1.787ns logic, 0.579ns route)
                                       (75.5% logic, 24.5% route)
1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152

=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/i_VmeInterface/stb_o'
  Clock period: 2.049ns (frequency: 488.019MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.049ns (Levels of Logic = 1)
  Source:            i_Core/i_VmeAccessMonostable/AsynchIn_ax (FF)
  Destination:       i_Core/i_VmeAccessMonostable/AsynchIn_ax (FF)
  Source Clock:      i_Core/i_VmeInterface/stb_o rising
  Destination Clock: i_Core/i_VmeInterface/stb_o rising

  Data Path: i_Core/i_VmeAccessMonostable/AsynchIn_ax to i_Core/i_VmeAccessMonostable/AsynchIn_ax
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.525   0.616  i_Core/i_VmeAccessMonostable/AsynchIn_ax (i_Core/i_VmeAccessMonostable/AsynchIn_ax)
     INV:I->O              1   0.255   0.579  i_Core/i_VmeAccessMonostable/AsynchIn_ax_INV_1_o1_INV_0 (i_Core/i_VmeAccessMonostable/AsynchIn_ax_INV_1_o)
     FD:D                      0.074          i_Core/i_VmeAccessMonostable/AsynchIn_ax
    ----------------------------------------
    Total                      2.049ns (0.854ns logic, 1.195ns route)
                                       (41.7% logic, 58.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/Rst_rq'
  Clock period: 2.049ns (frequency: 488.019MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.049ns (Levels of Logic = 1)
  Source:            i_Core/i_ClearMonostable/AsynchIn_ax (FF)
  Destination:       i_Core/i_ClearMonostable/AsynchIn_ax (FF)
  Source Clock:      i_Core/Rst_rq rising
  Destination Clock: i_Core/Rst_rq rising

  Data Path: i_Core/i_ClearMonostable/AsynchIn_ax to i_Core/i_ClearMonostable/AsynchIn_ax
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.525   0.616  i_Core/i_ClearMonostable/AsynchIn_ax (i_Core/i_ClearMonostable/AsynchIn_ax)
     INV:I->O              1   0.255   0.579  i_Core/i_ClearMonostable/AsynchIn_ax_INV_1_o1_INV_0 (i_Core/i_ClearMonostable/AsynchIn_ax_INV_1_o)
     FD:D                      0.074          i_Core/i_ClearMonostable/AsynchIn_ax
    ----------------------------------------
    Total                      2.049ns (0.854ns logic, 1.195ns route)
                                       (41.7% logic, 58.3% route)

1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174
=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/WriteCycle'
  Clock period: 2.049ns (frequency: 488.019MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.049ns (Levels of Logic = 1)
  Source:            i_Core/i_WriteCycleMonostable/AsynchIn_ax (FF)
  Destination:       i_Core/i_WriteCycleMonostable/AsynchIn_ax (FF)
  Source Clock:      i_Core/WriteCycle rising
  Destination Clock: i_Core/WriteCycle rising

  Data Path: i_Core/i_WriteCycleMonostable/AsynchIn_ax to i_Core/i_WriteCycleMonostable/AsynchIn_ax
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.525   0.616  i_Core/i_WriteCycleMonostable/AsynchIn_ax (i_Core/i_WriteCycleMonostable/AsynchIn_ax)
     INV:I->O              1   0.255   0.579  i_Core/i_WriteCycleMonostable/AsynchIn_ax_INV_1_o1_INV_0 (i_Core/i_WriteCycleMonostable/AsynchIn_ax_INV_1_o)
     FD:D                      0.074          i_Core/i_WriteCycleMonostable/AsynchIn_ax
    ----------------------------------------
    Total                      2.049ns (0.854ns logic, 1.195ns route)
                                       (41.7% logic, 58.3% route)

1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197
=========================================================================
Timing constraint: Default period analysis for Clock 'SysAppClk_ik'
  Clock period: 3.056ns (frequency: 327.221MHz)
  Total number of paths / destination ports: 129 / 97
-------------------------------------------------------------------------
Delay:               3.056ns (Levels of Logic = 1)
  Source:            i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
  Destination:       i_Core/i_Slv2SerWB/Dat_xb32_31 (FF)
  Source Clock:      SysAppClk_ik rising
  Destination Clock: SysAppClk_ik rising

  Data Path: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.525   0.688  i_Core/i_Slv2SerWB/AckI_d3_2 (i_Core/i_Slv2SerWB/AckI_d3_2)
     LUT2:I0->O           32   0.250   1.291  i_Core/i_Slv2SerWB/NewAckI_a<2>1 (i_Core/i_Slv2SerWB/NewAckI_a)
     FDE:CE                    0.302          i_Core/i_Slv2SerWB/Dat_xb32_0
    ----------------------------------------
    Total                      3.056ns (1.077ns logic, 1.979ns route)
                                       (35.2% logic, 64.8% route)

=========================================================================
1198
Timing constraint: Default OFFSET IN BEFORE for Clock 'VcTcXo_ik'
1199 1200 1201 1202 1203
  Total number of paths / destination ports: 1705 / 116
-------------------------------------------------------------------------
Offset:              8.362ns (Levels of Logic = 6)
  Source:            VmeGa_ib5n<0> (PAD)
  Destination:       i_Core/i_VmeInterface/adr_o_21 (FF)
1204
  Destination Clock: VcTcXo_ik rising
1205 1206 1207 1208 1209 1210 1211

  Data Path: VmeGa_ib5n<0> to i_Core/i_VmeInterface/adr_o_21
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.228   1.047  VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
     LUT6:I1->O            5   0.254   0.943  i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
1212 1213
     LUT4:I1->O            2   0.235   0.725  i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N6)
     LUT6:I4->O            1   0.250   0.808  i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N260)
1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240
     LUT6:I3->O           12   0.235   0.909  i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected)
     LUT5:I4->O           24   0.254   1.172  i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv)
     FDRE:CE                   0.302          i_Core/i_VmeInterface/adr_o_0
    ----------------------------------------
    Total                      8.362ns (2.758ns logic, 5.604ns route)
                                       (33.0% logic, 67.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SysAppClk_ik'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              1.918ns (Levels of Logic = 1)
  Source:            AFpgaProgD_iob8<4> (PAD)
  Destination:       i_Core/i_Slv2SerWB/AckI_xb3_2 (FF)
  Destination Clock: SysAppClk_ik rising

  Data Path: AFpgaProgD_iob8<4> to i_Core/i_Slv2SerWB/AckI_xb3_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.228   0.616  AFpgaProgD_iob8_4_IBUF (AFpgaProgD_iob8_4_IBUF)
     FDR:D                     0.074          i_Core/i_Slv2SerWB/AckI_d3_0
    ----------------------------------------
    Total                      1.918ns (1.302ns logic, 0.616ns route)
                                       (67.9% logic, 32.1% route)

=========================================================================
1241
Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik'
1242 1243 1244 1245 1246
  Total number of paths / destination ports: 190 / 94
-------------------------------------------------------------------------
Offset:              6.030ns (Levels of Logic = 2)
  Source:            i_Core/i_SpiMasterWB/Config1_qb32_29 (FF)
  Destination:       FlashSFpgaD_o (PAD)
1247
  Source Clock:      VcTcXo_ik rising
1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261

  Data Path: i_Core/i_SpiMasterWB/Config1_qb32_29 to FlashSFpgaD_o
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            66   0.525   1.654  i_Core/i_SpiMasterWB/Config1_qb32_29 (i_Core/i_SpiMasterWB/Config1_qb32_29)
     LUT3:I2->O           11   0.254   0.882  i_Core/i_SpiMasterWB/Mmux_MoSi_o11 (FlashAFpgaD_o_OBUF)
     OBUF:I->O                 2.715          PllFmc1SDio_io_OBUF (PllFmc1SDio_io)
    ----------------------------------------
    Total                      6.030ns (3.494ns logic, 2.536ns route)
                                       (57.9% logic, 42.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'VmeSysClk_ik'
1262
  Total number of paths / destination ports: 1 / 1
1263
-------------------------------------------------------------------------
1264
Offset:              3.856ns (Levels of Logic = 1)
1265
  Source:            i_Core/VmeSysClkDivider_c_23 (FF)
1266
  Destination:       FpLed_onb8<6> (PAD)
1267 1268
  Source Clock:      VmeSysClk_ik rising

1269
  Data Path: i_Core/VmeSysClkDivider_c_23 to FpLed_onb8<6>
1270 1271 1272
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
1273 1274
     FD:C->Q               2   0.525   0.616  i_Core/VmeSysClkDivider_c_23 (i_Core/VmeSysClkDivider_c_23)
     OBUFT:T->O                2.715          FpLed_onb8_6_OBUFT (FpLed_onb8<6>)
1275
    ----------------------------------------
1276 1277
    Total                      3.856ns (3.240ns logic, 0.616ns route)
                                       (84.0% logic, 16.0% route)
1278 1279

=========================================================================
1280
Timing constraint: Default OFFSET OUT AFTER for Clock 'Si57x_ik'
1281
  Total number of paths / destination ports: 1 / 1
1282
-------------------------------------------------------------------------
1283
Offset:              3.856ns (Levels of Logic = 1)
1284 1285 1286
  Source:            i_Core/Si57xDivider_c_23 (FF)
  Destination:       FpLed_onb8<4> (PAD)
  Source Clock:      Si57x_ik rising
1287

1288
  Data Path: i_Core/Si57xDivider_c_23 to FpLed_onb8<4>
1289 1290 1291
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
1292 1293
     FD:C->Q               2   0.525   0.616  i_Core/Si57xDivider_c_23 (i_Core/Si57xDivider_c_23)
     OBUFT:T->O                2.715          FpLed_onb8_4_OBUFT (FpLed_onb8<4>)
1294
    ----------------------------------------
1295 1296
    Total                      3.856ns (3.240ns logic, 0.616ns route)
                                       (84.0% logic, 16.0% route)
1297 1298 1299

=========================================================================
Timing constraint: Default path analysis
1300
  Total number of paths / destination ports: 13 / 7
1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
-------------------------------------------------------------------------
Delay:               6.896ns (Levels of Logic = 4)
  Source:            VmeGa_ib5n<0> (PAD)
  Destination:       FpLed_onb8<2> (PAD)

  Data Path: VmeGa_ib5n<0> to FpLed_onb8<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.228   1.047  VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
     LUT6:I1->O            5   0.254   0.823  i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
1312
     LUT2:I0->O            1   0.250   0.579  i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv1 (i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv)
1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327
     OBUFT:T->O                2.715          FpLed_onb8_2_OBUFT (FpLed_onb8<2>)
    ----------------------------------------
    Total                      6.896ns (4.447ns logic, 2.449ns route)
                                       (64.5% logic, 35.5% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock Si57x_ik
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
1328
Si57x_ik       |    2.365|         |         |         |
1329 1330
---------------+---------+---------+---------+---------+

1331
Clock to Setup on destination clock SysAppClk_ik
1332 1333 1334 1335
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
1336 1337
SysAppClk_ik   |    3.056|         |         |         |
VcTcXo_ik      |    3.078|         |         |         |
1338 1339
---------------+---------+---------+---------+---------+

1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351
Clock to Setup on destination clock VcTcXo_ik
---------------------------+---------+---------+---------+---------+
                           | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock               |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+
SysAppClk_ik               |    1.178|         |         |         |
VcTcXo_ik                  |    8.328|         |         |         |
i_Core/Rst_rq              |    1.141|         |         |         |
i_Core/WriteCycle          |    1.141|         |         |         |
i_Core/i_VmeInterface/stb_o|    1.141|         |         |         |
---------------------------+---------+---------+---------+---------+

1352 1353 1354 1355 1356
Clock to Setup on destination clock VmeSysClk_ik
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
1357
VmeSysClk_ik   |    2.365|         |         |         |
1358 1359 1360 1361 1362 1363 1364 1365 1366 1367
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock i_Core/Rst_rq
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
i_Core/Rst_rq  |    2.049|         |         |         |
---------------+---------+---------+---------+---------+

1368 1369 1370 1371 1372 1373 1374 1375
Clock to Setup on destination clock i_Core/WriteCycle
-----------------+---------+---------+---------+---------+
                 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock     |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
i_Core/WriteCycle|    2.049|         |         |         |
-----------------+---------+---------+---------+---------+

1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386
Clock to Setup on destination clock i_Core/i_VmeInterface/stb_o
---------------------------+---------+---------+---------+---------+
                           | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock               |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+
i_Core/i_VmeInterface/stb_o|    2.049|         |         |         |
---------------------------+---------+---------+---------+---------+

=========================================================================


1387 1388
Total REAL time to Xst completion: 16.00 secs
Total CPU time to Xst completion: 16.80 secs
1389 1390 1391
 
--> 

1392
Total memory usage is 280080 kilobytes
1393 1394

Number of errors   :    0 (   0 filtered)
1395
Number of warnings :  130 (   0 filtered)
1396 1397
Number of infos    :   12 (   0 filtered)