SFpga.twr 134 KB
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--------------------------------------------------------------------------------
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Release 12.3 Trace  (nt64)
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Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

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C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
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Design file:              SFpga.ncd
Physical constraint file: SFpga.pcf
Device,package,speed:     xc6slx150t,fgg676,C,-3 (PRODUCTION 1.12c 2010-09-15)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
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Timing constraint: TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" 25 MHz HIGH 50%;
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 46004 paths analyzed, 3159 endpoints analyzed, 0 failing endpoints
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 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
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 Minimum period is  12.735ns.
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--------------------------------------------------------------------------------

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Paths for end point i_Core/i_VmeInterface/adr_o_0 (SLICE_X74Y118.CE), 15 paths
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--------------------------------------------------------------------------------
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Slack (setup path):     27.265ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/state_FSM_FFd1 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_0 (FF)
  Requirement:          40.000ns
  Data Path Delay:      12.658ns (Levels of Logic = 1)
  Clock Path Skew:      -0.042ns (0.804 - 0.846)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/state_FSM_FFd1 to i_Core/i_VmeInterface/adr_o_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X85Y64.AQ      Tcko                  0.430   i_Core/i_VmeInterface/state_FSM_FFd1
                                                       i_Core/i_VmeInterface/state_FSM_FFd1
    SLICE_X90Y141.D5     net (fanout=77)       7.937   i_Core/i_VmeInterface/state_FSM_FFd1
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.314   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_0
    -------------------------------------------------  ---------------------------
    Total                                     12.658ns (1.070ns logic, 11.588ns route)
                                                       (8.5% logic, 91.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     32.014ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/VmeBaseAddr_7 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_0 (FF)
  Requirement:          40.000ns
  Data Path Delay:      7.997ns (Levels of Logic = 3)
  Clock Path Skew:      0.046ns (0.715 - 0.669)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_7 to i_Core/i_VmeInterface/adr_o_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y141.DQ    Tcko                  0.525   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr_7
    SLICE_X104Y141.A2    net (fanout=1)        0.713   i_Core/i_VmeInterface/VmeBaseAddr<7>
    SLICE_X104Y141.A     Tilo                  0.254   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o86
    SLICE_X90Y141.C5     net (fanout=2)        1.448   i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o85
    SLICE_X90Y141.C      Tilo                  0.255   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/selected
    SLICE_X90Y141.D4     net (fanout=12)       0.511   i_Core/i_VmeInterface/selected
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.314   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_0
    -------------------------------------------------  ---------------------------
    Total                                      7.997ns (1.674ns logic, 6.323ns route)
                                                       (20.9% logic, 79.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     32.190ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/VmeBaseAddr_5 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_0 (FF)
  Requirement:          40.000ns
  Data Path Delay:      7.821ns (Levels of Logic = 3)
  Clock Path Skew:      0.046ns (0.715 - 0.669)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_5 to i_Core/i_VmeInterface/adr_o_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y141.BQ    Tcko                  0.525   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr_5
    SLICE_X104Y141.A3    net (fanout=1)        0.537   i_Core/i_VmeInterface/VmeBaseAddr<5>
    SLICE_X104Y141.A     Tilo                  0.254   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o86
    SLICE_X90Y141.C5     net (fanout=2)        1.448   i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o85
    SLICE_X90Y141.C      Tilo                  0.255   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/selected
    SLICE_X90Y141.D4     net (fanout=12)       0.511   i_Core/i_VmeInterface/selected
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.314   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_0
    -------------------------------------------------  ---------------------------
    Total                                      7.821ns (1.674ns logic, 6.147ns route)
                                                       (21.4% logic, 78.6% route)

--------------------------------------------------------------------------------

Paths for end point i_Core/i_VmeInterface/adr_o_3 (SLICE_X74Y118.CE), 15 paths
--------------------------------------------------------------------------------
Slack (setup path):     27.288ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/state_FSM_FFd1 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_3 (FF)
  Requirement:          40.000ns
  Data Path Delay:      12.635ns (Levels of Logic = 1)
  Clock Path Skew:      -0.042ns (0.804 - 0.846)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/state_FSM_FFd1 to i_Core/i_VmeInterface/adr_o_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X85Y64.AQ      Tcko                  0.430   i_Core/i_VmeInterface/state_FSM_FFd1
                                                       i_Core/i_VmeInterface/state_FSM_FFd1
    SLICE_X90Y141.D5     net (fanout=77)       7.937   i_Core/i_VmeInterface/state_FSM_FFd1
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.291   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_3
    -------------------------------------------------  ---------------------------
    Total                                     12.635ns (1.047ns logic, 11.588ns route)
                                                       (8.3% logic, 91.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     32.037ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/VmeBaseAddr_7 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_3 (FF)
  Requirement:          40.000ns
  Data Path Delay:      7.974ns (Levels of Logic = 3)
  Clock Path Skew:      0.046ns (0.715 - 0.669)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_7 to i_Core/i_VmeInterface/adr_o_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y141.DQ    Tcko                  0.525   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr_7
    SLICE_X104Y141.A2    net (fanout=1)        0.713   i_Core/i_VmeInterface/VmeBaseAddr<7>
    SLICE_X104Y141.A     Tilo                  0.254   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o86
    SLICE_X90Y141.C5     net (fanout=2)        1.448   i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o85
    SLICE_X90Y141.C      Tilo                  0.255   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/selected
    SLICE_X90Y141.D4     net (fanout=12)       0.511   i_Core/i_VmeInterface/selected
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.291   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_3
    -------------------------------------------------  ---------------------------
    Total                                      7.974ns (1.651ns logic, 6.323ns route)
                                                       (20.7% logic, 79.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     32.213ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/VmeBaseAddr_5 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_3 (FF)
  Requirement:          40.000ns
  Data Path Delay:      7.798ns (Levels of Logic = 3)
  Clock Path Skew:      0.046ns (0.715 - 0.669)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_5 to i_Core/i_VmeInterface/adr_o_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y141.BQ    Tcko                  0.525   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr_5
    SLICE_X104Y141.A3    net (fanout=1)        0.537   i_Core/i_VmeInterface/VmeBaseAddr<5>
    SLICE_X104Y141.A     Tilo                  0.254   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o86
    SLICE_X90Y141.C5     net (fanout=2)        1.448   i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o85
    SLICE_X90Y141.C      Tilo                  0.255   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/selected
    SLICE_X90Y141.D4     net (fanout=12)       0.511   i_Core/i_VmeInterface/selected
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.291   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_3
    -------------------------------------------------  ---------------------------
    Total                                      7.798ns (1.651ns logic, 6.147ns route)
                                                       (21.2% logic, 78.8% route)

--------------------------------------------------------------------------------

Paths for end point i_Core/i_VmeInterface/adr_o_2 (SLICE_X74Y118.CE), 15 paths
--------------------------------------------------------------------------------
Slack (setup path):     27.290ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/state_FSM_FFd1 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_2 (FF)
  Requirement:          40.000ns
  Data Path Delay:      12.633ns (Levels of Logic = 1)
  Clock Path Skew:      -0.042ns (0.804 - 0.846)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/state_FSM_FFd1 to i_Core/i_VmeInterface/adr_o_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X85Y64.AQ      Tcko                  0.430   i_Core/i_VmeInterface/state_FSM_FFd1
                                                       i_Core/i_VmeInterface/state_FSM_FFd1
    SLICE_X90Y141.D5     net (fanout=77)       7.937   i_Core/i_VmeInterface/state_FSM_FFd1
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.289   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_2
    -------------------------------------------------  ---------------------------
    Total                                     12.633ns (1.045ns logic, 11.588ns route)
                                                       (8.3% logic, 91.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     32.039ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/VmeBaseAddr_7 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_2 (FF)
  Requirement:          40.000ns
  Data Path Delay:      7.972ns (Levels of Logic = 3)
  Clock Path Skew:      0.046ns (0.715 - 0.669)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_7 to i_Core/i_VmeInterface/adr_o_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y141.DQ    Tcko                  0.525   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr_7
    SLICE_X104Y141.A2    net (fanout=1)        0.713   i_Core/i_VmeInterface/VmeBaseAddr<7>
    SLICE_X104Y141.A     Tilo                  0.254   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o86
    SLICE_X90Y141.C5     net (fanout=2)        1.448   i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o85
    SLICE_X90Y141.C      Tilo                  0.255   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/selected
    SLICE_X90Y141.D4     net (fanout=12)       0.511   i_Core/i_VmeInterface/selected
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.289   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_2
    -------------------------------------------------  ---------------------------
    Total                                      7.972ns (1.649ns logic, 6.323ns route)
                                                       (20.7% logic, 79.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     32.215ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/i_VmeInterface/VmeBaseAddr_5 (FF)
  Destination:          i_Core/i_VmeInterface/adr_o_2 (FF)
  Requirement:          40.000ns
  Data Path Delay:      7.796ns (Levels of Logic = 3)
  Clock Path Skew:      0.046ns (0.715 - 0.669)
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_5 to i_Core/i_VmeInterface/adr_o_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y141.BQ    Tcko                  0.525   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr_5
    SLICE_X104Y141.A3    net (fanout=1)        0.537   i_Core/i_VmeInterface/VmeBaseAddr<5>
    SLICE_X104Y141.A     Tilo                  0.254   i_Core/i_VmeInterface/VmeBaseAddr<7>
                                                       i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o86
    SLICE_X90Y141.C5     net (fanout=2)        1.448   i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o85
    SLICE_X90Y141.C      Tilo                  0.255   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/selected
    SLICE_X90Y141.D4     net (fanout=12)       0.511   i_Core/i_VmeInterface/selected
    SLICE_X90Y141.DMUX   Tilo                  0.326   i_Core/i_VmeInterface/as_int_pre_as_int_AND_71_o
                                                       i_Core/i_VmeInterface/_n0350_inv1
    SLICE_X74Y118.CE     net (fanout=6)        3.651   i_Core/i_VmeInterface/_n0350_inv
    SLICE_X74Y118.CLK    Tceck                 0.289   i_Core/i_VmeInterface/adr_o<3>
                                                       i_Core/i_VmeInterface/adr_o_2
    -------------------------------------------------  ---------------------------
    Total                                      7.796ns (1.649ns logic, 6.147ns route)
                                                       (21.2% logic, 78.8% route)

--------------------------------------------------------------------------------

Hold Paths: TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" 25 MHz HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point i_Core/i_VmeInterface/dat_o_27 (SLICE_X88Y80.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.413ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/i_VmeInterface/dat_o_27 (FF)
  Destination:          i_Core/i_VmeInterface/dat_o_27 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.413ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Core/i_VmeInterface/dat_o_27 to i_Core/i_VmeInterface/dat_o_27
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y80.DQ      Tcko                  0.200   i_Core/i_VmeInterface/dat_o<27>
                                                       i_Core/i_VmeInterface/dat_o_27
    SLICE_X88Y80.D6      net (fanout=8)        0.023   i_Core/i_VmeInterface/dat_o<27>
    SLICE_X88Y80.CLK     Tah         (-Th)    -0.190   i_Core/i_VmeInterface/dat_o<27>
                                                       i_Core/i_VmeInterface/dat_o_27_dpot
                                                       i_Core/i_VmeInterface/dat_o_27
    -------------------------------------------------  ---------------------------
    Total                                      0.413ns (0.390ns logic, 0.023ns route)
                                                       (94.4% logic, 5.6% route)

--------------------------------------------------------------------------------

Paths for end point i_Core/i_VmeInterface/dat_o_11 (SLICE_X78Y109.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.417ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/i_VmeInterface/dat_o_11 (FF)
  Destination:          i_Core/i_VmeInterface/dat_o_11 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.417ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Core/i_VmeInterface/dat_o_11 to i_Core/i_VmeInterface/dat_o_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X78Y109.DQ     Tcko                  0.200   i_Core/i_VmeInterface/dat_o<11>
                                                       i_Core/i_VmeInterface/dat_o_11
    SLICE_X78Y109.D6     net (fanout=8)        0.027   i_Core/i_VmeInterface/dat_o<11>
    SLICE_X78Y109.CLK    Tah         (-Th)    -0.190   i_Core/i_VmeInterface/dat_o<11>
                                                       i_Core/i_VmeInterface/dat_o_11_dpot
                                                       i_Core/i_VmeInterface/dat_o_11
    -------------------------------------------------  ---------------------------
    Total                                      0.417ns (0.390ns logic, 0.027ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------

Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_3 (SLICE_X62Y80.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.424ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/i_SpiMasterWB/ShiftIn_qb32_3 (FF)
  Destination:          i_Core/i_SpiMasterWB/ShiftIn_qb32_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.424ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Destination Clock:    VcTcXo_ik_IBUF_BUFG rising at 40.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Core/i_SpiMasterWB/ShiftIn_qb32_3 to i_Core/i_SpiMasterWB/ShiftIn_qb32_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y80.DQ      Tcko                  0.200   i_Core/i_SpiMasterWB/ShiftIn_qb32<3>
                                                       i_Core/i_SpiMasterWB/ShiftIn_qb32_3
    SLICE_X62Y80.D6      net (fanout=4)        0.034   i_Core/i_SpiMasterWB/ShiftIn_qb32<3>
    SLICE_X62Y80.CLK     Tah         (-Th)    -0.190   i_Core/i_SpiMasterWB/ShiftIn_qb32<3>
                                                       i_Core/i_SpiMasterWB/ShiftIn_qb32_3_rstpot
                                                       i_Core/i_SpiMasterWB/ShiftIn_qb32_3
    -------------------------------------------------  ---------------------------
    Total                                      0.424ns (0.390ns logic, 0.034ns route)
                                                       (92.0% logic, 8.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" 25 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 37.500ns (period - min period limit)
  Period: 40.000ns
  Min period limit: 2.500ns (400.000MHz) (Tbcper_I)
  Physical resource: VcTcXo_ik_IBUF_BUFG/I0
  Logical resource: VcTcXo_ik_IBUF_BUFG/I0
  Location pin: BUFGMUX_X3Y16.I0
  Clock network: VcTcXo_ik_IBUF
--------------------------------------------------------------------------------
Slack: 38.601ns (period - min period limit)
  Period: 40.000ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: i_Core/i_Debouncer/BouncingSignal_x<2>/CLK
  Logical resource: i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2/CLK
  Location pin: SLICE_X22Y81.CLK
  Clock network: VcTcXo_ik_IBUF_BUFG
--------------------------------------------------------------------------------
Slack: 38.601ns (period - min period limit)
  Period: 40.000ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: i_Core/i_Debouncer/BouncingSignal_x<2>/CLK
  Logical resource: i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2/CLK
  Location pin: SLICE_X22Y81.CLK
  Clock network: VcTcXo_ik_IBUF_BUFG
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysClk_ik" 40 MHz HIGH 
50%;

 300 paths analyzed, 80 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   2.500ns.
--------------------------------------------------------------------------------

Paths for end point i_Core/VmeSysClkDivider_c_23 (SLICE_X36Y65.CIN), 20 paths
--------------------------------------------------------------------------------
Slack (setup path):     22.874ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_0 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_23 (FF)
  Requirement:          25.000ns
  Data Path Delay:      2.147ns (Levels of Logic = 6)
  Clock Path Skew:      0.056ns (0.901 - 0.845)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_23
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y60.AQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c_0
    SLICE_X36Y60.A5      net (fanout=1)        0.448   i_Core/VmeSysClkDivider_c<0>
    SLICE_X36Y60.COUT    Topcya                0.474   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/Mcount_VmeSysClkDivider_c_lut<0>_INV_0
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.313   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_23
    -------------------------------------------------  ---------------------------
    Total                                      2.147ns (1.684ns logic, 0.463ns route)
                                                       (78.4% logic, 21.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     22.969ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_4 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_23 (FF)
  Requirement:          25.000ns
  Data Path Delay:      2.051ns (Levels of Logic = 5)
  Clock Path Skew:      0.055ns (0.901 - 0.846)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_4 to i_Core/VmeSysClkDivider_c_23
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y61.AQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/VmeSysClkDivider_c_4
    SLICE_X36Y61.A5      net (fanout=1)        0.448   i_Core/VmeSysClkDivider_c<4>
    SLICE_X36Y61.COUT    Topcya                0.474   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/VmeSysClkDivider_c<4>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.313   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_23
    -------------------------------------------------  ---------------------------
    Total                                      2.051ns (1.591ns logic, 0.460ns route)
                                                       (77.6% logic, 22.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     23.044ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_3 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_23 (FF)
  Requirement:          25.000ns
  Data Path Delay:      1.977ns (Levels of Logic = 6)
  Clock Path Skew:      0.056ns (0.901 - 0.845)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_3 to i_Core/VmeSysClkDivider_c_23
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y60.DQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c_3
    SLICE_X36Y60.D5      net (fanout=1)        0.440   i_Core/VmeSysClkDivider_c<3>
    SLICE_X36Y60.COUT    Topcyd                0.312   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c<3>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.313   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_23
    -------------------------------------------------  ---------------------------
    Total                                      1.977ns (1.522ns logic, 0.455ns route)
                                                       (77.0% logic, 23.0% route)

--------------------------------------------------------------------------------

Paths for end point i_Core/VmeSysClkDivider_c_21 (SLICE_X36Y65.CIN), 20 paths
--------------------------------------------------------------------------------
Slack (setup path):     22.884ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_0 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_21 (FF)
  Requirement:          25.000ns
  Data Path Delay:      2.137ns (Levels of Logic = 6)
  Clock Path Skew:      0.056ns (0.901 - 0.845)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y60.AQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c_0
    SLICE_X36Y60.A5      net (fanout=1)        0.448   i_Core/VmeSysClkDivider_c<0>
    SLICE_X36Y60.COUT    Topcya                0.474   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/Mcount_VmeSysClkDivider_c_lut<0>_INV_0
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.303   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_21
    -------------------------------------------------  ---------------------------
    Total                                      2.137ns (1.674ns logic, 0.463ns route)
                                                       (78.3% logic, 21.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     22.979ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_4 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_21 (FF)
  Requirement:          25.000ns
  Data Path Delay:      2.041ns (Levels of Logic = 5)
  Clock Path Skew:      0.055ns (0.901 - 0.846)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_4 to i_Core/VmeSysClkDivider_c_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y61.AQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/VmeSysClkDivider_c_4
    SLICE_X36Y61.A5      net (fanout=1)        0.448   i_Core/VmeSysClkDivider_c<4>
    SLICE_X36Y61.COUT    Topcya                0.474   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/VmeSysClkDivider_c<4>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.303   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_21
    -------------------------------------------------  ---------------------------
    Total                                      2.041ns (1.581ns logic, 0.460ns route)
                                                       (77.5% logic, 22.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     23.054ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_3 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_21 (FF)
  Requirement:          25.000ns
  Data Path Delay:      1.967ns (Levels of Logic = 6)
  Clock Path Skew:      0.056ns (0.901 - 0.845)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_3 to i_Core/VmeSysClkDivider_c_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y60.DQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c_3
    SLICE_X36Y60.D5      net (fanout=1)        0.440   i_Core/VmeSysClkDivider_c<3>
    SLICE_X36Y60.COUT    Topcyd                0.312   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c<3>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.303   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_21
    -------------------------------------------------  ---------------------------
    Total                                      1.967ns (1.512ns logic, 0.455ns route)
                                                       (76.9% logic, 23.1% route)

--------------------------------------------------------------------------------

Paths for end point i_Core/VmeSysClkDivider_c_22 (SLICE_X36Y65.CIN), 20 paths
--------------------------------------------------------------------------------
Slack (setup path):     22.915ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_0 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_22 (FF)
  Requirement:          25.000ns
  Data Path Delay:      2.106ns (Levels of Logic = 6)
  Clock Path Skew:      0.056ns (0.901 - 0.845)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y60.AQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c_0
    SLICE_X36Y60.A5      net (fanout=1)        0.448   i_Core/VmeSysClkDivider_c<0>
    SLICE_X36Y60.COUT    Topcya                0.474   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/Mcount_VmeSysClkDivider_c_lut<0>_INV_0
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.272   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_22
    -------------------------------------------------  ---------------------------
    Total                                      2.106ns (1.643ns logic, 0.463ns route)
                                                       (78.0% logic, 22.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     23.010ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_4 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_22 (FF)
  Requirement:          25.000ns
  Data Path Delay:      2.010ns (Levels of Logic = 5)
  Clock Path Skew:      0.055ns (0.901 - 0.846)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_4 to i_Core/VmeSysClkDivider_c_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y61.AQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/VmeSysClkDivider_c_4
    SLICE_X36Y61.A5      net (fanout=1)        0.448   i_Core/VmeSysClkDivider_c<4>
    SLICE_X36Y61.COUT    Topcya                0.474   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/VmeSysClkDivider_c<4>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.272   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_22
    -------------------------------------------------  ---------------------------
    Total                                      2.010ns (1.550ns logic, 0.460ns route)
                                                       (77.1% logic, 22.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     23.085ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/VmeSysClkDivider_c_3 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_22 (FF)
  Requirement:          25.000ns
  Data Path Delay:      1.936ns (Levels of Logic = 6)
  Clock Path Skew:      0.056ns (0.901 - 0.845)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 0.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Core/VmeSysClkDivider_c_3 to i_Core/VmeSysClkDivider_c_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y60.DQ      Tcko                  0.525   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c_3
    SLICE_X36Y60.D5      net (fanout=1)        0.440   i_Core/VmeSysClkDivider_c<3>
    SLICE_X36Y60.COUT    Topcyd                0.312   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c<3>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<3>
    SLICE_X36Y61.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<7>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<7>
    SLICE_X36Y62.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.COUT    Tbyp                  0.093   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CIN     net (fanout=1)        0.003   i_Core/Mcount_VmeSysClkDivider_c_cy<19>
    SLICE_X36Y65.CLK     Tcinck                0.272   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_22
    -------------------------------------------------  ---------------------------
    Total                                      1.936ns (1.481ns logic, 0.455ns route)
                                                       (76.5% logic, 23.5% route)

--------------------------------------------------------------------------------

Hold Paths: TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysClk_ik" 40 MHz HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point i_Core/VmeSysClkDivider_c_23 (SLICE_X36Y65.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.521ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/VmeSysClkDivider_c_23 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_23 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.521ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         VmeSysClk_ik_BUFGP rising at 25.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Core/VmeSysClkDivider_c_23 to i_Core/VmeSysClkDivider_c_23
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y65.DQ      Tcko                  0.234   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/VmeSysClkDivider_c_23
    SLICE_X36Y65.D6      net (fanout=2)        0.023   i_Core/VmeSysClkDivider_c<23>
    SLICE_X36Y65.CLK     Tah         (-Th)    -0.264   i_Core/VmeSysClkDivider_c<23>
                                                       i_Core/VmeSysClkDivider_c<23>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_xor<23>
                                                       i_Core/VmeSysClkDivider_c_23
    -------------------------------------------------  ---------------------------
    Total                                      0.521ns (0.498ns logic, 0.023ns route)
                                                       (95.6% logic, 4.4% route)

--------------------------------------------------------------------------------

Paths for end point i_Core/VmeSysClkDivider_c_16 (SLICE_X36Y64.CIN), 16 paths
--------------------------------------------------------------------------------
Slack (hold path):      0.526ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/VmeSysClkDivider_c_14 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_16 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.616ns (Levels of Logic = 2)
  Clock Path Skew:      0.090ns (0.606 - 0.516)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 25.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Core/VmeSysClkDivider_c_14 to i_Core/VmeSysClkDivider_c_16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y63.CQ      Tcko                  0.234   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/VmeSysClkDivider_c_14
    SLICE_X36Y63.C5      net (fanout=1)        0.059   i_Core/VmeSysClkDivider_c<14>
    SLICE_X36Y63.COUT    Topcyc                0.203   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/VmeSysClkDivider_c<14>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.001   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CLK     Tckcin      (-Th)    -0.119   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
                                                       i_Core/VmeSysClkDivider_c_16
    -------------------------------------------------  ---------------------------
    Total                                      0.616ns (0.556ns logic, 0.060ns route)
                                                       (90.3% logic, 9.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.558ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/VmeSysClkDivider_c_10 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_16 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.649ns (Levels of Logic = 3)
  Clock Path Skew:      0.091ns (0.606 - 0.515)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 25.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Core/VmeSysClkDivider_c_10 to i_Core/VmeSysClkDivider_c_16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y62.CQ      Tcko                  0.234   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/VmeSysClkDivider_c_10
    SLICE_X36Y62.C5      net (fanout=1)        0.059   i_Core/VmeSysClkDivider_c<10>
    SLICE_X36Y62.COUT    Topcyc                0.203   i_Core/VmeSysClkDivider_c<11>
                                                       i_Core/VmeSysClkDivider_c<10>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.CIN     net (fanout=1)        0.001   i_Core/Mcount_VmeSysClkDivider_c_cy<11>
    SLICE_X36Y63.COUT    Tbyp                  0.032   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.001   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CLK     Tckcin      (-Th)    -0.119   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
                                                       i_Core/VmeSysClkDivider_c_16
    -------------------------------------------------  ---------------------------
    Total                                      0.649ns (0.588ns logic, 0.061ns route)
                                                       (90.6% logic, 9.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.587ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/VmeSysClkDivider_c_13 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_16 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.677ns (Levels of Logic = 2)
  Clock Path Skew:      0.090ns (0.606 - 0.516)
  Source Clock:         VmeSysClk_ik_BUFGP rising at 25.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Core/VmeSysClkDivider_c_13 to i_Core/VmeSysClkDivider_c_16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y63.BQ      Tcko                  0.234   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/VmeSysClkDivider_c_13
    SLICE_X36Y63.B5      net (fanout=1)        0.059   i_Core/VmeSysClkDivider_c<13>
    SLICE_X36Y63.COUT    Topcyb                0.264   i_Core/VmeSysClkDivider_c<15>
                                                       i_Core/VmeSysClkDivider_c<13>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CIN     net (fanout=1)        0.001   i_Core/Mcount_VmeSysClkDivider_c_cy<15>
    SLICE_X36Y64.CLK     Tckcin      (-Th)    -0.119   i_Core/VmeSysClkDivider_c<19>
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<19>
                                                       i_Core/VmeSysClkDivider_c_16
    -------------------------------------------------  ---------------------------
    Total                                      0.677ns (0.617ns logic, 0.060ns route)
                                                       (91.1% logic, 8.9% route)

--------------------------------------------------------------------------------

Paths for end point i_Core/VmeSysClkDivider_c_1 (SLICE_X36Y60.B5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.530ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/VmeSysClkDivider_c_1 (FF)
  Destination:          i_Core/VmeSysClkDivider_c_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.530ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         VmeSysClk_ik_BUFGP rising at 25.000ns
  Destination Clock:    VmeSysClk_ik_BUFGP rising at 25.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Core/VmeSysClkDivider_c_1 to i_Core/VmeSysClkDivider_c_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y60.BQ      Tcko                  0.234   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c_1
    SLICE_X36Y60.B5      net (fanout=1)        0.059   i_Core/VmeSysClkDivider_c<1>
    SLICE_X36Y60.CLK     Tah         (-Th)    -0.237   i_Core/VmeSysClkDivider_c<3>
                                                       i_Core/VmeSysClkDivider_c<1>_rt
                                                       i_Core/Mcount_VmeSysClkDivider_c_cy<3>
                                                       i_Core/VmeSysClkDivider_c_1
    -------------------------------------------------  ---------------------------
    Total                                      0.530ns (0.471ns logic, 0.059ns route)
                                                       (88.9% logic, 11.1% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysClk_ik" 40 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 22.500ns (period - min period limit)
  Period: 25.000ns
  Min period limit: 2.500ns (400.000MHz) (Tbcper_I)
  Physical resource: VmeSysClk_ik_BUFGP/BUFG/I0
  Logical resource: VmeSysClk_ik_BUFGP/BUFG/I0
  Location pin: BUFGMUX_X2Y10.I0
  Clock network: VmeSysClk_ik_BUFGP/IBUFG
--------------------------------------------------------------------------------
Slack: 24.520ns (period - min period limit)
  Period: 25.000ns
  Min period limit: 0.480ns (2083.333MHz) (Tcp)
  Physical resource: i_Core/VmeSysClkDivider_c<3>/CLK
  Logical resource: i_Core/VmeSysClkDivider_c_0/CK
  Location pin: SLICE_X36Y60.CLK
  Clock network: VmeSysClk_ik_BUFGP
--------------------------------------------------------------------------------
Slack: 24.520ns (period - min period limit)
  Period: 25.000ns
  Min period limit: 0.480ns (2083.333MHz) (Tcp)
  Physical resource: i_Core/VmeSysClkDivider_c<3>/CLK
  Logical resource: i_Core/VmeSysClkDivider_c_1/CK
  Location pin: SLICE_X36Y60.CLK
  Clock network: VmeSysClk_ik_BUFGP
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 100 MHz HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.500ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 100 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 7.500ns (period - min period limit)
  Period: 10.000ns
  Min period limit: 2.500ns (400.000MHz) (Tbcper_I)
  Physical resource: Si57x_BUFG/I0
  Logical resource: Si57x_BUFG/I0
  Location pin: BUFGMUX_X2Y4.I0
  Clock network: Si57x
--------------------------------------------------------------------------------
Slack: 9.520ns (period - min period limit)
  Period: 10.000ns
  Min period limit: 0.480ns (2083.333MHz) (Tcp)
  Physical resource: i_Core/Si57xDivider_c<3>/CLK
  Logical resource: i_Core/Si57xDivider_c_0/CK
  Location pin: SLICE_X36Y102.CLK
  Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
Slack: 9.520ns (period - min period limit)
  Period: 10.000ns
  Min period limit: 0.480ns (2083.333MHz) (Tcp)
  Physical resource: i_Core/Si57xDivider_c<3>/CLK
  Logical resource: i_Core/Si57xDivider_c_1/CK
  Location pin: SLICE_X36Y102.CLK
  Clock network: Si57x_BUFG
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 100 MHz HIGH 50%;

 300 paths analyzed, 80 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   2.500ns.
--------------------------------------------------------------------------------

Paths for end point i_Core/Si57xDivider_c_23 (SLICE_X36Y107.CIN), 20 paths
--------------------------------------------------------------------------------
Slack (setup path):     7.730ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_0 (FF)
  Destination:          i_Core/Si57xDivider_c_23 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.226ns (Levels of Logic = 6)
  Clock Path Skew:      -0.009ns (0.249 - 0.258)
1154
  Source Clock:         Si57x_BUFG rising at 0.000ns
1155
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1156 1157 1158 1159 1160 1161 1162 1163
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1164
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_23
1165 1166 1167
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
    SLICE_X36Y102.AQ     Tcko                  0.525   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c_0
    SLICE_X36Y102.A5     net (fanout=1)        0.448   i_Core/Si57xDivider_c<0>
    SLICE_X36Y102.COUT   Topcya                0.474   i_Core/Si57xDivider_c<3>
                                                       i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0
                                                       i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<7>
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.313   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_23
1190
    -------------------------------------------------  ---------------------------
1191 1192
    Total                                      2.226ns (1.684ns logic, 0.542ns route)
                                                       (75.7% logic, 24.3% route)
1193 1194

--------------------------------------------------------------------------------
1195 1196 1197 1198 1199 1200
Slack (setup path):     7.828ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_4 (FF)
  Destination:          i_Core/Si57xDivider_c_23 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.130ns (Levels of Logic = 5)
  Clock Path Skew:      -0.007ns (0.249 - 0.256)
1201
  Source Clock:         Si57x_BUFG rising at 0.000ns
1202
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1203 1204 1205 1206 1207 1208 1209 1210
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1211
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_4 to i_Core/Si57xDivider_c_23
1212 1213 1214
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
    SLICE_X36Y103.AQ     Tcko                  0.525   i_Core/Si57xDivider_c<7>
                                                       i_Core/Si57xDivider_c_4
    SLICE_X36Y103.A5     net (fanout=1)        0.448   i_Core/Si57xDivider_c<4>
    SLICE_X36Y103.COUT   Topcya                0.474   i_Core/Si57xDivider_c<7>
                                                       i_Core/Si57xDivider_c<4>_rt
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.313   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_23
1234
    -------------------------------------------------  ---------------------------
1235 1236
    Total                                      2.130ns (1.591ns logic, 0.539ns route)
                                                       (74.7% logic, 25.3% route)
1237 1238

--------------------------------------------------------------------------------
1239 1240 1241 1242 1243 1244
Slack (setup path):     7.900ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_3 (FF)
  Destination:          i_Core/Si57xDivider_c_23 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.056ns (Levels of Logic = 6)
  Clock Path Skew:      -0.009ns (0.249 - 0.258)
1245
  Source Clock:         Si57x_BUFG rising at 0.000ns
1246
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1247 1248 1249 1250 1251 1252 1253 1254
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1255
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_3 to i_Core/Si57xDivider_c_23
1256 1257 1258
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
    SLICE_X36Y102.DQ     Tcko                  0.525   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c_3
    SLICE_X36Y102.D5     net (fanout=1)        0.440   i_Core/Si57xDivider_c<3>
    SLICE_X36Y102.COUT   Topcyd                0.312   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c<3>_rt
                                                       i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<7>
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.313   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_23
1281
    -------------------------------------------------  ---------------------------
1282 1283
    Total                                      2.056ns (1.522ns logic, 0.534ns route)
                                                       (74.0% logic, 26.0% route)
1284 1285 1286

--------------------------------------------------------------------------------

1287
Paths for end point i_Core/Si57xDivider_c_21 (SLICE_X36Y107.CIN), 20 paths
1288
--------------------------------------------------------------------------------
1289 1290 1291 1292 1293 1294
Slack (setup path):     7.740ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_0 (FF)
  Destination:          i_Core/Si57xDivider_c_21 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.216ns (Levels of Logic = 6)
  Clock Path Skew:      -0.009ns (0.249 - 0.258)
1295
  Source Clock:         Si57x_BUFG rising at 0.000ns
1296
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1297 1298 1299 1300 1301 1302 1303 1304
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1305
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_21
1306 1307 1308
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330
    SLICE_X36Y102.AQ     Tcko                  0.525   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c_0
    SLICE_X36Y102.A5     net (fanout=1)        0.448   i_Core/Si57xDivider_c<0>
    SLICE_X36Y102.COUT   Topcya                0.474   i_Core/Si57xDivider_c<3>
                                                       i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0
                                                       i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<7>
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.303   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_21
1331
    -------------------------------------------------  ---------------------------
1332 1333
    Total                                      2.216ns (1.674ns logic, 0.542ns route)
                                                       (75.5% logic, 24.5% route)
1334 1335

--------------------------------------------------------------------------------
1336 1337 1338 1339 1340 1341
Slack (setup path):     7.838ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_4 (FF)
  Destination:          i_Core/Si57xDivider_c_21 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.120ns (Levels of Logic = 5)
  Clock Path Skew:      -0.007ns (0.249 - 0.256)
1342
  Source Clock:         Si57x_BUFG rising at 0.000ns
1343
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1344 1345 1346 1347 1348 1349 1350 1351
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1352
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_4 to i_Core/Si57xDivider_c_21
1353 1354 1355
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374
    SLICE_X36Y103.AQ     Tcko                  0.525   i_Core/Si57xDivider_c<7>
                                                       i_Core/Si57xDivider_c_4
    SLICE_X36Y103.A5     net (fanout=1)        0.448   i_Core/Si57xDivider_c<4>
    SLICE_X36Y103.COUT   Topcya                0.474   i_Core/Si57xDivider_c<7>
                                                       i_Core/Si57xDivider_c<4>_rt
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.303   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_21
1375
    -------------------------------------------------  ---------------------------
1376 1377
    Total                                      2.120ns (1.581ns logic, 0.539ns route)
                                                       (74.6% logic, 25.4% route)
1378 1379

--------------------------------------------------------------------------------
1380 1381 1382 1383 1384 1385
Slack (setup path):     7.910ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_3 (FF)
  Destination:          i_Core/Si57xDivider_c_21 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.046ns (Levels of Logic = 6)
  Clock Path Skew:      -0.009ns (0.249 - 0.258)
1386
  Source Clock:         Si57x_BUFG rising at 0.000ns
1387
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1388 1389 1390 1391 1392 1393 1394 1395
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1396
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_3 to i_Core/Si57xDivider_c_21
1397 1398 1399
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421
    SLICE_X36Y102.DQ     Tcko                  0.525   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c_3
    SLICE_X36Y102.D5     net (fanout=1)        0.440   i_Core/Si57xDivider_c<3>
    SLICE_X36Y102.COUT   Topcyd                0.312   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c<3>_rt
                                                       i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<7>
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.303   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_21
1422
    -------------------------------------------------  ---------------------------
1423 1424
    Total                                      2.046ns (1.512ns logic, 0.534ns route)
                                                       (73.9% logic, 26.1% route)
1425 1426 1427

--------------------------------------------------------------------------------

1428
Paths for end point i_Core/Si57xDivider_c_22 (SLICE_X36Y107.CIN), 20 paths
1429
--------------------------------------------------------------------------------
1430 1431 1432 1433 1434 1435
Slack (setup path):     7.771ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_0 (FF)
  Destination:          i_Core/Si57xDivider_c_22 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.185ns (Levels of Logic = 6)
  Clock Path Skew:      -0.009ns (0.249 - 0.258)
1436
  Source Clock:         Si57x_BUFG rising at 0.000ns
1437
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1438 1439 1440 1441 1442 1443 1444 1445
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1446
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_22
1447 1448 1449
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
    SLICE_X36Y102.AQ     Tcko                  0.525   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c_0
    SLICE_X36Y102.A5     net (fanout=1)        0.448   i_Core/Si57xDivider_c<0>
    SLICE_X36Y102.COUT   Topcya                0.474   i_Core/Si57xDivider_c<3>
                                                       i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0
                                                       i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<7>
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.272   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_22
1472
    -------------------------------------------------  ---------------------------
1473 1474
    Total                                      2.185ns (1.643ns logic, 0.542ns route)
                                                       (75.2% logic, 24.8% route)
1475 1476

--------------------------------------------------------------------------------
1477 1478 1479 1480 1481 1482
Slack (setup path):     7.869ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_4 (FF)
  Destination:          i_Core/Si57xDivider_c_22 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.089ns (Levels of Logic = 5)
  Clock Path Skew:      -0.007ns (0.249 - 0.256)
1483
  Source Clock:         Si57x_BUFG rising at 0.000ns
1484
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1485 1486 1487 1488 1489 1490 1491 1492
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1493
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_4 to i_Core/Si57xDivider_c_22
1494 1495 1496
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515
    SLICE_X36Y103.AQ     Tcko                  0.525   i_Core/Si57xDivider_c<7>
                                                       i_Core/Si57xDivider_c_4
    SLICE_X36Y103.A5     net (fanout=1)        0.448   i_Core/Si57xDivider_c<4>
    SLICE_X36Y103.COUT   Topcya                0.474   i_Core/Si57xDivider_c<7>
                                                       i_Core/Si57xDivider_c<4>_rt
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.272   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_22
1516
    -------------------------------------------------  ---------------------------
1517 1518
    Total                                      2.089ns (1.550ns logic, 0.539ns route)
                                                       (74.2% logic, 25.8% route)
1519 1520

--------------------------------------------------------------------------------
1521 1522 1523 1524 1525 1526
Slack (setup path):     7.941ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Core/Si57xDivider_c_3 (FF)
  Destination:          i_Core/Si57xDivider_c_22 (FF)
  Requirement:          10.000ns
  Data Path Delay:      2.015ns (Levels of Logic = 6)
  Clock Path Skew:      -0.009ns (0.249 - 0.258)
1527
  Source Clock:         Si57x_BUFG rising at 0.000ns
1528
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1529 1530 1531 1532 1533 1534 1535 1536
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1537
  Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_3 to i_Core/Si57xDivider_c_22
1538 1539 1540
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
    SLICE_X36Y102.DQ     Tcko                  0.525   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c_3
    SLICE_X36Y102.D5     net (fanout=1)        0.440   i_Core/Si57xDivider_c<3>
    SLICE_X36Y102.COUT   Topcyd                0.312   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c<3>_rt
                                                       i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<3>
    SLICE_X36Y103.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<7>
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.CIN    net (fanout=1)        0.082   i_Core/Mcount_Si57xDivider_c_cy<7>
    SLICE_X36Y104.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<11>
                                                       i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<11>
    SLICE_X36Y105.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<15>
                                                       i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<15>
    SLICE_X36Y106.COUT   Tbyp                  0.093   i_Core/Si57xDivider_c<19>
                                                       i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CIN    net (fanout=1)        0.003   i_Core/Mcount_Si57xDivider_c_cy<19>
    SLICE_X36Y107.CLK    Tcinck                0.272   i_Core/Si57xDivider_c<23>
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_22
1563
    -------------------------------------------------  ---------------------------
1564 1565
    Total                                      2.015ns (1.481ns logic, 0.534ns route)
                                                       (73.5% logic, 26.5% route)
1566 1567 1568

--------------------------------------------------------------------------------

1569
Hold Paths: TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 100 MHz HIGH 50%;
1570 1571
--------------------------------------------------------------------------------

1572
Paths for end point i_Core/Si57xDivider_c_23 (SLICE_X36Y107.D6), 1 path
1573
--------------------------------------------------------------------------------
1574 1575 1576
Slack (hold path):      0.521ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/Si57xDivider_c_23 (FF)
  Destination:          i_Core/Si57xDivider_c_23 (FF)
1577
  Requirement:          0.000ns
1578 1579 1580 1581
  Data Path Delay:      0.521ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         Si57x_BUFG rising at 10.000ns
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1582 1583
  Clock Uncertainty:    0.000ns

1584
  Minimum Data Path at Fast Process Corner: i_Core/Si57xDivider_c_23 to i_Core/Si57xDivider_c_23
1585 1586 1587
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1588 1589 1590 1591 1592 1593 1594
    SLICE_X36Y107.DQ     Tcko                  0.234   i_Core/Si57xDivider_c<23>
                                                       i_Core/Si57xDivider_c_23
    SLICE_X36Y107.D6     net (fanout=2)        0.023   i_Core/Si57xDivider_c<23>
    SLICE_X36Y107.CLK    Tah         (-Th)    -0.264   i_Core/Si57xDivider_c<23>
                                                       i_Core/Si57xDivider_c<23>_rt
                                                       i_Core/Mcount_Si57xDivider_c_xor<23>
                                                       i_Core/Si57xDivider_c_23
1595
    -------------------------------------------------  ---------------------------
1596 1597
    Total                                      0.521ns (0.498ns logic, 0.023ns route)
                                                       (95.6% logic, 4.4% route)
1598 1599 1600

--------------------------------------------------------------------------------

1601
Paths for end point i_Core/Si57xDivider_c_1 (SLICE_X36Y102.B5), 1 path
1602
--------------------------------------------------------------------------------
1603 1604 1605
Slack (hold path):      0.530ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/Si57xDivider_c_1 (FF)
  Destination:          i_Core/Si57xDivider_c_1 (FF)
1606
  Requirement:          0.000ns
1607 1608 1609 1610
  Data Path Delay:      0.530ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         Si57x_BUFG rising at 10.000ns
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1611 1612
  Clock Uncertainty:    0.000ns

1613
  Minimum Data Path at Fast Process Corner: i_Core/Si57xDivider_c_1 to i_Core/Si57xDivider_c_1
1614 1615 1616
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1617 1618 1619 1620 1621 1622 1623
    SLICE_X36Y102.BQ     Tcko                  0.234   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c_1
    SLICE_X36Y102.B5     net (fanout=1)        0.059   i_Core/Si57xDivider_c<1>
    SLICE_X36Y102.CLK    Tah         (-Th)    -0.237   i_Core/Si57xDivider_c<3>
                                                       i_Core/Si57xDivider_c<1>_rt
                                                       i_Core/Mcount_Si57xDivider_c_cy<3>
                                                       i_Core/Si57xDivider_c_1
1624
    -------------------------------------------------  ---------------------------
1625 1626
    Total                                      0.530ns (0.471ns logic, 0.059ns route)
                                                       (88.9% logic, 11.1% route)
1627 1628 1629

--------------------------------------------------------------------------------

1630
Paths for end point i_Core/Si57xDivider_c_5 (SLICE_X36Y103.B5), 1 path
1631
--------------------------------------------------------------------------------
1632 1633 1634
Slack (hold path):      0.530ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/Si57xDivider_c_5 (FF)
  Destination:          i_Core/Si57xDivider_c_5 (FF)
1635
  Requirement:          0.000ns
1636 1637 1638 1639
  Data Path Delay:      0.530ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         Si57x_BUFG rising at 10.000ns
  Destination Clock:    Si57x_BUFG rising at 10.000ns
1640 1641
  Clock Uncertainty:    0.000ns

1642
  Minimum Data Path at Fast Process Corner: i_Core/Si57xDivider_c_5 to i_Core/Si57xDivider_c_5
1643 1644 1645
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1646 1647 1648 1649 1650 1651 1652
    SLICE_X36Y103.BQ     Tcko                  0.234   i_Core/Si57xDivider_c<7>
                                                       i_Core/Si57xDivider_c_5
    SLICE_X36Y103.B5     net (fanout=1)        0.059   i_Core/Si57xDivider_c<5>
    SLICE_X36Y103.CLK    Tah         (-Th)    -0.237   i_Core/Si57xDivider_c<7>
                                                       i_Core/Si57xDivider_c<5>_rt
                                                       i_Core/Mcount_Si57xDivider_c_cy<7>
                                                       i_Core/Si57xDivider_c_5
1653
    -------------------------------------------------  ---------------------------
1654 1655
    Total                                      0.530ns (0.471ns logic, 0.059ns route)
                                                       (88.9% logic, 11.1% route)
1656 1657 1658

--------------------------------------------------------------------------------

1659
Component Switching Limit Checks: TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 100 MHz HIGH 50%;
1660
--------------------------------------------------------------------------------
1661 1662
Slack: 7.500ns (period - min period limit)
  Period: 10.000ns
1663 1664 1665 1666 1667 1668
  Min period limit: 2.500ns (400.000MHz) (Tbcper_I)
  Physical resource: Si57x_BUFG/I0
  Logical resource: Si57x_BUFG/I0
  Location pin: BUFGMUX_X2Y4.I0
  Clock network: Si57x
--------------------------------------------------------------------------------
1669 1670 1671 1672 1673 1674
Slack: 9.520ns (period - min period limit)
  Period: 10.000ns
  Min period limit: 0.480ns (2083.333MHz) (Tcp)
  Physical resource: i_Core/Si57xDivider_c<3>/CLK
  Logical resource: i_Core/Si57xDivider_c_0/CK
  Location pin: SLICE_X36Y102.CLK
1675 1676
  Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
1677 1678 1679 1680 1681 1682
Slack: 9.520ns (period - min period limit)
  Period: 10.000ns
  Min period limit: 0.480ns (2083.333MHz) (Tcp)
  Physical resource: i_Core/Si57xDivider_c<3>/CLK
  Logical resource: i_Core/Si57xDivider_c_1/CK
  Location pin: SLICE_X36Y102.CLK
1683 1684 1685
  Clock network: Si57x_BUFG
--------------------------------------------------------------------------------

1686
================================================================================
1687
Timing constraint: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 100 MHz HIGH 
1688 1689 1690 1691
50%;

 129 paths analyzed, 97 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
1692
 Minimum period is   4.909ns.
1693 1694
--------------------------------------------------------------------------------

1695
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_20 (SLICE_X68Y84.CE), 2 paths
1696
--------------------------------------------------------------------------------
1697
Slack (setup path):     5.091ns (requirement - (data path - clock path skew + uncertainty))
1698
  Source:               i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
1699 1700 1701 1702
  Destination:          i_Core/i_Slv2SerWB/Dat_xb32_20 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.672ns (Levels of Logic = 1)
  Clock Path Skew:      -0.202ns (0.861 - 1.063)
1703
  Source Clock:         SysAppClk_ik_BUFGP rising at 0.000ns
1704
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1705 1706 1707 1708 1709 1710 1711 1712
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1713
  Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_20
1714 1715 1716
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1717
    SLICE_X42Y103.CQ     Tcko                  0.476   i_Core/i_Slv2SerWB/AckI_d3<2>
1718
                                                       i_Core/i_Slv2SerWB/AckI_d3_2
1719 1720
    SLICE_X59Y103.A3     net (fanout=1)        1.255   i_Core/i_Slv2SerWB/AckI_d3<2>
    SLICE_X59Y103.A      Tilo                  0.259   i_Core/i_Slv2SerWB/Dat_xb32<3>
1721
                                                       i_Core/i_Slv2SerWB/NewAckI_a<2>1
1722 1723 1724
    SLICE_X68Y84.CE      net (fanout=7)        2.369   i_Core/i_Slv2SerWB/NewAckI_a
    SLICE_X68Y84.CLK     Tceck                 0.313   i_Core/i_Slv2SerWB/Dat_xb32<23>
                                                       i_Core/i_Slv2SerWB/Dat_xb32_20
1725
    -------------------------------------------------  ---------------------------
1726 1727
    Total                                      4.672ns (1.048ns logic, 3.624ns route)
                                                       (22.4% logic, 77.6% route)
1728 1729

--------------------------------------------------------------------------------
1730
Slack (setup path):     5.179ns (requirement - (data path - clock path skew + uncertainty))
1731
  Source:               i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
1732 1733 1734 1735
  Destination:          i_Core/i_Slv2SerWB/Dat_xb32_20 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.584ns (Levels of Logic = 1)
  Clock Path Skew:      -0.202ns (0.861 - 1.063)
1736
  Source Clock:         SysAppClk_ik_BUFGP rising at 0.000ns
1737
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1738 1739 1740 1741 1742 1743 1744 1745
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1746
  Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_20
1747 1748 1749
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1750
    SLICE_X42Y103.BQ     Tcko                  0.476   i_Core/i_Slv2SerWB/AckI_d3<2>
1751
                                                       i_Core/i_Slv2SerWB/AckI_d3_1
1752 1753
    SLICE_X59Y103.A4     net (fanout=2)        1.167   i_Core/i_Slv2SerWB/AckI_d3<1>
    SLICE_X59Y103.A      Tilo                  0.259   i_Core/i_Slv2SerWB/Dat_xb32<3>
1754
                                                       i_Core/i_Slv2SerWB/NewAckI_a<2>1
1755 1756 1757
    SLICE_X68Y84.CE      net (fanout=7)        2.369   i_Core/i_Slv2SerWB/NewAckI_a
    SLICE_X68Y84.CLK     Tceck                 0.313   i_Core/i_Slv2SerWB/Dat_xb32<23>
                                                       i_Core/i_Slv2SerWB/Dat_xb32_20
1758
    -------------------------------------------------  ---------------------------
1759 1760
    Total                                      4.584ns (1.048ns logic, 3.536ns route)
                                                       (22.9% logic, 77.1% route)
1761 1762 1763

--------------------------------------------------------------------------------

1764
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_22 (SLICE_X68Y84.CE), 2 paths
1765
--------------------------------------------------------------------------------
1766
Slack (setup path):     5.135ns (requirement - (data path - clock path skew + uncertainty))
1767
  Source:               i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
1768 1769 1770 1771
  Destination:          i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.628ns (Levels of Logic = 1)
  Clock Path Skew:      -0.202ns (0.861 - 1.063)
1772
  Source Clock:         SysAppClk_ik_BUFGP rising at 0.000ns
1773
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1774 1775 1776 1777 1778 1779 1780 1781
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1782
  Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_22
1783 1784 1785
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1786
    SLICE_X42Y103.CQ     Tcko                  0.476   i_Core/i_Slv2SerWB/AckI_d3<2>
1787
                                                       i_Core/i_Slv2SerWB/AckI_d3_2
1788 1789
    SLICE_X59Y103.A3     net (fanout=1)        1.255   i_Core/i_Slv2SerWB/AckI_d3<2>
    SLICE_X59Y103.A      Tilo                  0.259   i_Core/i_Slv2SerWB/Dat_xb32<3>
1790
                                                       i_Core/i_Slv2SerWB/NewAckI_a<2>1
1791 1792 1793
    SLICE_X68Y84.CE      net (fanout=7)        2.369   i_Core/i_Slv2SerWB/NewAckI_a
    SLICE_X68Y84.CLK     Tceck                 0.269   i_Core/i_Slv2SerWB/Dat_xb32<23>
                                                       i_Core/i_Slv2SerWB/Dat_xb32_22
1794
    -------------------------------------------------  ---------------------------
1795 1796
    Total                                      4.628ns (1.004ns logic, 3.624ns route)
                                                       (21.7% logic, 78.3% route)
1797 1798

--------------------------------------------------------------------------------
1799
Slack (setup path):     5.223ns (requirement - (data path - clock path skew + uncertainty))
1800
  Source:               i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
1801 1802 1803 1804
  Destination:          i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.540ns (Levels of Logic = 1)
  Clock Path Skew:      -0.202ns (0.861 - 1.063)
1805
  Source Clock:         SysAppClk_ik_BUFGP rising at 0.000ns
1806
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1807 1808 1809 1810 1811 1812 1813 1814
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1815
  Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_22
1816 1817 1818
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1819
    SLICE_X42Y103.BQ     Tcko                  0.476   i_Core/i_Slv2SerWB/AckI_d3<2>
1820
                                                       i_Core/i_Slv2SerWB/AckI_d3_1
1821 1822
    SLICE_X59Y103.A4     net (fanout=2)        1.167   i_Core/i_Slv2SerWB/AckI_d3<1>
    SLICE_X59Y103.A      Tilo                  0.259   i_Core/i_Slv2SerWB/Dat_xb32<3>
1823
                                                       i_Core/i_Slv2SerWB/NewAckI_a<2>1
1824 1825 1826
    SLICE_X68Y84.CE      net (fanout=7)        2.369   i_Core/i_Slv2SerWB/NewAckI_a
    SLICE_X68Y84.CLK     Tceck                 0.269   i_Core/i_Slv2SerWB/Dat_xb32<23>
                                                       i_Core/i_Slv2SerWB/Dat_xb32_22
1827
    -------------------------------------------------  ---------------------------
1828 1829
    Total                                      4.540ns (1.004ns logic, 3.536ns route)
                                                       (22.1% logic, 77.9% route)
1830 1831 1832

--------------------------------------------------------------------------------

1833
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_23 (SLICE_X68Y84.CE), 2 paths
1834
--------------------------------------------------------------------------------
1835
Slack (setup path):     5.138ns (requirement - (data path - clock path skew + uncertainty))
1836
  Source:               i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
1837 1838 1839 1840
  Destination:          i_Core/i_Slv2SerWB/Dat_xb32_23 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.625ns (Levels of Logic = 1)
  Clock Path Skew:      -0.202ns (0.861 - 1.063)
1841
  Source Clock:         SysAppClk_ik_BUFGP rising at 0.000ns
1842
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1843 1844 1845 1846 1847 1848 1849 1850
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1851
  Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_23
1852 1853 1854
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1855
    SLICE_X42Y103.CQ     Tcko                  0.476   i_Core/i_Slv2SerWB/AckI_d3<2>
1856
                                                       i_Core/i_Slv2SerWB/AckI_d3_2
1857 1858
    SLICE_X59Y103.A3     net (fanout=1)        1.255   i_Core/i_Slv2SerWB/AckI_d3<2>
    SLICE_X59Y103.A      Tilo                  0.259   i_Core/i_Slv2SerWB/Dat_xb32<3>
1859
                                                       i_Core/i_Slv2SerWB/NewAckI_a<2>1
1860 1861 1862
    SLICE_X68Y84.CE      net (fanout=7)        2.369   i_Core/i_Slv2SerWB/NewAckI_a
    SLICE_X68Y84.CLK     Tceck                 0.266   i_Core/i_Slv2SerWB/Dat_xb32<23>
                                                       i_Core/i_Slv2SerWB/Dat_xb32_23
1863
    -------------------------------------------------  ---------------------------
1864 1865
    Total                                      4.625ns (1.001ns logic, 3.624ns route)
                                                       (21.6% logic, 78.4% route)
1866 1867

--------------------------------------------------------------------------------
1868
Slack (setup path):     5.226ns (requirement - (data path - clock path skew + uncertainty))
1869
  Source:               i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
1870 1871 1872 1873
  Destination:          i_Core/i_Slv2SerWB/Dat_xb32_23 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.537ns (Levels of Logic = 1)
  Clock Path Skew:      -0.202ns (0.861 - 1.063)
1874
  Source Clock:         SysAppClk_ik_BUFGP rising at 0.000ns
1875
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1876 1877 1878 1879 1880 1881 1882 1883
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

1884
  Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_23
1885 1886 1887
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1888
    SLICE_X42Y103.BQ     Tcko                  0.476   i_Core/i_Slv2SerWB/AckI_d3<2>
1889
                                                       i_Core/i_Slv2SerWB/AckI_d3_1
1890 1891
    SLICE_X59Y103.A4     net (fanout=2)        1.167   i_Core/i_Slv2SerWB/AckI_d3<1>
    SLICE_X59Y103.A      Tilo                  0.259   i_Core/i_Slv2SerWB/Dat_xb32<3>
1892
                                                       i_Core/i_Slv2SerWB/NewAckI_a<2>1
1893 1894 1895
    SLICE_X68Y84.CE      net (fanout=7)        2.369   i_Core/i_Slv2SerWB/NewAckI_a
    SLICE_X68Y84.CLK     Tceck                 0.266   i_Core/i_Slv2SerWB/Dat_xb32<23>
                                                       i_Core/i_Slv2SerWB/Dat_xb32_23
1896
    -------------------------------------------------  ---------------------------
1897 1898
    Total                                      4.537ns (1.001ns logic, 3.536ns route)
                                                       (22.1% logic, 77.9% route)
1899 1900 1901

--------------------------------------------------------------------------------

1902
Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 100 MHz HIGH 50%;
1903 1904
--------------------------------------------------------------------------------

1905
Paths for end point i_Core/i_Slv2SerWB/DatInShReg_b32_2 (SLICE_X58Y103.C4), 1 path
1906
--------------------------------------------------------------------------------
1907 1908 1909
Slack (hold path):      0.482ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/i_Slv2SerWB/DatInShReg_b32_3 (FF)
  Destination:          i_Core/i_Slv2SerWB/DatInShReg_b32_2 (FF)
1910
  Requirement:          0.000ns
1911
  Data Path Delay:      0.482ns (Levels of Logic = 1)
1912
  Clock Path Skew:      0.000ns
1913 1914
  Source Clock:         SysAppClk_ik_BUFGP rising at 10.000ns
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1915 1916
  Clock Uncertainty:    0.000ns

1917
  Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_3 to i_Core/i_Slv2SerWB/DatInShReg_b32_2
1918 1919 1920
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1921 1922 1923 1924 1925 1926
    SLICE_X58Y103.DMUX   Tshcko                0.238   i_Core/i_Slv2SerWB/DatInShReg_b32<7>
                                                       i_Core/i_Slv2SerWB/DatInShReg_b32_3
    SLICE_X58Y103.C4     net (fanout=2)        0.123   i_Core/i_Slv2SerWB/DatInShReg_b32<3>
    SLICE_X58Y103.CLK    Tah         (-Th)    -0.121   i_Core/i_Slv2SerWB/DatInShReg_b32<7>
                                                       i_Core/i_Slv2SerWB/DatInShReg_b32<3>_rt
                                                       i_Core/i_Slv2SerWB/DatInShReg_b32_2
1927
    -------------------------------------------------  ---------------------------
1928 1929
    Total                                      0.482ns (0.359ns logic, 0.123ns route)
                                                       (74.5% logic, 25.5% route)
1930 1931 1932

--------------------------------------------------------------------------------

1933
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_0 (SLICE_X59Y103.AX), 1 path
1934
--------------------------------------------------------------------------------
1935 1936 1937
Slack (hold path):      0.490ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Core/i_Slv2SerWB/DatInShReg_b32_0 (FF)
  Destination:          i_Core/i_Slv2SerWB/Dat_xb32_0 (FF)
1938
  Requirement:          0.000ns
1939 1940 1941 1942
  Data Path Delay:      0.492ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.031 - 0.029)
  Source Clock:         SysAppClk_ik_BUFGP rising at 10.000ns
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1943 1944
  Clock Uncertainty:    0.000ns

1945
  Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_0 to i_Core/i_Slv2SerWB/Dat_xb32_0
1946 1947 1948
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1949 1950 1951 1952 1953
    SLICE_X58Y103.AMUX   Tshcko                0.238   i_Core/i_Slv2SerWB/DatInShReg_b32<7>
                                                       i_Core/i_Slv2SerWB/DatInShReg_b32_0
    SLICE_X59Y103.AX     net (fanout=1)        0.195   i_Core/i_Slv2SerWB/DatInShReg_b32<0>
    SLICE_X59Y103.CLK    Tckdi       (-Th)    -0.059   i_Core/i_Slv2SerWB/Dat_xb32<3>
                                                       i_Core/i_Slv2SerWB/Dat_xb32_0
1954
    -------------------------------------------------  ---------------------------
1955 1956
    Total                                      0.492ns (0.297ns logic, 0.195ns route)
                                                       (60.4% logic, 39.6% route)
1957 1958 1959

--------------------------------------------------------------------------------

1960
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_23 (SLICE_X68Y84.DX), 1 path
1961
--------------------------------------------------------------------------------
1962
Slack (hold path):      0.505ns (requirement - (clock path skew + uncertainty - data path))
1963 1964
  Source:               i_Core/i_Slv2SerWB/DatInShReg_b32_23 (FF)
  Destination:          i_Core/i_Slv2SerWB/Dat_xb32_23 (FF)
1965
  Requirement:          0.000ns
1966 1967 1968 1969
  Data Path Delay:      0.512ns (Levels of Logic = 0)
  Clock Path Skew:      0.007ns (0.039 - 0.032)
  Source Clock:         SysAppClk_ik_BUFGP rising at 10.000ns
  Destination Clock:    SysAppClk_ik_BUFGP rising at 10.000ns
1970 1971
  Clock Uncertainty:    0.000ns

1972
  Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_23 to i_Core/i_Slv2SerWB/Dat_xb32_23
1973 1974 1975
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
1976
    SLICE_X68Y86.DQ      Tcko                  0.234   i_Core/i_Slv2SerWB/DatInShReg_b32<23>
1977
                                                       i_Core/i_Slv2SerWB/DatInShReg_b32_23
1978 1979
    SLICE_X68Y84.DX      net (fanout=2)        0.237   i_Core/i_Slv2SerWB/DatInShReg_b32<23>
    SLICE_X68Y84.CLK     Tckdi       (-Th)    -0.041   i_Core/i_Slv2SerWB/Dat_xb32<23>
1980
                                                       i_Core/i_Slv2SerWB/Dat_xb32_23
1981
    -------------------------------------------------  ---------------------------
1982 1983
    Total                                      0.512ns (0.275ns logic, 0.237ns route)
                                                       (53.7% logic, 46.3% route)
1984 1985 1986

--------------------------------------------------------------------------------

1987
Component Switching Limit Checks: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 100 MHz HIGH 50%;
1988
--------------------------------------------------------------------------------
1989 1990
Slack: 7.500ns (period - min period limit)
  Period: 10.000ns
1991 1992 1993 1994 1995 1996
  Min period limit: 2.500ns (400.000MHz) (Tbcper_I)
  Physical resource: SysAppClk_ik_BUFGP/BUFG/I0
  Logical resource: SysAppClk_ik_BUFGP/BUFG/I0
  Location pin: BUFGMUX_X3Y14.I0
  Clock network: SysAppClk_ik_BUFGP/IBUFG
--------------------------------------------------------------------------------
1997 1998
Slack: 9.520ns (period - min period limit)
  Period: 10.000ns
1999
  Min period limit: 0.480ns (2083.333MHz) (Tcp)
2000 2001 2002
  Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<31>/CLK
  Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_28/CK
  Location pin: SLICE_X48Y91.CLK
2003 2004
  Clock network: SysAppClk_ik_BUFGP
--------------------------------------------------------------------------------
2005 2006
Slack: 9.520ns (period - min period limit)
  Period: 10.000ns
2007
  Min period limit: 0.480ns (2083.333MHz) (Tcp)
2008 2009 2010
  Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<31>/CLK
  Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_29/CK
  Location pin: SLICE_X48Y91.CLK
2011 2012 2013
  Clock network: SysAppClk_ik_BUFGP
--------------------------------------------------------------------------------

2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock Si57x_ik
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
2027 2028
Si57x_ik       |    2.270|         |         |         |
Si57x_ikn      |    2.270|         |         |         |
2029 2030 2031 2032 2033 2034 2035
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock Si57x_ikn
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
2036 2037
Si57x_ik       |    2.270|         |         |         |
Si57x_ikn      |    2.270|         |         |         |
2038 2039 2040 2041 2042 2043 2044
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock SysAppClk_ik
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061
SysAppClk_ik   |    4.909|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock VcTcXo_ik
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VcTcXo_ik      |   12.735|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock VmeSysClk_ik
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VmeSysClk_ik   |    2.126|         |         |         |
2062 2063 2064 2065 2066 2067 2068 2069
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

2070
Constraints cover 46733 paths, 0 nets, and 4348 connections
2071 2072

Design statistics:
2073
   Minimum period:  12.735ns{1}   (Maximum frequency:  78.524MHz)
2074 2075 2076 2077 2078


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

2079
Analysis completed Mon Dec 20 17:36:41 2010 
2080 2081 2082 2083 2084 2085
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

2086
Peak Memory Usage: 391 MB
2087 2088 2089