SFpga_map.map 18.3 KB
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Release 12.3 Map M.70d (nt64)
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Xilinx Map Application Log File for Design 'SFpga'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr
off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf 
Target Device  : xc6slx150t
Target Package : fgg676
Target Speed   : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
13
Mapped Date    : Mon Dec 20 08:25:44 2010
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
   PllFmc12SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllFmc12SFpga_ikn connected to top level port
   PllFmc12SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllFmc22SFpga_ik connected to top level port
   PllFmc22SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllFmc22SFpga_ikn connected to top level port
   PllFmc22SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllSys2SFpga_ik connected to top level port
   PllSys2SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllSys2SFpga_ikn connected to top level port
   PllSys2SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllDds2SFpga_ik connected to top level port
   PllDds2SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllDds2SFpga_ikn connected to top level port
   PllDds2SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal DdsSyncOut_ik connected to top level port
   DdsSyncOut_ik has been removed.
WARNING:MapLib:701 - Signal DdsSyncOut_ikn connected to top level port
   DdsSyncOut_ikn has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<15> connected to top level port
   DdrDQ_iob16<15> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<14> connected to top level port
   DdrDQ_iob16<14> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<13> connected to top level port
   DdrDQ_iob16<13> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<12> connected to top level port
   DdrDQ_iob16<12> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<11> connected to top level port
   DdrDQ_iob16<11> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<10> connected to top level port
   DdrDQ_iob16<10> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<9> connected to top level port
   DdrDQ_iob16<9> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<8> connected to top level port
   DdrDQ_iob16<8> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<7> connected to top level port
   DdrDQ_iob16<7> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<6> connected to top level port
   DdrDQ_iob16<6> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<5> connected to top level port
   DdrDQ_iob16<5> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<4> connected to top level port
   DdrDQ_iob16<4> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<3> connected to top level port
   DdrDQ_iob16<3> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<2> connected to top level port
   DdrDQ_iob16<2> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<1> connected to top level port
   DdrDQ_iob16<1> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<0> connected to top level port
   DdrDQ_iob16<0> has been removed.
WARNING:MapLib:701 - Signal Si57xSDa_io connected to top level port Si57xSDa_io
   has been removed.
WARNING:MapLib:701 - Signal AFpgaProgDone_io connected to top level port
   AFpgaProgDone_io has been removed.
WARNING:MapLib:701 - Signal DdsIOUpdate_io connected to top level port
   DdsIOUpdate_io has been removed.
WARNING:MapLib:701 - Signal WRModeDef2_io connected to top level port
   WRModeDef2_io has been removed.
WARNING:MapLib:701 - Signal Sfp2ModeDef2_io connected to top level port
   Sfp2ModeDef2_io has been removed.
WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
   has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
   has been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
   AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
   VAdjInhibit_ozn has been removed.
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
92 93
Total REAL time at the beginning of Placer: 30 secs 
Total CPU  time at the beginning of Placer: 13 secs 
94 95

Phase 1.1  Initial Placement Analysis
96
Phase 1.1  Initial Placement Analysis (Checksum:ee27935a) REAL time: 36 secs 
97 98

Phase 2.7  Design Feasibility Check
99
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
100 101
   and 2 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
102
Phase 2.7  Design Feasibility Check (Checksum:ee27935a) REAL time: 36 secs 
103 104

Phase 3.31  Local Placement Optimization
105
Phase 3.31  Local Placement Optimization (Checksum:ee27935a) REAL time: 36 secs 
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122

Phase 4.2  Initial Placement for Architecture Specific Features
...
.......
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <VmeSysClk_ik> is placed at site <PAD550>. The corresponding
   BUFG component <VmeSysClk_ik_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y9>.
   There is only a select set of IOBs that can use the fast path to the Clocker
   buffer, and they are not being used. You may want to analyze why this problem
   exists and correct it. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <VmeSysClk_ik.PAD>
   allowing your design to continue. This constraint disables all clock placer
   rules related to the specified COMP.PIN. The use of this override is highly
   discouraged as it may lead to very poor timing results. It is recommended
   that this error condition be corrected in the design.
Phase 4.2  Initial Placement for Architecture Specific Features
123
(Checksum:d3736e22) REAL time: 44 secs 
124 125

Phase 5.36  Local Placement Optimization
126
Phase 5.36  Local Placement Optimization (Checksum:d3736e22) REAL time: 44 secs 
127 128

Phase 6.30  Global Clock Region Assignment
129
Phase 6.30  Global Clock Region Assignment (Checksum:d3736e22) REAL time: 44 secs 
130 131 132

Phase 7.3  Local Placement Optimization
...
133
Phase 7.3  Local Placement Optimization (Checksum:d47075b5) REAL time: 45 secs 
134 135

Phase 8.5  Local Placement Optimization
136
Phase 8.5  Local Placement Optimization (Checksum:d384eabe) REAL time: 45 secs 
137 138

Phase 9.8  Global Placement
139
........
140
.......................
141 142 143
.....................................
....
Phase 9.8  Global Placement (Checksum:7253f7a8) REAL time: 52 secs 
144 145

Phase 10.5  Local Placement Optimization
146
Phase 10.5  Local Placement Optimization (Checksum:7253f7a8) REAL time: 52 secs 
147 148

Phase 11.18  Placement Optimization
149
Phase 11.18  Placement Optimization (Checksum:85580283) REAL time: 1 mins 2 secs 
150 151

Phase 12.5  Local Placement Optimization
152
Phase 12.5  Local Placement Optimization (Checksum:85580283) REAL time: 1 mins 2 secs 
153 154

Phase 13.34  Placement Validation
155
Phase 13.34  Placement Validation (Checksum:8244a4e2) REAL time: 1 mins 3 secs 
156

157 158
Total REAL time to Placer completion: 1 mins 7 secs 
Total CPU  time to Placer completion: 48 secs 
159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<4>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<5>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<6>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<7>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncClk_ik_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRModeDef0_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTrst_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSDo_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PllDacDout_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsTClkIn_i_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPllLock_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2ModeDef0_i_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2LoS_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRTxFault_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsBunchClkIn_i_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TempIdDQ_io_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsDrOver_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTdi_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTck_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc1PrsntM2C_in_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTms_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc2PrsntM2C_in_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O> is incomplete. The
   signal does not drive any load pins in the design.

Design Summary
--------------

Design Summary:
Number of errors:      0
262
Number of warnings:   83
263
Slice Logic Utilization:
264 265
  Number of Slice Registers:                   812 out of 184,304    1%
    Number used as Flip Flops:                 812
266 267 268
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
269 270 271 272
  Number of Slice LUTs:                        954 out of  92,152    1%
    Number used as logic:                      911 out of  92,152    1%
      Number using O6 output only:             573
      Number using O5 output only:             172
273
      Number using O5 and O6:                  166
274
      Number used as ROM:                        0
275
    Number used as Memory:                      13 out of  21,680    1%
276 277 278 279 280
      Number used as Dual Port RAM:              8
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                  4
      Number used as Single Port RAM:            0
281 282
      Number used as Shift Register:             5
        Number using O6 output only:             5
283 284
        Number using O5 output only:             0
        Number using O5 and O6:                  0
285 286
    Number used exclusively as route-thrus:     30
      Number with same-slice register load:     21
287 288 289 290
      Number with same-slice carry load:         9
      Number with other load:                    0

Slice Logic Distribution:
291 292 293 294 295
  Number of occupied Slices:                   365 out of  23,038    1%
  Number of LUT Flip Flop pairs used:        1,098
    Number with an unused Flip Flop:           364 out of   1,098   33%
    Number with an unused LUT:                 144 out of   1,098   13%
    Number of fully used LUT-FF pairs:         590 out of   1,098   53%
296 297
    Number of unique control sets:              32
    Number of slice register sites lost
298
      to control set restrictions:              83 out of 184,304    1%
299 300 301 302 303 304 305 306

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
307 308
  Number of bonded IOBs:                       330 out of     396   83%
    Number of LOCed IOBs:                      328 out of     330   99%
309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338
    IOB Master Pads:                             2
    IOB Slave Pads:                              2

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     268    0%
  Number of RAMB8BWERs:                          0 out of     536    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       4 out of      16   25%
    Number used as BUFGs:                        4
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of      12    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     586    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     586    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     586    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     384    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of     180    0%
  Number of GTPA1_DUALs:                         0 out of       4    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       4    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       6    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

339
Average Fanout of Non-Clock Nets:                3.01
340

341 342 343
Peak Memory Usage:  630 MB
Total REAL time to MAP completion:  1 mins 10 secs 
Total CPU time to MAP completion:   50 secs 
344 345 346

Mapping completed.
See MAP report file "SFpga_map.mrp" for details.