SFpga_map.mrp 76.7 KB
Newer Older
1
Release 12.3 Map M.70d (nt64)
2 3 4 5 6 7 8 9 10 11 12
Xilinx Mapping Report File for Design 'SFpga'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr
off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf 
Target Device  : xc6slx150t
Target Package : fgg676
Target Speed   : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
13
Mapped Date    : Mon Dec 20 08:25:44 2010
14 15 16 17

Design Summary
--------------
Number of errors:      0
18
Number of warnings:   83
19
Slice Logic Utilization:
20 21
  Number of Slice Registers:                   812 out of 184,304    1%
    Number used as Flip Flops:                 812
22 23 24
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
25 26 27 28
  Number of Slice LUTs:                        954 out of  92,152    1%
    Number used as logic:                      911 out of  92,152    1%
      Number using O6 output only:             573
      Number using O5 output only:             172
29
      Number using O5 and O6:                  166
30
      Number used as ROM:                        0
31
    Number used as Memory:                      13 out of  21,680    1%
32 33 34 35 36
      Number used as Dual Port RAM:              8
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                  4
      Number used as Single Port RAM:            0
37 38
      Number used as Shift Register:             5
        Number using O6 output only:             5
39 40
        Number using O5 output only:             0
        Number using O5 and O6:                  0
41 42
    Number used exclusively as route-thrus:     30
      Number with same-slice register load:     21
43 44 45 46
      Number with same-slice carry load:         9
      Number with other load:                    0

Slice Logic Distribution:
47 48 49 50 51
  Number of occupied Slices:                   365 out of  23,038    1%
  Number of LUT Flip Flop pairs used:        1,098
    Number with an unused Flip Flop:           364 out of   1,098   33%
    Number with an unused LUT:                 144 out of   1,098   13%
    Number of fully used LUT-FF pairs:         590 out of   1,098   53%
52 53
    Number of unique control sets:              32
    Number of slice register sites lost
54
      to control set restrictions:              83 out of 184,304    1%
55 56 57 58 59 60 61 62

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
63 64
  Number of bonded IOBs:                       330 out of     396   83%
    Number of LOCed IOBs:                      328 out of     330   99%
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
    IOB Master Pads:                             2
    IOB Slave Pads:                              2

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     268    0%
  Number of RAMB8BWERs:                          0 out of     536    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       4 out of      16   25%
    Number used as BUFGs:                        4
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of      12    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     586    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     586    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     586    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     384    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of     180    0%
  Number of GTPA1_DUALs:                         0 out of       4    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       4    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       6    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

95
Average Fanout of Non-Clock Nets:                3.01
96

97 98 99
Peak Memory Usage:  630 MB
Total REAL time to MAP completion:  1 mins 10 secs 
Total CPU time to MAP completion:   50 secs 
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
   PllFmc12SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllFmc12SFpga_ikn connected to top level port
   PllFmc12SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllFmc22SFpga_ik connected to top level port
   PllFmc22SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllFmc22SFpga_ikn connected to top level port
   PllFmc22SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllSys2SFpga_ik connected to top level port
   PllSys2SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllSys2SFpga_ikn connected to top level port
   PllSys2SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllDds2SFpga_ik connected to top level port
   PllDds2SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllDds2SFpga_ikn connected to top level port
   PllDds2SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal DdsSyncOut_ik connected to top level port
   DdsSyncOut_ik has been removed.
WARNING:MapLib:701 - Signal DdsSyncOut_ikn connected to top level port
   DdsSyncOut_ikn has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<15> connected to top level port
   DdrDQ_iob16<15> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<14> connected to top level port
   DdrDQ_iob16<14> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<13> connected to top level port
   DdrDQ_iob16<13> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<12> connected to top level port
   DdrDQ_iob16<12> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<11> connected to top level port
   DdrDQ_iob16<11> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<10> connected to top level port
   DdrDQ_iob16<10> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<9> connected to top level port
   DdrDQ_iob16<9> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<8> connected to top level port
   DdrDQ_iob16<8> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<7> connected to top level port
   DdrDQ_iob16<7> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<6> connected to top level port
   DdrDQ_iob16<6> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<5> connected to top level port
   DdrDQ_iob16<5> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<4> connected to top level port
   DdrDQ_iob16<4> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<3> connected to top level port
   DdrDQ_iob16<3> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<2> connected to top level port
   DdrDQ_iob16<2> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<1> connected to top level port
   DdrDQ_iob16<1> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<0> connected to top level port
   DdrDQ_iob16<0> has been removed.
WARNING:MapLib:701 - Signal Si57xSDa_io connected to top level port Si57xSDa_io
   has been removed.
WARNING:MapLib:701 - Signal AFpgaProgDone_io connected to top level port
   AFpgaProgDone_io has been removed.
WARNING:MapLib:701 - Signal DdsIOUpdate_io connected to top level port
   DdsIOUpdate_io has been removed.
WARNING:MapLib:701 - Signal WRModeDef2_io connected to top level port
   WRModeDef2_io has been removed.
WARNING:MapLib:701 - Signal Sfp2ModeDef2_io connected to top level port
   Sfp2ModeDef2_io has been removed.
WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
   has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
   has been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
   AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
   VAdjInhibit_ozn has been removed.
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <VmeSysClk_ik> is placed at site <PAD550>. The corresponding
   BUFG component <VmeSysClk_ik_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y9>.
   There is only a select set of IOBs that can use the fast path to the Clocker
   buffer, and they are not being used. You may want to analyze why this problem
   exists and correct it. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <VmeSysClk_ik.PAD>
   allowing your design to continue. This constraint disables all clock placer
   rules related to the specified COMP.PIN. The use of this override is highly
   discouraged as it may lead to very poor timing results. It is recommended
   that this error condition be corrected in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<4>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<5>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<6>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<7>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncClk_ik_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRModeDef0_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTrst_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSDo_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PllDacDout_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsTClkIn_i_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPllLock_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2ModeDef0_i_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2LoS_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRTxFault_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsBunchClkIn_i_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TempIdDQ_io_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsDrOver_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTdi_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTck_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc1PrsntM2C_in_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTms_i_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc2PrsntM2C_in_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O> is incomplete. The
   signal does not drive any load pins in the design.

Section 3 - Informational
-------------------------
302
INFO:LIT:243 - Logical network N456 has no load.
303 304
INFO:LIT:395 - The above info message is repeated 51 more times for the
   following (max. 5 shown):
305
   N458,
306 307 308 309 310 311 312 313 314 315 316 317 318 319 320
   VmeAm_ib6<2>_IBUF,
   VmeAm_ib6<1>_IBUF,
   VmeDs_inb2<2>_IBUF,
   VmeDs_inb2<1>_IBUF
   To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
321
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
322 323 324 325 326 327
   and 2 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
INFO:Pack:1650 - Map created a placed design.

Section 4 - Removed Logic Summary
---------------------------------
328
  67 block(s) removed
329
   2 block(s) optimized away
330
  37 signal(s) removed
331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

Loadless block "i_DdsSyncOut_ik" (IBUFGDS) removed.
 The signal "DdsSyncOut_ik" is loadless and has been removed.
  Loadless block "DdsSyncOut_ik" (PAD) removed.
 The signal "DdsSyncOut_ikn" is loadless and has been removed.
  Loadless block "DdsSyncOut_ikn" (PAD) removed.
Loadless block "i_PllDds2SFpga_ik" (IBUFGDS) removed.
 The signal "PllDds2SFpga_ik" is loadless and has been removed.
  Loadless block "PllDds2SFpga_ik" (PAD) removed.
 The signal "PllDds2SFpga_ikn" is loadless and has been removed.
  Loadless block "PllDds2SFpga_ikn" (PAD) removed.
Loadless block "i_PllFmc12SFpga_ik" (IBUFGDS) removed.
 The signal "PllFmc12SFpga_ik" is loadless and has been removed.
  Loadless block "PllFmc12SFpga_ik" (PAD) removed.
 The signal "PllFmc12SFpga_ikn" is loadless and has been removed.
  Loadless block "PllFmc12SFpga_ikn" (PAD) removed.
Loadless block "i_PllFmc22SFpga_ik" (IBUFGDS) removed.
 The signal "PllFmc22SFpga_ik" is loadless and has been removed.
  Loadless block "PllFmc22SFpga_ik" (PAD) removed.
 The signal "PllFmc22SFpga_ikn" is loadless and has been removed.
  Loadless block "PllFmc22SFpga_ikn" (PAD) removed.
Loadless block "i_PllSys2SFpga_ik" (IBUFGDS) removed.
 The signal "PllSys2SFpga_ik" is loadless and has been removed.
  Loadless block "PllSys2SFpga_ik" (PAD) removed.
 The signal "PllSys2SFpga_ikn" is loadless and has been removed.
  Loadless block "PllSys2SFpga_ikn" (PAD) removed.
The signal "i_DdrLDQS_io/O" is sourceless and has been removed.
The signal "i_DdrUDQS_io/O" is sourceless and has been removed.

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "DdrDQ_iob16<15>" is unused and has been removed.
 Unused block "DdrDQ_iob16_15_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<14>" is unused and has been removed.
 Unused block "DdrDQ_iob16_14_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<13>" is unused and has been removed.
 Unused block "DdrDQ_iob16_13_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<12>" is unused and has been removed.
 Unused block "DdrDQ_iob16_12_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<11>" is unused and has been removed.
 Unused block "DdrDQ_iob16_11_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<10>" is unused and has been removed.
 Unused block "DdrDQ_iob16_10_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<9>" is unused and has been removed.
 Unused block "DdrDQ_iob16_9_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<8>" is unused and has been removed.
 Unused block "DdrDQ_iob16_8_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<7>" is unused and has been removed.
 Unused block "DdrDQ_iob16_7_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<6>" is unused and has been removed.
 Unused block "DdrDQ_iob16_6_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<5>" is unused and has been removed.
 Unused block "DdrDQ_iob16_5_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<4>" is unused and has been removed.
 Unused block "DdrDQ_iob16_4_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<3>" is unused and has been removed.
 Unused block "DdrDQ_iob16_3_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<2>" is unused and has been removed.
 Unused block "DdrDQ_iob16_2_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<1>" is unused and has been removed.
 Unused block "DdrDQ_iob16_1_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<0>" is unused and has been removed.
 Unused block "DdrDQ_iob16_0_OBUFT" (TRI) removed.
The signal "Si57xSDa_io" is unused and has been removed.
 Unused block "Si57xSDa_io_OBUFT" (TRI) removed.
The signal "AFpgaProgDone_io" is unused and has been removed.
 Unused block "AFpgaProgDone_io_OBUFT" (TRI) removed.
The signal "AFpgaProgProgram_o" is unused and has been removed.
 Unused block "AFpgaProgProgram_o_OBUFT" (TRI) removed.
The signal "VAdjInhibit_ozn" is unused and has been removed.
 Unused block "VAdjInhibit_ozn_OBUFT" (TRI) removed.
The signal "DdsIOUpdate_io" is unused and has been removed.
 Unused block "DdsIOUpdate_io_OBUFT" (TRI) removed.
The signal "WRModeDef2_io" is unused and has been removed.
 Unused block "WRModeDef2_io_OBUFT" (TRI) removed.
The signal "Sfp2ModeDef2_io" is unused and has been removed.
 Unused block "Sfp2ModeDef2_io_OBUFT" (TRI) removed.
The signal "Fmc1SDa_io" is unused and has been removed.
 Unused block "Fmc1SDa_io_OBUFT" (TRI) removed.
The signal "Fmc2SDa_io" is unused and has been removed.
 Unused block "Fmc2SDa_io_OBUFT" (TRI) removed.
Unused block "AFpgaProgDone_io" (PAD) removed.
Unused block "AFpgaProgProgram_o" (PAD) removed.
Unused block "DdrDQ_iob16<0>" (PAD) removed.
Unused block "DdrDQ_iob16<10>" (PAD) removed.
Unused block "DdrDQ_iob16<11>" (PAD) removed.
Unused block "DdrDQ_iob16<12>" (PAD) removed.
Unused block "DdrDQ_iob16<13>" (PAD) removed.
Unused block "DdrDQ_iob16<14>" (PAD) removed.
Unused block "DdrDQ_iob16<15>" (PAD) removed.
Unused block "DdrDQ_iob16<1>" (PAD) removed.
Unused block "DdrDQ_iob16<2>" (PAD) removed.
Unused block "DdrDQ_iob16<3>" (PAD) removed.
Unused block "DdrDQ_iob16<4>" (PAD) removed.
Unused block "DdrDQ_iob16<5>" (PAD) removed.
Unused block "DdrDQ_iob16<6>" (PAD) removed.
Unused block "DdrDQ_iob16<7>" (PAD) removed.
Unused block "DdrDQ_iob16<8>" (PAD) removed.
Unused block "DdrDQ_iob16<9>" (PAD) removed.
Unused block "DdsIOUpdate_io" (PAD) removed.
Unused block "Fmc1SDa_io" (PAD) removed.
Unused block "Fmc2SDa_io" (PAD) removed.
Unused block "Sfp2ModeDef2_io" (PAD) removed.
Unused block "Si57xSDa_io" (PAD) removed.
Unused block "VAdjInhibit_ozn" (PAD) removed.
Unused block "WRModeDef2_io" (PAD) removed.
Unused block "i_DdrLDQS_io/IBUFDS" (IBUFDS) removed.
Unused block "i_DdrUDQS_io/IBUFDS" (IBUFDS) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| AFpgaProgClk_io                    | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgCsi_io                    | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgD_iob8<0>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgD_iob8<1>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgD_iob8<2>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgD_iob8<3>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgD_iob8<4>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgD_iob8<5>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgD_iob8<6>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgD_iob8<7>                 | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| AFpgaProgInit_io                   | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgM_iob2<0>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgM_iob2<1>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| AFpgaProgRdWr_io                   | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| DdrA_ob14<0>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<1>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<2>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<3>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<4>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<5>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<6>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<7>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<8>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<9>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<10>                      | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<11>                      | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<12>                      | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrA_ob14<13>                      | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrBA_ob3<0>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrBA_ob3<1>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrBA_ob3<2>                       | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrCAS_o                           | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrCkE_o                           | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrCk_ok                           | IOB              | OUTPUT    | DIFF_SSTL15_II       |       |          |      |              |          |          |
| DdrCk_okn                          | IOB              | OUTPUT    | DIFF_SSTL15_II       |       |          |      |              |          |          |
| DdrLDM_o                           | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrLDQS_io                         | IOB              | OUTPUT    | DIFF_SSTL15_II       |       |          |      |              |          |          |
| DdrLDQS_ion                        | IOB              | OUTPUT    | DIFF_SSTL15_II       |       |          |      |              |          |          |
| DdrODT_o                           | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrRAS_o                           | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrReset_or                        | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrUDM_o                           | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdrUDQS_io                         | IOB              | OUTPUT    | DIFF_SSTL15_II       |       |          |      |              |          |          |
| DdrUDQS_ion                        | IOB              | OUTPUT    | DIFF_SSTL15_II       |       |          |      |              |          |          |
| DdrWe_o                            | IOB              | OUTPUT    | SSTL15_II            |       |          |      |              |          |          |
| DdsD_ob16<0>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<1>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<2>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<3>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<4>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<5>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<6>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<7>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<8>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<9>                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<10>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<11>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<12>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<13>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<14>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsD_ob16<15>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsDrCtl_o                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsDrHold_o                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsDrOver_i                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DdsF_ob2<0>                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsF_ob2<1>                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsIoReset_or                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsMasterRst_or                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsOsk_o                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsPdClk_ik                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DdsPllLock_i                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DdsPowerDown_o                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsProfile_ob3<0>                  | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsProfile_ob3<1>                  | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsProfile_ob3<2>                  | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsRamSwpOvr_i                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DdsSClk_o                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsSDio_io                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DdsSDo_i                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DdsSyncClk_ik                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DdsSyncIn_ok                       | IOBM             | OUTPUT    | LVDS_33              |       |          |      |              |          |          |
| DdsSyncIn_okn                      | IOBS             | OUTPUT    | LVDS_33              |       |          |      |              |          |          |
| DdsSyncSmpErr_i                    | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DdsTxEnable_o                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FlashAFpgaClk_ok                   | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FlashAFpgaCs_on                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FlashAFpgaD_o                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FlashAFpgaQ_i                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| FlashSFpgaClk_ok                   | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FlashSFpgaCs_on                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FlashSFpgaD_o                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FlashSFpgaQ_i                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| Fmc1PGC2M_in                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| Fmc1PrsntM2C_in                    | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| Fmc1SCl_ok                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| Fmc2PGC2M_in                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| Fmc2PrsntM2C_in                    | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| Fmc2SCl_ok                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FpGpIo1OutputMode_o                | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FpGpIo2OutputMode_o                | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FpGpIo34OutputMode_o               | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| FpLed_onb8<0>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| FpLed_onb8<1>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| FpLed_onb8<2>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| FpLed_onb8<3>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| FpLed_onb8<4>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| FpLed_onb8<5>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| FpLed_onb8<6>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| FpLed_onb8<7>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| ManualAddress_ib5<0>               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| ManualAddress_ib5<1>               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| ManualAddress_ib5<2>               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| ManualAddress_ib5<3>               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| ManualAddress_ib5<4>               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PcbRev_ib8<0>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PcbRev_ib8<1>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PcbRev_ib8<2>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PcbRev_ib8<3>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PcbRev_ib8<4>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PcbRev_ib8<5>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PcbRev_ib8<6>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PcbRev_ib8<7>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| PllDacClrn_orn                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDacDin_o                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDacDout_i                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllDacLDac_on                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDacSClk_ok                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDacSynch_on                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDdsClk_ok                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| PllDdsCs_on                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDdsLd_i                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllDdsPd_on                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDdsRefMon_i                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllDdsRefSel_o                     | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| PllDdsReset_orn                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDdsSClk_ok                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDdsSDio_io                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllDdsSdo_i                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllDdsStatus_i                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllDdsSynch_on                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc1Cs_on                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc1Ld_i                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllFmc1Pd_on                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc1Ref1_ok                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc1RefMon_i                    | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllFmc1RefSel_o                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc1Reset_orn                   | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc1SClk_ok                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc1SDio_io                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc1Sdo_i                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllFmc1Status_i                    | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllFmc1Synch_on                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc2Cs_on                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc2Ld_i                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllFmc2Pd_on                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc2Ref1_ok                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc2RefMon_i                    | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllFmc2RefSel_o                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc2Reset_orn                   | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc2SClk_ok                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc2SDio_io                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllFmc2Sdo_i                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllFmc2Status_i                    | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllFmc2Synch_on                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllSysCs_on                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllSysLd_i                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllSysPd_on                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllSysRef12_ok                     | IOBM             | OUTPUT    | LVDS_33              |       |          |      |              |          |          |
| PllSysRef12_okn                    | IOBS             | OUTPUT    | LVDS_33              |       |          |      |              |          |          |
| PllSysRefMon_i                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllSysRefSel_o                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllSysReset_orn                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllSysSClk_ok                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllSysSDio_io                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PllSysSdo_i                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllSysStatus_i                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| PllSysSynch_on                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| PushButton_ion                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| Sfp2LoS_i                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| Sfp2ModeDef0_i                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| Sfp2ModeDef1_i                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| Sfp2RateSelect                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| Sfp2TxDisable_o                    | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| Sfp2TxFault_i                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
655
| Si57xOe_o                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849
| Si57xSCl_ok                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| Si57x_ik                           | IOB              | INPUT     | LVDS_33              | TRUE  |          |      |              |          |          |
| Si57x_ikn                          | IOB              | INPUT     | LVDS_33              | TRUE  |          |      |              |          |          |
| Switch_ib2<0>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| Switch_ib2<1>                      | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SysAppClk_ik                       | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SysAppClk_ok                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| SysAppSlow_iob2<1>                 | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| SysAppSlow_iob2<2>                 | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| TempIdDQ_io                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| UseGa_i                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| VAdcCs_on                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VAdcDin_o                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VAdcDout_i                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VAdcSClk_ok                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VAdjCs_on                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VAdjDin_o                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VAdjSClk_ok                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VAdjSpi_o                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VcTcXo_ik                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeADirVfcToVme_o                  | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeAOeN_oen                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeA_iob31<1>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<2>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<3>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<4>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<5>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<6>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<7>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<8>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<9>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<10>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<11>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<12>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<13>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<14>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<15>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<16>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<17>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<18>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<19>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<20>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<21>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<22>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<23>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<24>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<25>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<26>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<27>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<28>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<29>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<30>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeA_iob31<31>                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeAm_ib6<0>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeAm_ib6<1>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeAm_ib6<2>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeAm_ib6<3>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeAm_ib6<4>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeAm_ib6<5>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeAs_in                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeBerr_o                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeDDirVfcToVme_o                  | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeDOeN_oen                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<0>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<1>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<2>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<3>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<4>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<5>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<6>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<7>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<8>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<9>                      | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<10>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<11>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<12>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<13>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<14>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<15>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<16>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<17>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<18>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<19>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<20>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<21>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<22>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<23>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<24>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<25>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<26>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<27>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<28>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<29>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<30>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeD_iob32<31>                     | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeDs_inb2<1>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeDs_inb2<2>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeDtAckOe_oe                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeDtAck_on                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeGaP_in                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeGa_ib5n<0>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeGa_ib5n<1>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeGa_ib5n<2>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeGa_ib5n<3>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeGa_ib5n<4>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeIackIn_in                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeIackOut_on                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeIack_in                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeIrq_ob7<1>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeIrq_ob7<2>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeIrq_ob7<3>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeIrq_ob7<4>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeIrq_ob7<5>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeIrq_ob7<6>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeIrq_ob7<7>                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeLword_io                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeP0BunchSelectDir_o              | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0BunchSelectOe_o               | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0BuslineDir_o                  | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0BuslineOe_o                   | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0HwHighByteDir_o               | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0HwHighByteOe_o                | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0HwLowByteDir_o                | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0HwLowByteOe_o                 | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0LvdsBunchClkIn_i              | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeP0LvdsBunchClkOut_o             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeP0LvdsTClkIn_i                  | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeP0LvdsTClkOut_o                 | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeRetryOe_oe                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeRetry_on                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeSysClk_ik                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeSysReset_in                     | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeTck_i                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeTdi_i                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeTdoOe_oe                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeTdo_o                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| VmeTms_i                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeTrst_i                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| VmeWrite_in                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| WRLoS_i                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| WRModeDef0_i                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| WRModeDef1_i                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| WRRateSelect_o                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| WRTxDisable_o                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| WRTxFault_i                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.

For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.

Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.