Commit 0895a9f9 authored by Andrea Boccardi's avatar Andrea Boccardi

rerun of ISE with added timing constraints

parent 36769977
......@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary:
Total memory usage is 88036 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 6 sec
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 5 sec
Writing NGDBUILD log file "SFpga.bld"...
......@@ -58,3 +58,14 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:09 2010
Fri Dec 17 10:02:33 2010
# NOTE: This file is designed to be imported into a spreadsheet program
......@@ -296,7 +296,7 @@ E14||IOBS|IO_L40N_0|UNUSED||0|||||||||
E15|||GND||||||||||||
E16|VmeP0HwLowByteOe_o|IOB|IO_L49N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E17|||VCCAUX||||||||2.5||||
E18|Si57xOe_o|IOB|IO_L51N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E18||IOBS|IO_L51N_0|UNUSED||0|||||||||
E19|||GND||||||||||||
E20|VmeWrite_in|IOB|IO_L57N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
E21|||VCCO_0|||0|||||3.30||||
......
Release 12.3 par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Thu Dec 16 18:43:02 2010
BQPLV2:: Fri Dec 17 10:01:26 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -26,11 +26,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 587
Number using O5 output only: 154
Number using O5 and O6: 166
Number using O5 and O6: 158
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 15
Number with same-slice register load: 6
Number used exclusively as route-thrus: 31
Number with same-slice register load: 22
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113
Number with an unused Flip Flop: 382 out of 1,113 34%
Number with an unused LUT: 196 out of 1,113 17%
Number of fully used LUT-FF pairs: 535 out of 1,113 48%
Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -63,8 +63,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99%
IOB Master Pads: 2
IOB Slave Pads: 2
......@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 24 secs
Finished initial Timing Analysis. REAL time: 24 secs
Starting initial Timing Analysis. REAL time: 22 secs
Finished initial Timing Analysis. REAL time: 22 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -152,27 +152,27 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 5215 unrouted; REAL time: 27 secs
Phase 1 : 5204 unrouted; REAL time: 25 secs
Phase 2 : 4592 unrouted; REAL time: 34 secs
Phase 2 : 4597 unrouted; REAL time: 31 secs
Phase 3 : 1753 unrouted; REAL time: 46 secs
Phase 3 : 1889 unrouted; REAL time: 44 secs
Phase 4 : 1753 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 57 secs
Phase 4 : 1889 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 56 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 4 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Total REAL time to Router completion: 1 mins 4 secs
Total CPU time to Router completion: 1 mins 2 secs
......@@ -192,18 +192,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 221 | 0.247 | 1.696 |
| Si57x_BUFG | BUFGMUX_X2Y4| No | 217 | 0.248 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 18 | 0.186 | 1.688 |
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 15 | 0.009 | 1.515 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 217 | 0.000 | 4.055 |
| i_Core/Rst_rq | Local| | 213 | 0.000 | 6.628 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.159 |
| e/stb_o | Local| | 19 | 0.000 | 4.448 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -220,8 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.189ns| 8.144ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.321ns| | 0| 0
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.399ns| 7.934ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.347ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 5.459ns| 2.874ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.459ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -235,9 +238,9 @@ All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 8 secs
Total CPU time to PAR completion: 1 mins 6 secs
Total CPU time to PAR completion: 1 mins 7 secs
Peak Memory Usage: 371 MB
Peak Memory Usage: 369 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
//! **************************************************************************
// Written by: Map M.70d on Thu Dec 16 18:42:57 2010
// Written by: Map M.70d on Fri Dec 17 10:01:22 2010
//! **************************************************************************
SCHEMATIC START;
......@@ -255,7 +255,6 @@ COMP "DdsF_ob2<1>" LOCATE = SITE "A2" LEVEL 1;
COMP "DdsDrOver_i" LOCATE = SITE "G13" LEVEL 1;
COMP "PllFmc2Synch_on" LOCATE = SITE "V12" LEVEL 1;
COMP "DdsTxEnable_o" LOCATE = SITE "G8" LEVEL 1;
COMP "Si57xOe_o" LOCATE = SITE "E18" LEVEL 1;
COMP "VmeP0BunchSelectDir_o" LOCATE = SITE "G15" LEVEL 1;
COMP "VAdjSClk_ok" LOCATE = SITE "J2" LEVEL 1;
COMP "PllDacClrn_orn" LOCATE = SITE "Y21" LEVEL 1;
......@@ -978,6 +977,63 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_30" BEL "i_Core/i_Slv2SerWB/Dat_xb32_29"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_28" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_27" BEL "i_Core/i_Slv2SerWB/Dat_xb32_26"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_25" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_24" BEL "i_Core/i_Slv2SerWB/Dat_xb32_23"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_22" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_21" BEL "i_Core/i_Slv2SerWB/Dat_xb32_20"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_19" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_18" BEL "i_Core/i_Slv2SerWB/Dat_xb32_17"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_16" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_15" BEL "i_Core/i_Slv2SerWB/Dat_xb32_14"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_13" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_12" BEL "i_Core/i_Slv2SerWB/Dat_xb32_11"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_10" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_9" BEL "i_Core/i_Slv2SerWB/Dat_xb32_8"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_7" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_6" BEL "i_Core/i_Slv2SerWB/Dat_xb32_5"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_4" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_3" BEL "i_Core/i_Slv2SerWB/Dat_xb32_2"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_1" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_0" BEL "i_Core/i_Slv2SerWB/AckI_xb3_2"
BEL "i_Core/i_Slv2SerWB/DatInShReg_b32_31" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/AckI_d3_2" BEL "i_Core/i_Slv2SerWB/AckI_d3_1" BEL
"i_Core/i_Slv2SerWB/AckI_d3_0" BEL "SysAppClk_ik_BUFGP/BUFG";
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
SCHEMATIC END;
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.189" best="8.144" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.321" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.399" best="7.934" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.347" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.459" best="2.874" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.459" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
......@@ -10,7 +10,7 @@ Total CPU time to Xst completion: 0.16 secs
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs
Total CPU time to Xst completion: 0.16 secs
--> Reading design: SFpga.prj
......@@ -303,6 +303,7 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 1-bit tristate buffer for signal <DdrDQ_iob16<1>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315
Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338
Found 1-bit tristate buffer for signal <Si57xOe_o> created at line 339
Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 374
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 375
......@@ -319,7 +320,7 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
inferred 3 Adder/Subtractor(s).
inferred 69 D-type flip-flop(s).
inferred 1 Multiplexer(s).
inferred 33 Tristate(s).
inferred 34 Tristate(s).
Unit <SystemFpga> synthesized.
Synthesizing Unit <Monostable>.
......@@ -329,7 +330,7 @@ Synthesizing Unit <Monostable>.
Found 20-bit register for signal <Counter_c>.
Found 1-bit register for signal <SynchOutput_oq>.
Found 1-bit register for signal <AsynchIn_ax>.
Found 20-bit adder for signal <Counter_c[19]_GND_25_o_add_6_OUT> created at line 20.
Found 20-bit adder for signal <Counter_c[19]_GND_26_o_add_6_OUT> created at line 20.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 25 D-type flip-flop(s).
......@@ -343,7 +344,7 @@ Synthesizing Unit <Debouncer>.
Found 16-bit register for signal <Counter_c>.
Found 1-bit register for signal <DebouncedSignal_oq>.
Found 3-bit register for signal <BouncingSignal_x>.
Found 16-bit adder for signal <Counter_c[15]_GND_34_o_add_7_OUT> created at line 38.
Found 16-bit adder for signal <Counter_c[15]_GND_35_o_add_7_OUT> created at line 38.
Found 1-bit comparator equal for signal <n0003> created at line 31
Summary:
inferred 1 Adder/Subtractor(s).
......@@ -393,9 +394,9 @@ Synthesizing Unit <VmeInterfaceWB>.
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 9-bit adder for signal <AckTimeout_c[8]_GND_35_o_add_16_OUT> created at line 100.
Found 22-bit adder for signal <adr_o[21]_GND_35_o_add_48_OUT> created at line 200.
Found 1-bit 4-to-1 multiplexer for signal <_n0284> created at line 148.
Found 9-bit adder for signal <AckTimeout_c[8]_GND_36_o_add_16_OUT> created at line 100.
Found 22-bit adder for signal <adr_o[21]_GND_36_o_add_48_OUT> created at line 200.
Found 1-bit 4-to-1 multiplexer for signal <_n0291> created at line 148.
Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148.
Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110
......@@ -429,7 +430,7 @@ Synthesizing Unit <VmeInterfaceWB>.
Found 1-bit tristate buffer for signal <vme_data<2>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<1>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<0>> created at line 110
Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_35_o_equal_12_o> created at line 75
Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_36_o_equal_12_o> created at line 75
Found 3-bit comparator equal for signal <vme_addr[3]_intlev_reg[2]_equal_43_o> created at line 178
Summary:
inferred 2 Adder/Subtractor(s).
......@@ -461,10 +462,10 @@ WARNING:Xst:647 - Input <Dat_ib32<30:11>> is never used. This port will be prese
Found 1-bit register for signal <fifo_empty>.
Found 1-bit register for signal <Stb_d>.
Found 1-bit register for signal <osc_clk>.
Found 4-bit subtractor for signal <int_counter[3]_GND_68_o_sub_23_OUT> created at line 101.
Found 4-bit adder for signal <int_counter[3]_GND_68_o_add_20_OUT> created at line 99.
Found 3-bit adder for signal <int_pointer_w[2]_GND_68_o_add_29_OUT> created at line 115.
Found 3-bit adder for signal <int_pointer_r[2]_GND_68_o_add_31_OUT> created at line 118.
Found 4-bit subtractor for signal <int_counter[3]_GND_69_o_sub_23_OUT> created at line 101.
Found 4-bit adder for signal <int_counter[3]_GND_69_o_add_20_OUT> created at line 99.
Found 3-bit adder for signal <int_pointer_w[2]_GND_69_o_add_29_OUT> created at line 115.
Found 3-bit adder for signal <int_pointer_r[2]_GND_69_o_add_31_OUT> created at line 118.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 165.
Found 3-bit comparator equal for signal <int_pointer_w[2]_int_pointer_r[2]_equal_42_o> created at line 132
Found 3-bit comparator equal for signal <n0078> created at line 134
......@@ -587,8 +588,8 @@ Synthesizing Unit <SpiMasterWB>.
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 12-bit adder for signal <TxCounter_cb12[11]_GND_77_o_add_40_OUT> created at line 138.
Found 16-bit adder for signal <TimeCounter_cb16[15]_GND_77_o_add_67_OUT> created at line 163.
Found 12-bit adder for signal <TxCounter_cb12[11]_GND_78_o_add_40_OUT> created at line 138.
Found 16-bit adder for signal <TimeCounter_cb16[15]_GND_78_o_add_67_OUT> created at line 163.
Found 1-bit 32-to-1 multiplexer for signal <a_SpiChannel_b5[4]_MiSo_ib32[31]_Mux_56_o> created at line 150.
Found 32-bit 7-to-1 multiplexer for signal <Dat_oab32> created at line 185.
Found 16-bit comparator equal for signal <TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o> created at line 77
......@@ -649,8 +650,8 @@ Macro Statistics
5-bit 2-to-1 multiplexer : 1
7-bit 2-to-1 multiplexer : 1
9-bit 2-to-1 multiplexer : 1
# Tristates : 65
1-bit tristate buffer : 65
# Tristates : 66
1-bit tristate buffer : 66
# FSMs : 2
# Xors : 4
1-bit xor3 : 2
......@@ -901,9 +902,9 @@ Primitive and Black Box Usage:
# IBUFGDS : 6
# IOBUF : 32
# IOBUFDS : 2
# OBUF : 152
# OBUF : 151
# OBUFDS : 3
# OBUFT : 33
# OBUFT : 34
Device utilization summary:
---------------------------
......@@ -996,8 +997,8 @@ Delay: 8.328ns (Levels of Logic = 5)
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 2 0.525 1.047 i_Core/i_VmeInterface/adr_o_21_1 (i_Core/i_VmeInterface/adr_o_21_1)
LUT6:I1->O 4 0.254 0.912 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1)
LUT6:I1->O 4 0.254 0.912 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o12)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_4_o1)
LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster)
LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster)
LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o)
......@@ -1175,8 +1176,8 @@ Offset: 8.362ns (Levels of Logic = 6)
---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N5)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N259)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o311 (N5)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o87_SW0 (N259)
LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected)
LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv)
FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0
......@@ -1343,12 +1344,12 @@ i_Core/i_VmeInterface/stb_o| 2.049| | | |
=========================================================================
Total REAL time to Xst completion: 28.00 secs
Total CPU time to Xst completion: 28.30 secs
Total REAL time to Xst completion: 27.00 secs
Total CPU time to Xst completion: 26.61 secs
-->
Total memory usage is 154916 kilobytes
Total memory usage is 154724 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 126 ( 0 filtered)
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -696,3 +696,6 @@ NET "VmeSysClk_ik" CLOCK_DEDICATED_ROUTE = "FALSE";
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/16
NET "Si57x_ik" TNM_NET = "Si57x_ik";
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 120 MHz HIGH 50 %;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/17
NET "SysAppClk_ik" TNM_NET = SysAppClk_ik;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50%;
Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:10 2010
Fri Dec 17 10:02:34 2010
All signals are completely routed.
......
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Thu Dec 16 18:41:28 2010
Mapped Date : Fri Dec 17 09:59:57 2010
Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
......@@ -79,6 +79,8 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed.
WARNING:MapLib:701 - Signal Si57xOe_o connected to top level port Si57xOe_o has
been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
......@@ -89,20 +91,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 28 secs
Total REAL time at the beginning of Placer: 26 secs
Total CPU time at the beginning of Placer: 26 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:fbd9bf1c) REAL time: 36 secs
Phase 1.1 Initial Placement Analysis (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
INFO:Place:834 - Only a subset of IOs are locked. Out of 329 IOs, 327 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:fbd9bf1c) REAL time: 36 secs
Phase 2.7 Design Feasibility Check (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:fbd9bf1c) REAL time: 36 secs
Phase 3.31 Local Placement Optimization (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
......@@ -120,42 +122,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:b9a90c54) REAL time: 50 secs
(Checksum:2c046bcb) REAL time: 47 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:b9a90c54) REAL time: 50 secs
Phase 5.36 Local Placement Optimization (Checksum:2c046bcb) REAL time: 47 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:b9a90c54) REAL time: 50 secs
Phase 6.30 Global Clock Region Assignment (Checksum:2c046bcb) REAL time: 47 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:5a4374ed) REAL time: 52 secs
Phase 7.3 Local Placement Optimization (Checksum:e20e3683) REAL time: 48 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b9b9c566) REAL time: 52 secs
Phase 8.5 Local Placement Optimization (Checksum:2c14b62b) REAL time: 49 secs
Phase 9.8 Global Placement
...........
.............
................
..............................
.......................
.....
Phase 9.8 Global Placement (Checksum:1b243f66) REAL time: 1 mins 3 secs
Phase 9.8 Global Placement (Checksum:ae7774fb) REAL time: 1 mins
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:1b243f66) REAL time: 1 mins 3 secs
Phase 10.5 Local Placement Optimization (Checksum:ae7774fb) REAL time: 1 mins 1 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:3389a4d6) REAL time: 1 mins 18 secs
Phase 11.18 Placement Optimization (Checksum:fe895bce) REAL time: 1 mins 14 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:3389a4d6) REAL time: 1 mins 18 secs
Phase 12.5 Local Placement Optimization (Checksum:fe895bce) REAL time: 1 mins 14 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:bed3755b) REAL time: 1 mins 19 secs
Phase 13.34 Placement Validation (Checksum:b38174ec) REAL time: 1 mins 14 secs
Total REAL time to Placer completion: 1 mins 28 secs
Total CPU time to Placer completion: 1 mins 24 secs
Total REAL time to Placer completion: 1 mins 23 secs
Total CPU time to Placer completion: 1 mins 22 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
......@@ -259,18 +261,18 @@ Design Summary
Design Summary:
Number of errors: 0
Number of warnings: 83
Number of warnings: 84
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 587
Number using O5 output only: 154
Number using O5 and O6: 166
Number using O5 and O6: 158
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -282,17 +284,17 @@ Slice Logic Utilization:
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 15
Number with same-slice register load: 6
Number used exclusively as route-thrus: 31
Number with same-slice register load: 22
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113
Number with an unused Flip Flop: 382 out of 1,113 34%
Number with an unused LUT: 196 out of 1,113 17%
Number of fully used LUT-FF pairs: 535 out of 1,113 48%
Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of unique control sets: 32
Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1%
......@@ -304,8 +306,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99%
IOB Master Pads: 2
IOB Slave Pads: 2
......@@ -336,11 +338,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02
Average Fanout of Non-Clock Nets: 3.03
Peak Memory Usage: 406 MB
Total REAL time to MAP completion: 1 mins 31 secs
Total CPU time to MAP completion: 1 mins 28 secs
Total REAL time to MAP completion: 1 mins 26 secs
Total CPU time to MAP completion: 1 mins 25 secs
Mapping completed.
See MAP report file "SFpga_map.mrp" for details.
......@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Thu Dec 16 18:41:28 2010
Mapped Date : Fri Dec 17 09:59:57 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 83
Number of warnings: 84
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 587
Number using O5 output only: 154
Number using O5 and O6: 166
Number using O5 and O6: 158
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -38,17 +38,17 @@ Slice Logic Utilization:
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 15
Number with same-slice register load: 6
Number used exclusively as route-thrus: 31
Number with same-slice register load: 22
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113
Number with an unused Flip Flop: 382 out of 1,113 34%
Number with an unused LUT: 196 out of 1,113 17%
Number of fully used LUT-FF pairs: 535 out of 1,113 48%
Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of unique control sets: 32
Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1%
......@@ -60,8 +60,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99%
IOB Master Pads: 2
IOB Slave Pads: 2
......@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02
Average Fanout of Non-Clock Nets: 3.03
Peak Memory Usage: 406 MB
Total REAL time to MAP completion: 1 mins 31 secs
Total CPU time to MAP completion: 1 mins 28 secs
Total REAL time to MAP completion: 1 mins 26 secs
Total CPU time to MAP completion: 1 mins 25 secs
Table of Contents
-----------------
......@@ -185,6 +185,8 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed.
WARNING:MapLib:701 - Signal Si57xOe_o connected to top level port Si57xOe_o has
been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port