Commit 0f297cf7 authored by Andrea Boccardi's avatar Andrea Boccardi

Sram accesses forced to be at 100MHz

parent 6f2550fb
......@@ -18,7 +18,7 @@ module WbToCy7c1470 (
reg [3:0] ReadCycle_d;
reg [31:0] DatI_db32 [2:0];
reg [2:0] WriteCycle_d;
reg [3:0] WriteCycle_d;
wire ReadCycle_a = Cyc_i && Stb_i && ~We_i;
wire WriteCycle_a = Cyc_i && Stb_i && We_i;
......@@ -30,9 +30,9 @@ assign SramOe_on = ~ReadCycle_d[2];
always @(posedge Clk_ik) SramAddress_ob21 <= Adr_ib21;
always @(posedge Clk_ik) WriteCycle_d <= {WriteCycle_d[1:0], WriteCycle_a};
always @(posedge Clk_ik) WriteCycle_d <= {WriteCycle_d[2:0], WriteCycle_a};
assign SramWe_on = ~WriteCycle_d[0];
assign SramWe_on = ~(WriteCycle_d[1:0]==2'b01);
always @(posedge Clk_ik) begin
DatI_db32[2] <= DatI_db32[1];
......@@ -40,9 +40,9 @@ always @(posedge Clk_ik) begin
DatI_db32[0] <= Dat_ib32;
end
assign SramData_iob36 = WriteCycle_d[2] ? {4'h0, DatI_db32[2]} : 36'hz;
assign SramData_iob36 = (WriteCycle_d[3:2]==2'b01) ? {4'h0, DatI_db32[2]} : 36'hz;
always @(posedge Clk_ik) if (ReadCycle_d[2]) Dat_ob32 <= SramData_iob36;
always @(posedge Clk_ik) if (ReadCycle_d[3:2]==2'b01) Dat_ob32 <= SramData_iob36;
assign SramClk_ok = Clk_ik;
......
......@@ -14,6 +14,26 @@ WaitSimulation('1000')
VmeReset()
WaitSimulation('1000')
print "Setting the Application FPGA SRAM1(0), SRAM1(1), SRAM2(0), SRAM2(1) to 3 to: 0x1a, 0x1b, 0x2a, 0x2b"
MyBoard.ApplSram1.Write(0, 0x1a)
MyBoard.ApplSram1.Write(4, 0x1b)
MyBoard.ApplSram2.Write(0, 0x2a)
MyBoard.ApplSram2.Write(4, 0x2b)
print "Application FPGA SRAM1(0)is: ", hex(MyBoard.ApplSram1.Read(0))
print "Application FPGA SRAM1(1)is: ", hex(MyBoard.ApplSram1.Read(4))
print "Application FPGA SRAM2(0)is: ", hex(MyBoard.ApplSram2.Read(0))
print "Application FPGA SRAM2(1)is: ", hex(MyBoard.ApplSram2.Read(4))
WaitSimulation(10000)
StopSimulation()
exit()
#SIMULATIN FLOW
print "Release: ", hex(MyBoard.ReleaseID.Read())
......
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