Maintenance scheduled 24th July -- expect downtime along that day

Commit 12b83ada authored by Andrea Boccardi's avatar Andrea Boccardi

changed the clock source to the VCTCXO

parent bd941eab
......@@ -41,7 +41,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 14
Total memory usage is 154956 kilobytes
Total memory usage is 155532 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
......
......@@ -93,3 +93,20 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
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Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 13:48:21 2010
Mon Dec 20 17:36:28 2010
# NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Mon Dec 20 13:47:50 2010
PCBE13225:: Mon Dec 20 17:35:53 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -21,16 +21,16 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 843 out of 184,304 1%
Number used as Flip Flops: 843
Number of Slice Registers: 834 out of 184,304 1%
Number used as Flip Flops: 834
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 993 out of 92,152 1%
Number used as logic: 951 out of 92,152 1%
Number using O6 output only: 595
Number using O5 output only: 196
Number using O5 and O6: 160
Number of Slice LUTs: 965 out of 92,152 1%
Number used as logic: 934 out of 92,152 1%
Number using O6 output only: 579
Number using O5 output only: 187
Number using O5 and O6: 168
Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 6
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 28
Number with same-slice register load: 18
Number used exclusively as route-thrus: 17
Number with same-slice register load: 7
Number with same-slice carry load: 10
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 395 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,152
Number with an unused Flip Flop: 387 out of 1,152 33%
Number with an unused LUT: 159 out of 1,152 13%
Number of fully used LUT-FF pairs: 606 out of 1,152 52%
Number of occupied Slices: 383 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,137
Number with an unused Flip Flop: 369 out of 1,137 32%
Number with an unused LUT: 172 out of 1,137 15%
Number of fully used LUT-FF pairs: 596 out of 1,137 52%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -155,29 +155,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 5380 unrouted; REAL time: 11 secs
Phase 1 : 5283 unrouted; REAL time: 12 secs
Phase 2 : 4700 unrouted; REAL time: 15 secs
Phase 2 : 4622 unrouted; REAL time: 16 secs
Phase 3 : 1691 unrouted; REAL time: 20 secs
Phase 3 : 1786 unrouted; REAL time: 24 secs
Phase 4 : 1691 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Phase 4 : 1786 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Total REAL time to Router completion: 29 secs
Total CPU time to Router completion: 29 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Total REAL time to Router completion: 32 secs
Total CPU time to Router completion: 30 secs
Partition Implementation Status
-------------------------------
......@@ -195,20 +195,20 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 227 | 0.253 | 1.701 |
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 210 | 0.329 | 1.697 |
+---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y10| No | 6 | 0.084 | 1.643 |
| Si57x_BUFG | BUFGMUX_X2Y4| No | 6 | 0.008 | 1.686 |
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.084 | 1.642 |
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y10| No | 6 | 0.084 | 1.639 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 14 | 0.177 | 1.690 |
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.188 | 1.690 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 211 | 0.000 | 4.695 |
| i_Core/Rst_rq | Local| | 197 | 0.000 | 3.235 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/WriteCycle | Local| | 1 | 0.000 | 3.167 |
| i_Core/WriteCycle | Local| | 1 | 0.000 | 2.542 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 5.423 |
| e/stb_o | Local| | 19 | 0.000 | 4.912 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -218,6 +218,8 @@ the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
......@@ -225,11 +227,22 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.224ns| 8.109ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.342ns| | 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 5.091ns| 4.909ns| 0| 0
lk_ik" 100 MHz HIGH 50% | HOLD | 0.482ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 7.500ns| 2.500ns| 0| 0
00 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" | SETUP | 7.730ns| 2.270ns| 0| 0
100 MHz HIGH 50% | HOLD | 0.521ns| | 0| 0
| MINPERIOD | 7.500ns| 2.500ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysC | SETUP | 22.874ns| 2.126ns| 0| 0
lk_ik" 40 MHz HIGH 50% | HOLD | 0.521ns| | 0| 0
| MINPERIOD | 22.500ns| 2.500ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.902ns| 3.431ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.392ns| | 0| 0
TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" | SETUP | 27.265ns| 12.735ns| 0| 0
25 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -242,10 +255,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 50 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 31 secs
Total REAL time to PAR completion: 35 secs
Total CPU time to PAR completion: 33 secs
Peak Memory Usage: 549 MB
Peak Memory Usage: 572 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
//! **************************************************************************
// Written by: Map M.70d on Mon Dec 20 13:47:47 2010
// Written by: Map M.70d on Mon Dec 20 17:35:51 2010
//! **************************************************************************
SCHEMATIC START;
......@@ -334,19 +334,19 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "i_Core/Rst_rq" BEL
TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/VcTcXoDivider_c_22" BEL "i_Core/VcTcXoDivider_c_21" BEL
"i_Core/VcTcXoDivider_c_20" BEL "i_Core/VcTcXoDivider_c_19" BEL
"i_Core/VcTcXoDivider_c_18" BEL "i_Core/VcTcXoDivider_c_17" BEL
"i_Core/VcTcXoDivider_c_16" BEL "i_Core/VcTcXoDivider_c_15" BEL
"i_Core/VcTcXoDivider_c_14" BEL "i_Core/VcTcXoDivider_c_13" BEL
"i_Core/VcTcXoDivider_c_12" BEL "i_Core/VcTcXoDivider_c_11" BEL
"i_Core/VcTcXoDivider_c_10" BEL "i_Core/VcTcXoDivider_c_9" BEL
"i_Core/VcTcXoDivider_c_8" BEL "i_Core/VcTcXoDivider_c_7" BEL
"i_Core/VcTcXoDivider_c_6" BEL "i_Core/VcTcXoDivider_c_5" BEL
"i_Core/VcTcXoDivider_c_4" BEL "i_Core/VcTcXoDivider_c_3" BEL
"i_Core/VcTcXoDivider_c_2" BEL "i_Core/VcTcXoDivider_c_1" BEL
"i_Core/VcTcXoDivider_c_0" BEL "i_Core/Rst_rq" BEL
"i_Core/i_VmeInterface/state_FSM_FFd2" BEL
"i_Core/i_VmeInterface/stb_d" BEL "i_Core/i_VmeInterface/adr_o_21" BEL
"i_Core/i_VmeInterface/adr_o_20" BEL "i_Core/i_VmeInterface/adr_o_19"
......@@ -437,9 +437,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_24" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
......@@ -464,9 +461,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_ClearMonostable/Counter_c_25" BEL
"i_Core/i_ClearMonostable/Counter_c_24" BEL
"i_Core/i_ClearMonostable/Counter_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_22" BEL
"i_Core/i_ClearMonostable/Counter_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_20" BEL
......@@ -491,9 +485,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_25" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_24" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_23" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_22" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_21" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_20" BEL
......@@ -996,7 +987,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeInterface/AckTimeout_c_2" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "VcTcXo_ik_IBUF_BUFG" BEL
"i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
......@@ -1022,6 +1013,45 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP VmeSysClk_ik = BEL "i_Core/VmeSysClkDivider_c_23" BEL
"i_Core/VmeSysClkDivider_c_22" BEL "i_Core/VmeSysClkDivider_c_21" BEL
"i_Core/VmeSysClkDivider_c_20" BEL "i_Core/VmeSysClkDivider_c_19" BEL
"i_Core/VmeSysClkDivider_c_18" BEL "i_Core/VmeSysClkDivider_c_17" BEL
"i_Core/VmeSysClkDivider_c_16" BEL "i_Core/VmeSysClkDivider_c_15" BEL
"i_Core/VmeSysClkDivider_c_14" BEL "i_Core/VmeSysClkDivider_c_13" BEL
"i_Core/VmeSysClkDivider_c_12" BEL "i_Core/VmeSysClkDivider_c_11" BEL
"i_Core/VmeSysClkDivider_c_10" BEL "i_Core/VmeSysClkDivider_c_9" BEL
"i_Core/VmeSysClkDivider_c_8" BEL "i_Core/VmeSysClkDivider_c_7" BEL
"i_Core/VmeSysClkDivider_c_6" BEL "i_Core/VmeSysClkDivider_c_5" BEL
"i_Core/VmeSysClkDivider_c_4" BEL "i_Core/VmeSysClkDivider_c_3" BEL
"i_Core/VmeSysClkDivider_c_2" BEL "i_Core/VmeSysClkDivider_c_1" BEL
"i_Core/VmeSysClkDivider_c_0" BEL "VmeSysClk_ik_BUFGP/BUFG";
TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_30" BEL "i_Core/i_Slv2SerWB/Dat_xb32_29"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_28" BEL
......@@ -1078,7 +1108,10 @@ TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/AckI_d3_2" BEL "i_Core/i_Slv2SerWB/AckI_d3_1" BEL
"i_Core/i_Slv2SerWB/AckI_d3_0" BEL "SysAppClk_ik_BUFGP/BUFG";
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" 25 MHz HIGH 50%;
TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysClk_ik" 40 MHz HIGH 50%;
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 100 MHz HIGH 50%;
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 100 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 100 MHz HIGH 50%;
SCHEMATIC END;
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.224" best="8.109" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.342" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.902" best="3.431" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.392" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.091" best="4.909" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.482" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="7.730" best="2.270" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VmeSysClk_ik = PERIOD TIMEGRP &quot;VmeSysClk_ik&quot; 40 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="22.874" best="2.126" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="22.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VcTcXo_ik = PERIOD TIMEGRP &quot;VcTcXo_ik&quot; 25 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="27.265" best="12.735" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
......@@ -4,13 +4,13 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: SFpga.prj
......@@ -129,7 +129,7 @@ Parsing module <AddressDecoderWBSys>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v\" into library work
Parsing module <SystemFpga>.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro <dly> is redefined.
WARNING:HDLCompiler:224 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 588: Assignment to input AFpgaProgDone_io
WARNING:HDLCompiler:224 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to input AFpgaProgDone_io
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v\" into library work
Parsing module <SFpga>.
......@@ -138,7 +138,7 @@ Parsing module <SFpga>.
=========================================================================
Elaborating module <SFpga>.
WARNING:HDLCompiler:1016 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 487: Port osc_clk is not connected to this instance
WARNING:HDLCompiler:1016 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 507: Port osc_clk is not connected to this instance
Elaborating module <SystemFpga>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 325: Assignment to DdrLDQS_io ignored, since the identifier is never used
......@@ -155,12 +155,12 @@ Elaborating module <InterruptManagerWB>.
Elaborating module <AddressDecoderWBSys>.
Elaborating module <Generic4OutputRegs(Reg2Default=32'b01000100010001000)>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 548: Assignment to GenericOutputReg3 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 568: Assignment to GenericOutputReg3 ignored, since the identifier is never used
Elaborating module <Generic4InputRegs>.
Elaborating module <Slv2SerWB>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 588: Assignment to AFpgaProgDone_io ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to AFpgaProgDone_io ignored, since the identifier is never used
Elaborating module <SpiMasterWB>.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net <GenericInputReg1[31]> does not have a driver.
......@@ -264,8 +264,8 @@ WARNING:Xst:647 - Input <Gbit12RefClk_ik> is never used. This port will be prese
WARNING:Xst:647 - Input <Gbit3App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit4App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit34RefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 487: Output port <osc_clk> of the instance <i_InterruptManager> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 535: Output port <Reg3Value_ob32> of the instance <i_Generic4OutputRegs> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 507: Output port <osc_clk> of the instance <i_InterruptManager> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 555: Output port <Reg3Value_ob32> of the instance <i_Generic4OutputRegs> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <GenericInputReg1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
......@@ -283,9 +283,9 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 2-bit register for signal <VmeSysReset_dx>.
Found 1-bit register for signal <Rst_rq>.
Found 24-bit register for signal <Si57xDivider_c>.
Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_9_OUT> created at line 380.
Found 24-bit adder for signal <VcTcXoDivider_c[23]_GND_2_o_add_12_OUT> created at line 383.
Found 24-bit adder for signal <VmeSysClkDivider_c[23]_GND_2_o_add_15_OUT> created at line 386.
Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_7_OUT> created at line 376.
Found 24-bit adder for signal <VcTcXoDivider_c[23]_GND_2_o_add_10_OUT> created at line 379.
Found 24-bit adder for signal <VmeSysClkDivider_c[23]_GND_2_o_add_13_OUT> created at line 382.
Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 296
Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 300
Found 1-bit tristate buffer for signal <Fmc1SDa_io> created at line 305
......@@ -308,16 +308,16 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315
Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338
Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 374
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 375
Found 1-bit tristate buffer for signal <FpLed_onb8<2>> created at line 376
Found 1-bit tristate buffer for signal <FpLed_onb8<3>> created at line 377
Found 1-bit tristate buffer for signal <FpLed_onb8<4>> created at line 397
Found 1-bit tristate buffer for signal <FpLed_onb8<5>> created at line 398
Found 1-bit tristate buffer for signal <FpLed_onb8<6>> created at line 399
Found 1-bit tristate buffer for signal <FpLed_onb8<7>> created at line 400
Found 1-bit tristate buffer for signal <AFpgaProgProgram_o> created at line 589
Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 636
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 408
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 409
Found 1-bit tristate buffer for signal <FpLed_onb8<2>> created at line 410
Found 1-bit tristate buffer for signal <FpLed_onb8<3>> created at line 411
Found 1-bit tristate buffer for signal <FpLed_onb8<4>> created at line 412
Found 1-bit tristate buffer for signal <FpLed_onb8<5>> created at line 413
Found 1-bit tristate buffer for signal <FpLed_onb8<6>> created at line 414
Found 1-bit tristate buffer for signal <FpLed_onb8<7>> created at line 418
Found 1-bit tristate buffer for signal <AFpgaProgProgram_o> created at line 609
Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 656
Summary:
inferred 3 Adder/Subtractor(s).
inferred 76 D-type flip-flop(s).
......@@ -326,15 +326,15 @@ Unit <SystemFpga> synthesized.
Synthesizing Unit <Monostable>.
Related source file is "/vfc_svn/hdl/design/monostable.v".
g_CounterBits = 26
g_CounterBits = 23
Found 4-bit register for signal <AsynchInAX_db4>.
Found 26-bit register for signal <Counter_c>.
Found 23-bit register for signal <Counter_c>.
Found 1-bit register for signal <SynchOutput_oq>.
Found 1-bit register for signal <AsynchIn_ax>.
Found 26-bit adder for signal <Counter_c[25]_GND_25_o_add_6_OUT> created at line 20.
Found 23-bit adder for signal <Counter_c[22]_GND_25_o_add_6_OUT> created at line 20.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 32 D-type flip-flop(s).
inferred 29 D-type flip-flop(s).
Unit <Monostable> synthesized.
Synthesizing Unit <Debouncer>.
......@@ -398,7 +398,7 @@ Synthesizing Unit <VmeInterfaceWB>.
Found 9-bit adder for signal <AckTimeout_c[8]_GND_35_o_add_16_OUT> created at line 100.
Found 22-bit adder for signal <adr_o[21]_GND_35_o_add_48_OUT> created at line 200.
Found 1-bit 4-to-1 multiplexer for signal <_n0284> created at line 148.
Found 1-bit 4-to-1 multiplexer for signal <_n0293> created at line 148.
Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148.
Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<29>> created at line 110
......@@ -498,7 +498,7 @@ Synthesizing Unit <Generic4OutputRegs>.
Found 32-bit register for signal <Reg2Value_ob32>.
Found 32-bit register for signal <Reg3Value_ob32>.
Found 32-bit register for signal <Reg0Value_ob32>.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 41.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 40.
Summary:
inferred 128 D-type flip-flop(s).
inferred 2 Multiplexer(s).
......@@ -614,8 +614,8 @@ Macro Statistics
12-bit adder : 1
16-bit adder : 2
22-bit adder : 1
23-bit adder : 3
24-bit adder : 3
26-bit adder : 3
3-bit adder : 2
4-bit addsub : 1
9-bit adder : 1
......@@ -625,8 +625,8 @@ Macro Statistics
16-bit register : 2
2-bit register : 4
22-bit register : 1
23-bit register : 3
24-bit register : 3
26-bit register : 3
3-bit register : 4
31-bit register : 1
32-bit register : 15
......@@ -703,8 +703,8 @@ Unit <Monostable> synthesized (advanced).
Synthesizing (advanced) Unit <SystemFpga>.
The following registers are absorbed into counter <VmeSysClkDivider_c>: 1 register on signal <VmeSysClkDivider_c>.
The following registers are absorbed into counter <VcTcXoDivider_c>: 1 register on signal <VcTcXoDivider_c>.
The following registers are absorbed into counter <Si57xDivider_c>: 1 register on signal <Si57xDivider_c>.
The following registers are absorbed into counter <VcTcXoDivider_c>: 1 register on signal <VcTcXoDivider_c>.
Unit <SystemFpga> synthesized (advanced).
Synthesizing (advanced) Unit <VmeInterfaceWB>.
......@@ -724,8 +724,8 @@ Macro Statistics
3-bit adder : 2
# Counters : 11
16-bit up counter : 1
23-bit up counter : 3
24-bit up counter : 3
26-bit up counter : 3
3-bit up counter : 2
4-bit updown counter : 1
9-bit up counter : 1
......@@ -847,8 +847,8 @@ Unit <SFpga> processed.
Final Register Report
Macro Statistics
# Registers : 837
Flip-Flops : 837
# Registers : 828
Flip-Flops : 828
# Shift Registers : 6
2-bit shift register : 2
3-bit shift register : 4
......@@ -874,25 +874,25 @@ Top Level Output File Name : SFpga.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1582
# BELS : 1555
# GND : 1
# INV : 32
# LUT1 : 206
# LUT1 : 197
# LUT2 : 168
# LUT3 : 130
# LUT4 : 113
# LUT5 : 145
# LUT6 : 304
# MUXCY : 229
# LUT4 : 116
# LUT5 : 148
# LUT6 : 298
# MUXCY : 220
# MUXF7 : 28
# VCC : 1
# XORCY : 225
# FlipFlops/Latches : 843
# XORCY : 216
# FlipFlops/Latches : 834
# FD : 195
# FDE : 102
# FDPE : 1
# FDR : 135
# FDRE : 351
# FDRE : 342
# FDS : 26
# FDSE : 33
# RAMS : 3
......@@ -901,10 +901,10 @@ Primitive and Black Box Usage:
# Shift Registers : 6
# SRLC16E : 6
# Clock Buffers : 4
# BUFG : 1
# BUFGP : 3
# IO Buffers : 302
# IBUF : 75
# BUFG : 2
# BUFGP : 2
# IO Buffers : 303
# IBUF : 76
# IBUFGDS : 6
# IOBUF : 32
# IOBUFDS : 2
......@@ -919,18 +919,18 @@ Selected Device : 6slx150tfgg676-3
Slice Logic Utilization:
Number of Slice Registers: 843 out of 184304 0%
Number of Slice LUTs: 1112 out of 92152 1%
Number used as Logic: 1098 out of 92152 1%
Number of Slice Registers: 834 out of 184304 0%
Number of Slice LUTs: 1103 out of 92152 1%
Number used as Logic: 1089 out of 92152 1%
Number used as Memory: 14 out of 21680 0%
Number used as RAM: 8
Number used as SRL: 6
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1328
Number with an unused Flip Flop: 485 out of 1328 36%
Number with an unused LUT: 216 out of 1328 16%
Number of fully used LUT-FF pairs: 627 out of 1328 47%
Number of LUT Flip Flop pairs used: 1319
Number with an unused Flip Flop: 485 out of 1319 36%
Number with an unused LUT: 216 out of 1319 16%
Number of fully used LUT-FF pairs: 618 out of 1319 46%
Number of unique control sets: 34
IO Utilization:
......@@ -961,8 +961,8 @@ Clock Information:
-----------------------------------+------------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------------------------------+-------+
Si57x_ik | IBUFGDS+BUFG | 733 |
VcTcXo_ik | BUFGP | 24 |
VcTcXo_ik | IBUF+BUFG | 724 |
Si57x_ik | IBUFGDS+BUFG | 24 |
VmeSysClk_ik | BUFGP | 24 |
i_Core/i_VmeInterface/stb_o | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax) | 1 |
i_Core/Rst_rq | NONE(i_Core/i_ClearMonostable/AsynchIn_ax) | 1 |
......@@ -989,15 +989,15 @@ Timing Details:
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'Si57x_ik'
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 8.328ns (frequency: 120.083MHz)
Total number of paths / destination ports: 46561 / 1699
Total number of paths / destination ports: 45868 / 1672
-------------------------------------------------------------------------
Delay: 8.328ns (Levels of Logic = 5)
Source: i_Core/i_VmeInterface/adr_o_21_1 (FF)
Destination: i_Core/i_VmeInterface/DataReg_31 (FF)
Source Clock: Si57x_ik rising
Destination Clock: Si57x_ik rising
Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising
Data Path: i_Core/i_VmeInterface/adr_o_21_1 to i_Core/i_VmeInterface/DataReg_31
Gate Net
......@@ -1015,47 +1015,47 @@ Delay: 8.328ns (Levels of Logic = 5)
(24.9% logic, 75.1% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Timing constraint: Default period analysis for Clock 'Si57x_ik'
Clock period: 2.365ns (frequency: 422.770MHz)
Total number of paths / destination ports: 300 / 24
-------------------------------------------------------------------------
Delay: 2.365ns (Levels of Logic = 25)
Source: i_Core/VcTcXoDivider_c_0 (FF)
Destination: i_Core/VcTcXoDivider_c_23 (FF)
Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising
Source: i_Core/Si57xDivider_c_0 (FF)
Destination: i_Core/Si57xDivider_c_23 (FF)
Source Clock: Si57x_ik rising
Destination Clock: Si57x_ik rising
Data Path: i_Core/VcTcXoDivider_c_0 to i_Core/VcTcXoDivider_c_23
Data Path: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_23
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.579 i_Core/VcTcXoDivider_c_0 (i_Core/VcTcXoDivider_c_0)
INV:I->O 1 0.255 0.000 i_Core/Mcount_VcTcXoDivider_c_lut<0>_INV_0 (i_Core/Mcount_VcTcXoDivider_c_lut<0>)
MUXCY:S->O 1 0.215 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<0> (i_Core/Mcount_VcTcXoDivider_c_cy<0>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<1> (i_Core/Mcount_VcTcXoDivider_c_cy<1>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<2> (i_Core/Mcount_VcTcXoDivider_c_cy<2>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<3> (i_Core/Mcount_VcTcXoDivider_c_cy<3>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<4> (i_Core/Mcount_VcTcXoDivider_c_cy<4>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<5> (i_Core/Mcount_VcTcXoDivider_c_cy<5>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<6> (i_Core/Mcount_VcTcXoDivider_c_cy<6>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<7> (i_Core/Mcount_VcTcXoDivider_c_cy<7>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<8> (i_Core/Mcount_VcTcXoDivider_c_cy<8>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<9> (i_Core/Mcount_VcTcXoDivider_c_cy<9>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<10> (i_Core/Mcount_VcTcXoDivider_c_cy<10>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<11> (i_Core/Mcount_VcTcXoDivider_c_cy<11>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<12> (i_Core/Mcount_VcTcXoDivider_c_cy<12>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<13> (i_Core/Mcount_VcTcXoDivider_c_cy<13>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<14> (i_Core/Mcount_VcTcXoDivider_c_cy<14>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<15> (i_Core/Mcount_VcTcXoDivider_c_cy<15>)