Skip to content

V
VME FMC Carrier VFC
Commit 12b83ada authored by Andrea Boccardi's avatar Andrea Boccardi
Browse files
Options

changed the clock source to the VCTCXO

parent bd941eab
Show whitespace changes
Inline Side-by-side
Showing with 32440 additions and 31197 deletions
trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
View file @ 12b83ada
......@@ -41,7 +41,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 14
Total memory usage is 154956 kilobytes
Total memory usage is 155532 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ 12b83ada
......@@ -93,3 +93,20 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.ncd
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngc
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngd
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngr
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
View file @ 12b83ada
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 13:48:21 2010
Mon Dec 20 17:36:28 2010
# NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.par
View file @ 12b83ada
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Mon Dec 20 13:47:50 2010
PCBE13225:: Mon Dec 20 17:35:53 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -21,16 +21,16 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 843 out of 184,304 1%
Number used as Flip Flops: 843
Number of Slice Registers: 834 out of 184,304 1%
Number used as Flip Flops: 834
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 993 out of 92,152 1%
Number used as logic: 951 out of 92,152 1%
Number using O6 output only: 595
Number using O5 output only: 196
Number using O5 and O6: 160
Number of Slice LUTs: 965 out of 92,152 1%
Number used as logic: 934 out of 92,152 1%
Number using O6 output only: 579
Number using O5 output only: 187
Number using O5 and O6: 168
Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 6
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 28
Number with same-slice register load: 18
Number used exclusively as route-thrus: 17
Number with same-slice register load: 7
Number with same-slice carry load: 10
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 395 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,152
Number with an unused Flip Flop: 387 out of 1,152 33%
Number with an unused LUT: 159 out of 1,152 13%
Number of fully used LUT-FF pairs: 606 out of 1,152 52%
Number of occupied Slices: 383 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,137
Number with an unused Flip Flop: 369 out of 1,137 32%
Number with an unused LUT: 172 out of 1,137 15%
Number of fully used LUT-FF pairs: 596 out of 1,137 52%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -155,29 +155,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 5380 unrouted; REAL time: 11 secs
Phase 1 : 5283 unrouted; REAL time: 12 secs
Phase 2 : 4700 unrouted; REAL time: 15 secs
Phase 2 : 4622 unrouted; REAL time: 16 secs
Phase 3 : 1691 unrouted; REAL time: 20 secs
Phase 3 : 1786 unrouted; REAL time: 24 secs
Phase 4 : 1691 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Phase 4 : 1786 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Total REAL time to Router completion: 29 secs
Total CPU time to Router completion: 29 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Total REAL time to Router completion: 32 secs
Total CPU time to Router completion: 30 secs
Partition Implementation Status
-------------------------------
......@@ -195,20 +195,20 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 227 | 0.253 | 1.701 |
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 210 | 0.329 | 1.697 |
+---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y10| No | 6 | 0.084 | 1.643 |
| Si57x_BUFG | BUFGMUX_X2Y4| No | 6 | 0.008 | 1.686 |
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.084 | 1.642 |
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y10| No | 6 | 0.084 | 1.639 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 14 | 0.177 | 1.690 |
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.188 | 1.690 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 211 | 0.000 | 4.695 |
| i_Core/Rst_rq | Local| | 197 | 0.000 | 3.235 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/WriteCycle | Local| | 1 | 0.000 | 3.167 |
| i_Core/WriteCycle | Local| | 1 | 0.000 | 2.542 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 5.423 |
| e/stb_o | Local| | 19 | 0.000 | 4.912 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -218,6 +218,8 @@ the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
......@@ -225,11 +227,22 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.224ns| 8.109ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.342ns| | 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 5.091ns| 4.909ns| 0| 0
lk_ik" 100 MHz HIGH 50% | HOLD | 0.482ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 7.500ns| 2.500ns| 0| 0
00 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" | SETUP | 7.730ns| 2.270ns| 0| 0
100 MHz HIGH 50% | HOLD | 0.521ns| | 0| 0
| MINPERIOD | 7.500ns| 2.500ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysC | SETUP | 22.874ns| 2.126ns| 0| 0
lk_ik" 40 MHz HIGH 50% | HOLD | 0.521ns| | 0| 0
| MINPERIOD | 22.500ns| 2.500ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.902ns| 3.431ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.392ns| | 0| 0
TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" | SETUP | 27.265ns| 12.735ns| 0| 0
25 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -242,10 +255,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 50 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 31 secs
Total REAL time to PAR completion: 35 secs
Total CPU time to PAR completion: 33 secs
Peak Memory Usage: 549 MB
Peak Memory Usage: 572 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ 12b83ada
//! **************************************************************************
// Written by: Map M.70d on Mon Dec 20 13:47:47 2010
// Written by: Map M.70d on Mon Dec 20 17:35:51 2010
//! **************************************************************************
SCHEMATIC START;
......@@ -334,19 +334,19 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "i_Core/Rst_rq" BEL
TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/VcTcXoDivider_c_22" BEL "i_Core/VcTcXoDivider_c_21" BEL
"i_Core/VcTcXoDivider_c_20" BEL "i_Core/VcTcXoDivider_c_19" BEL
"i_Core/VcTcXoDivider_c_18" BEL "i_Core/VcTcXoDivider_c_17" BEL
"i_Core/VcTcXoDivider_c_16" BEL "i_Core/VcTcXoDivider_c_15" BEL
"i_Core/VcTcXoDivider_c_14" BEL "i_Core/VcTcXoDivider_c_13" BEL
"i_Core/VcTcXoDivider_c_12" BEL "i_Core/VcTcXoDivider_c_11" BEL
"i_Core/VcTcXoDivider_c_10" BEL "i_Core/VcTcXoDivider_c_9" BEL
"i_Core/VcTcXoDivider_c_8" BEL "i_Core/VcTcXoDivider_c_7" BEL
"i_Core/VcTcXoDivider_c_6" BEL "i_Core/VcTcXoDivider_c_5" BEL
"i_Core/VcTcXoDivider_c_4" BEL "i_Core/VcTcXoDivider_c_3" BEL
"i_Core/VcTcXoDivider_c_2" BEL "i_Core/VcTcXoDivider_c_1" BEL
"i_Core/VcTcXoDivider_c_0" BEL "i_Core/Rst_rq" BEL
"i_Core/i_VmeInterface/state_FSM_FFd2" BEL
"i_Core/i_VmeInterface/stb_d" BEL "i_Core/i_VmeInterface/adr_o_21" BEL
"i_Core/i_VmeInterface/adr_o_20" BEL "i_Core/i_VmeInterface/adr_o_19"
......@@ -437,9 +437,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_24" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
......@@ -464,9 +461,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_ClearMonostable/Counter_c_25" BEL
"i_Core/i_ClearMonostable/Counter_c_24" BEL
"i_Core/i_ClearMonostable/Counter_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_22" BEL
"i_Core/i_ClearMonostable/Counter_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_20" BEL
......@@ -491,9 +485,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_25" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_24" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_23" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_22" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_21" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_20" BEL
......@@ -996,7 +987,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeInterface/AckTimeout_c_2" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "VcTcXo_ik_IBUF_BUFG" BEL
"i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
......@@ -1022,6 +1013,45 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP VmeSysClk_ik = BEL "i_Core/VmeSysClkDivider_c_23" BEL
"i_Core/VmeSysClkDivider_c_22" BEL "i_Core/VmeSysClkDivider_c_21" BEL
"i_Core/VmeSysClkDivider_c_20" BEL "i_Core/VmeSysClkDivider_c_19" BEL
"i_Core/VmeSysClkDivider_c_18" BEL "i_Core/VmeSysClkDivider_c_17" BEL
"i_Core/VmeSysClkDivider_c_16" BEL "i_Core/VmeSysClkDivider_c_15" BEL
"i_Core/VmeSysClkDivider_c_14" BEL "i_Core/VmeSysClkDivider_c_13" BEL
"i_Core/VmeSysClkDivider_c_12" BEL "i_Core/VmeSysClkDivider_c_11" BEL
"i_Core/VmeSysClkDivider_c_10" BEL "i_Core/VmeSysClkDivider_c_9" BEL
"i_Core/VmeSysClkDivider_c_8" BEL "i_Core/VmeSysClkDivider_c_7" BEL
"i_Core/VmeSysClkDivider_c_6" BEL "i_Core/VmeSysClkDivider_c_5" BEL
"i_Core/VmeSysClkDivider_c_4" BEL "i_Core/VmeSysClkDivider_c_3" BEL
"i_Core/VmeSysClkDivider_c_2" BEL "i_Core/VmeSysClkDivider_c_1" BEL
"i_Core/VmeSysClkDivider_c_0" BEL "VmeSysClk_ik_BUFGP/BUFG";
TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_30" BEL "i_Core/i_Slv2SerWB/Dat_xb32_29"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_28" BEL
......@@ -1078,7 +1108,10 @@ TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/AckI_d3_2" BEL "i_Core/i_Slv2SerWB/AckI_d3_1" BEL
"i_Core/i_Slv2SerWB/AckI_d3_0" BEL "SysAppClk_ik_BUFGP/BUFG";
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" 25 MHz HIGH 50%;
TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysClk_ik" 40 MHz HIGH 50%;
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 100 MHz HIGH 50%;
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 100 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 100 MHz HIGH 50%;
SCHEMATIC END;
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ 12b83ada
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.224" best="8.109" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.342" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.902" best="3.431" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.392" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.091" best="4.909" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.482" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="7.730" best="2.270" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VmeSysClk_ik = PERIOD TIMEGRP &quot;VmeSysClk_ik&quot; 40 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="22.874" best="2.126" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="22.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VcTcXo_ik = PERIOD TIMEGRP &quot;VcTcXo_ik&quot; 25 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="27.265" best="12.735" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.syr
View file @ 12b83ada
......@@ -4,13 +4,13 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: SFpga.prj
......@@ -129,7 +129,7 @@ Parsing module <AddressDecoderWBSys>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v\" into library work
Parsing module <SystemFpga>.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro <dly> is redefined.
WARNING:HDLCompiler:224 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 588: Assignment to input AFpgaProgDone_io
WARNING:HDLCompiler:224 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to input AFpgaProgDone_io
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v\" into library work
Parsing module <SFpga>.
......@@ -138,7 +138,7 @@ Parsing module <SFpga>.
=========================================================================
Elaborating module <SFpga>.
WARNING:HDLCompiler:1016 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 487: Port osc_clk is not connected to this instance
WARNING:HDLCompiler:1016 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 507: Port osc_clk is not connected to this instance
Elaborating module <SystemFpga>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 325: Assignment to DdrLDQS_io ignored, since the identifier is never used
......@@ -155,12 +155,12 @@ Elaborating module <InterruptManagerWB>.
Elaborating module <AddressDecoderWBSys>.
Elaborating module <Generic4OutputRegs(Reg2Default=32'b01000100010001000)>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 548: Assignment to GenericOutputReg3 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 568: Assignment to GenericOutputReg3 ignored, since the identifier is never used
Elaborating module <Generic4InputRegs>.
Elaborating module <Slv2SerWB>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 588: Assignment to AFpgaProgDone_io ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to AFpgaProgDone_io ignored, since the identifier is never used
Elaborating module <SpiMasterWB>.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net <GenericInputReg1[31]> does not have a driver.
......@@ -264,8 +264,8 @@ WARNING:Xst:647 - Input <Gbit12RefClk_ik> is never used. This port will be prese
WARNING:Xst:647 - Input <Gbit3App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit4App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit34RefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 487: Output port <osc_clk> of the instance <i_InterruptManager> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 535: Output port <Reg3Value_ob32> of the instance <i_Generic4OutputRegs> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 507: Output port <osc_clk> of the instance <i_InterruptManager> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 555: Output port <Reg3Value_ob32> of the instance <i_Generic4OutputRegs> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <GenericInputReg1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
......@@ -283,9 +283,9 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 2-bit register for signal <VmeSysReset_dx>.
Found 1-bit register for signal <Rst_rq>.
Found 24-bit register for signal <Si57xDivider_c>.
Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_9_OUT> created at line 380.
Found 24-bit adder for signal <VcTcXoDivider_c[23]_GND_2_o_add_12_OUT> created at line 383.
Found 24-bit adder for signal <VmeSysClkDivider_c[23]_GND_2_o_add_15_OUT> created at line 386.
Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_7_OUT> created at line 376.
Found 24-bit adder for signal <VcTcXoDivider_c[23]_GND_2_o_add_10_OUT> created at line 379.
Found 24-bit adder for signal <VmeSysClkDivider_c[23]_GND_2_o_add_13_OUT> created at line 382.
Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 296
Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 300
Found 1-bit tristate buffer for signal <Fmc1SDa_io> created at line 305
......@@ -308,16 +308,16 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315
Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338
Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 374
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 375
Found 1-bit tristate buffer for signal <FpLed_onb8<2>> created at line 376
Found 1-bit tristate buffer for signal <FpLed_onb8<3>> created at line 377
Found 1-bit tristate buffer for signal <FpLed_onb8<4>> created at line 397
Found 1-bit tristate buffer for signal <FpLed_onb8<5>> created at line 398
Found 1-bit tristate buffer for signal <FpLed_onb8<6>> created at line 399
Found 1-bit tristate buffer for signal <FpLed_onb8<7>> created at line 400
Found 1-bit tristate buffer for signal <AFpgaProgProgram_o> created at line 589
Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 636
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 408
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 409
Found 1-bit tristate buffer for signal <FpLed_onb8<2>> created at line 410
Found 1-bit tristate buffer for signal <FpLed_onb8<3>> created at line 411
Found 1-bit tristate buffer for signal <FpLed_onb8<4>> created at line 412
Found 1-bit tristate buffer for signal <FpLed_onb8<5>> created at line 413
Found 1-bit tristate buffer for signal <FpLed_onb8<6>> created at line 414
Found 1-bit tristate buffer for signal <FpLed_onb8<7>> created at line 418
Found 1-bit tristate buffer for signal <AFpgaProgProgram_o> created at line 609
Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 656
Summary:
inferred 3 Adder/Subtractor(s).
inferred 76 D-type flip-flop(s).
......@@ -326,15 +326,15 @@ Unit <SystemFpga> synthesized.
Synthesizing Unit <Monostable>.
Related source file is "/vfc_svn/hdl/design/monostable.v".
g_CounterBits = 26
g_CounterBits = 23
Found 4-bit register for signal <AsynchInAX_db4>.
Found 26-bit register for signal <Counter_c>.
Found 23-bit register for signal <Counter_c>.
Found 1-bit register for signal <SynchOutput_oq>.
Found 1-bit register for signal <AsynchIn_ax>.
Found 26-bit adder for signal <Counter_c[25]_GND_25_o_add_6_OUT> created at line 20.
Found 23-bit adder for signal <Counter_c[22]_GND_25_o_add_6_OUT> created at line 20.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 32 D-type flip-flop(s).
inferred 29 D-type flip-flop(s).
Unit <Monostable> synthesized.
Synthesizing Unit <Debouncer>.
......@@ -398,7 +398,7 @@ Synthesizing Unit <VmeInterfaceWB>.
Found 9-bit adder for signal <AckTimeout_c[8]_GND_35_o_add_16_OUT> created at line 100.
Found 22-bit adder for signal <adr_o[21]_GND_35_o_add_48_OUT> created at line 200.
Found 1-bit 4-to-1 multiplexer for signal <_n0284> created at line 148.
Found 1-bit 4-to-1 multiplexer for signal <_n0293> created at line 148.
Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148.
Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<29>> created at line 110
......@@ -498,7 +498,7 @@ Synthesizing Unit <Generic4OutputRegs>.
Found 32-bit register for signal <Reg2Value_ob32>.
Found 32-bit register for signal <Reg3Value_ob32>.
Found 32-bit register for signal <Reg0Value_ob32>.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 41.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 40.
Summary:
inferred 128 D-type flip-flop(s).
inferred 2 Multiplexer(s).
......@@ -614,8 +614,8 @@ Macro Statistics
12-bit adder : 1
16-bit adder : 2
22-bit adder : 1
23-bit adder : 3
24-bit adder : 3
26-bit adder : 3
3-bit adder : 2
4-bit addsub : 1
9-bit adder : 1
......@@ -625,8 +625,8 @@ Macro Statistics
16-bit register : 2
2-bit register : 4
22-bit register : 1
23-bit register : 3
24-bit register : 3
26-bit register : 3
3-bit register : 4
31-bit register : 1
32-bit register : 15
......@@ -703,8 +703,8 @@ Unit <Monostable> synthesized (advanced).
Synthesizing (advanced) Unit <SystemFpga>.
The following registers are absorbed into counter <VmeSysClkDivider_c>: 1 register on signal <VmeSysClkDivider_c>.
The following registers are absorbed into counter <VcTcXoDivider_c>: 1 register on signal <VcTcXoDivider_c>.
The following registers are absorbed into counter <Si57xDivider_c>: 1 register on signal <Si57xDivider_c>.
The following registers are absorbed into counter <VcTcXoDivider_c>: 1 register on signal <VcTcXoDivider_c>.
Unit <SystemFpga> synthesized (advanced).
Synthesizing (advanced) Unit <VmeInterfaceWB>.
......@@ -724,8 +724,8 @@ Macro Statistics
3-bit adder : 2
# Counters : 11
16-bit up counter : 1
23-bit up counter : 3
24-bit up counter : 3
26-bit up counter : 3
3-bit up counter : 2
4-bit updown counter : 1
9-bit up counter : 1
......@@ -847,8 +847,8 @@ Unit <SFpga> processed.
Final Register Report
Macro Statistics
# Registers : 837
Flip-Flops : 837
# Registers : 828
Flip-Flops : 828
# Shift Registers : 6
2-bit shift register : 2
3-bit shift register : 4
......@@ -874,25 +874,25 @@ Top Level Output File Name : SFpga.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1582
# BELS : 1555
# GND : 1
# INV : 32
# LUT1 : 206
# LUT1 : 197
# LUT2 : 168
# LUT3 : 130
# LUT4 : 113
# LUT5 : 145
# LUT6 : 304
# MUXCY : 229
# LUT4 : 116
# LUT5 : 148
# LUT6 : 298
# MUXCY : 220
# MUXF7 : 28
# VCC : 1
# XORCY : 225
# FlipFlops/Latches : 843
# XORCY : 216
# FlipFlops/Latches : 834
# FD : 195
# FDE : 102
# FDPE : 1
# FDR : 135
# FDRE : 351
# FDRE : 342
# FDS : 26
# FDSE : 33
# RAMS : 3
......@@ -901,10 +901,10 @@ Primitive and Black Box Usage:
# Shift Registers : 6
# SRLC16E : 6
# Clock Buffers : 4
# BUFG : 1
# BUFGP : 3
# IO Buffers : 302
# IBUF : 75
# BUFG : 2
# BUFGP : 2
# IO Buffers : 303
# IBUF : 76
# IBUFGDS : 6
# IOBUF : 32
# IOBUFDS : 2
......@@ -919,18 +919,18 @@ Selected Device : 6slx150tfgg676-3
Slice Logic Utilization:
Number of Slice Registers: 843 out of 184304 0%
Number of Slice LUTs: 1112 out of 92152 1%
Number used as Logic: 1098 out of 92152 1%
Number of Slice Registers: 834 out of 184304 0%
Number of Slice LUTs: 1103 out of 92152 1%
Number used as Logic: 1089 out of 92152 1%
Number used as Memory: 14 out of 21680 0%
Number used as RAM: 8
Number used as SRL: 6
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1328
Number with an unused Flip Flop: 485 out of 1328 36%
Number with an unused LUT: 216 out of 1328 16%
Number of fully used LUT-FF pairs: 627 out of 1328 47%
Number of LUT Flip Flop pairs used: 1319
Number with an unused Flip Flop: 485 out of 1319 36%
Number with an unused LUT: 216 out of 1319 16%
Number of fully used LUT-FF pairs: 618 out of 1319 46%
Number of unique control sets: 34
IO Utilization:
......@@ -961,8 +961,8 @@ Clock Information:
-----------------------------------+------------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------------------------------+-------+
Si57x_ik | IBUFGDS+BUFG | 733 |
VcTcXo_ik | BUFGP | 24 |
VcTcXo_ik | IBUF+BUFG | 724 |
Si57x_ik | IBUFGDS+BUFG | 24 |
VmeSysClk_ik | BUFGP | 24 |
i_Core/i_VmeInterface/stb_o | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax) | 1 |
i_Core/Rst_rq | NONE(i_Core/i_ClearMonostable/AsynchIn_ax) | 1 |
......@@ -989,15 +989,15 @@ Timing Details:
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'Si57x_ik'
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 8.328ns (frequency: 120.083MHz)
Total number of paths / destination ports: 46561 / 1699
Total number of paths / destination ports: 45868 / 1672
-------------------------------------------------------------------------
Delay: 8.328ns (Levels of Logic = 5)
Source: i_Core/i_VmeInterface/adr_o_21_1 (FF)
Destination: i_Core/i_VmeInterface/DataReg_31 (FF)
Source Clock: Si57x_ik rising
Destination Clock: Si57x_ik rising
Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising
Data Path: i_Core/i_VmeInterface/adr_o_21_1 to i_Core/i_VmeInterface/DataReg_31
Gate Net
......@@ -1015,47 +1015,47 @@ Delay: 8.328ns (Levels of Logic = 5)
(24.9% logic, 75.1% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Timing constraint: Default period analysis for Clock 'Si57x_ik'
Clock period: 2.365ns (frequency: 422.770MHz)
Total number of paths / destination ports: 300 / 24
-------------------------------------------------------------------------
Delay: 2.365ns (Levels of Logic = 25)
Source: i_Core/VcTcXoDivider_c_0 (FF)
Destination: i_Core/VcTcXoDivider_c_23 (FF)
Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising
Source: i_Core/Si57xDivider_c_0 (FF)
Destination: i_Core/Si57xDivider_c_23 (FF)
Source Clock: Si57x_ik rising
Destination Clock: Si57x_ik rising
Data Path: i_Core/VcTcXoDivider_c_0 to i_Core/VcTcXoDivider_c_23
Data Path: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_23
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.579 i_Core/VcTcXoDivider_c_0 (i_Core/VcTcXoDivider_c_0)
INV:I->O 1 0.255 0.000 i_Core/Mcount_VcTcXoDivider_c_lut<0>_INV_0 (i_Core/Mcount_VcTcXoDivider_c_lut<0>)
MUXCY:S->O 1 0.215 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<0> (i_Core/Mcount_VcTcXoDivider_c_cy<0>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<1> (i_Core/Mcount_VcTcXoDivider_c_cy<1>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<2> (i_Core/Mcount_VcTcXoDivider_c_cy<2>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<3> (i_Core/Mcount_VcTcXoDivider_c_cy<3>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<4> (i_Core/Mcount_VcTcXoDivider_c_cy<4>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<5> (i_Core/Mcount_VcTcXoDivider_c_cy<5>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<6> (i_Core/Mcount_VcTcXoDivider_c_cy<6>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<7> (i_Core/Mcount_VcTcXoDivider_c_cy<7>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<8> (i_Core/Mcount_VcTcXoDivider_c_cy<8>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<9> (i_Core/Mcount_VcTcXoDivider_c_cy<9>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<10> (i_Core/Mcount_VcTcXoDivider_c_cy<10>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<11> (i_Core/Mcount_VcTcXoDivider_c_cy<11>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<12> (i_Core/Mcount_VcTcXoDivider_c_cy<12>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<13> (i_Core/Mcount_VcTcXoDivider_c_cy<13>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<14> (i_Core/Mcount_VcTcXoDivider_c_cy<14>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<15> (i_Core/Mcount_VcTcXoDivider_c_cy<15>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<16> (i_Core/Mcount_VcTcXoDivider_c_cy<16>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<17> (i_Core/Mcount_VcTcXoDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<18> (i_Core/Mcount_VcTcXoDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<19> (i_Core/Mcount_VcTcXoDivider_c_cy<19>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<20> (i_Core/Mcount_VcTcXoDivider_c_cy<20>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<21> (i_Core/Mcount_VcTcXoDivider_c_cy<21>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<22> (i_Core/Mcount_VcTcXoDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VcTcXoDivider_c_xor<23> (i_Core/Result<23>1)
FD:D 0.074 i_Core/VcTcXoDivider_c_23
FD:C->Q 1 0.525 0.579 i_Core/Si57xDivider_c_0 (i_Core/Si57xDivider_c_0)
INV:I->O 1 0.255 0.000 i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0 (i_Core/Mcount_Si57xDivider_c_lut<0>)
MUXCY:S->O 1 0.215 0.000 i_Core/Mcount_Si57xDivider_c_cy<0> (i_Core/Mcount_Si57xDivider_c_cy<0>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<1> (i_Core/Mcount_Si57xDivider_c_cy<1>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<2> (i_Core/Mcount_Si57xDivider_c_cy<2>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<3> (i_Core/Mcount_Si57xDivider_c_cy<3>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<4> (i_Core/Mcount_Si57xDivider_c_cy<4>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<5> (i_Core/Mcount_Si57xDivider_c_cy<5>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<6> (i_Core/Mcount_Si57xDivider_c_cy<6>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<7> (i_Core/Mcount_Si57xDivider_c_cy<7>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<8> (i_Core/Mcount_Si57xDivider_c_cy<8>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<9> (i_Core/Mcount_Si57xDivider_c_cy<9>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<10> (i_Core/Mcount_Si57xDivider_c_cy<10>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<11> (i_Core/Mcount_Si57xDivider_c_cy<11>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<12> (i_Core/Mcount_Si57xDivider_c_cy<12>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<13> (i_Core/Mcount_Si57xDivider_c_cy<13>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<14> (i_Core/Mcount_Si57xDivider_c_cy<14>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<15> (i_Core/Mcount_Si57xDivider_c_cy<15>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<16> (i_Core/Mcount_Si57xDivider_c_cy<16>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<17> (i_Core/Mcount_Si57xDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<18> (i_Core/Mcount_Si57xDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<19> (i_Core/Mcount_Si57xDivider_c_cy<19>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<20> (i_Core/Mcount_Si57xDivider_c_cy<20>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<21> (i_Core/Mcount_Si57xDivider_c_cy<21>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<22> (i_Core/Mcount_Si57xDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_Si57xDivider_c_xor<23> (i_Core/Result<23>1)
FD:D 0.074 i_Core/Si57xDivider_c_23
----------------------------------------
Total 2.365ns (1.787ns logic, 0.579ns route)
(75.5% logic, 24.5% route)
......@@ -1195,13 +1195,13 @@ Delay: 3.056ns (Levels of Logic = 1)
(35.2% logic, 64.8% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Si57x_ik'
Timing constraint: Default OFFSET IN BEFORE for Clock 'VcTcXo_ik'
Total number of paths / destination ports: 1705 / 116
-------------------------------------------------------------------------
Offset: 8.362ns (Levels of Logic = 6)
Source: VmeGa_ib5n<0> (PAD)
Destination: i_Core/i_VmeInterface/adr_o_21 (FF)
Destination Clock: Si57x_ik rising
Destination Clock: VcTcXo_ik rising
Data Path: VmeGa_ib5n<0> to i_Core/i_VmeInterface/adr_o_21
Gate Net
......@@ -1238,13 +1238,13 @@ Offset: 1.918ns (Levels of Logic = 1)
(67.9% logic, 32.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Si57x_ik'
Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik'
Total number of paths / destination ports: 190 / 94
-------------------------------------------------------------------------
Offset: 6.030ns (Levels of Logic = 2)
Source: i_Core/i_SpiMasterWB/Config1_qb32_29 (FF)
Destination: FlashSFpgaD_o (PAD)
Source Clock: Si57x_ik rising
Source Clock: VcTcXo_ik rising
Data Path: i_Core/i_SpiMasterWB/Config1_qb32_29 to FlashSFpgaD_o
Gate Net
......@@ -1277,27 +1277,27 @@ Offset: 3.856ns (Levels of Logic = 1)
(84.0% logic, 16.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik'
Timing constraint: Default OFFSET OUT AFTER for Clock 'Si57x_ik'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 3.856ns (Levels of Logic = 1)
Source: i_Core/VcTcXoDivider_c_23 (FF)
Destination: FpLed_onb8<5> (PAD)
Source Clock: VcTcXo_ik rising
Source: i_Core/Si57xDivider_c_23 (FF)
Destination: FpLed_onb8<4> (PAD)
Source Clock: Si57x_ik rising
Data Path: i_Core/VcTcXoDivider_c_23 to FpLed_onb8<5>
Data Path: i_Core/Si57xDivider_c_23 to FpLed_onb8<4>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.616 i_Core/VcTcXoDivider_c_23 (i_Core/VcTcXoDivider_c_23)
OBUFT:T->O 2.715 FpLed_onb8_5_OBUFT (FpLed_onb8<5>)
FD:C->Q 2 0.525 0.616 i_Core/Si57xDivider_c_23 (i_Core/Si57xDivider_c_23)
OBUFT:T->O 2.715 FpLed_onb8_4_OBUFT (FpLed_onb8<4>)
----------------------------------------
Total 3.856ns (3.240ns logic, 0.616ns route)
(84.0% logic, 16.0% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 19 / 7
Total number of paths / destination ports: 13 / 7
-------------------------------------------------------------------------
Delay: 6.896ns (Levels of Logic = 4)
Source: VmeGa_ib5n<0> (PAD)
......@@ -1321,33 +1321,33 @@ Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock Si57x_ik
---------------------------+---------+---------+---------+---------+
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+
Si57x_ik | 8.328| | | |
SysAppClk_ik | 1.178| | | |
i_Core/Rst_rq | 1.141| | | |
i_Core/WriteCycle | 1.141| | | |
i_Core/i_VmeInterface/stb_o| 1.141| | | |
---------------------------+---------+---------+---------+---------+
---------------+---------+---------+---------+---------+
Si57x_ik | 2.365| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 3.078| | | |
SysAppClk_ik | 3.056| | | |
VcTcXo_ik | 3.078| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VcTcXo_ik
---------------+---------+---------+---------+---------+
---------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VcTcXo_ik | 2.365| | | |
---------------+---------+---------+---------+---------+
---------------------------+---------+---------+---------+---------+
SysAppClk_ik | 1.178| | | |
VcTcXo_ik | 8.328| | | |
i_Core/Rst_rq | 1.141| | | |
i_Core/WriteCycle | 1.141| | | |
i_Core/i_VmeInterface/stb_o| 1.141| | | |
---------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock VmeSysClk_ik
---------------+---------+---------+---------+---------+
......@@ -1384,12 +1384,12 @@ i_Core/i_VmeInterface/stb_o| 2.049| | | |
=========================================================================
Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 17.59 secs
Total REAL time to Xst completion: 16.00 secs
Total CPU time to Xst completion: 16.80 secs
-->
Total memory usage is 277584 kilobytes
Total memory usage is 280080 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 130 ( 0 filtered)
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.twr
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ucf
View file @ 12b83ada
......@@ -695,7 +695,14 @@ NET "WRTxFault_i" IOSTANDARD = LVCMOS33;
NET "VmeSysClk_ik" CLOCK_DEDICATED_ROUTE = "FALSE";
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/16
NET "Si57x_ik" TNM_NET = "Si57x_ik";
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 120 MHz HIGH 50 %;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/17
NET "SysAppClk_ik" TNM_NET = SysAppClk_ik;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/20
NET "VcTcXo_ik" TNM_NET = VcTcXo_ik;
TIMESPEC TS_VcTcXo_ik = PERIOD "VcTcXo_ik" 25 MHz HIGH 50%;
NET "VmeSysClk_ik" TNM_NET = VmeSysClk_ik;
TIMESPEC TS_VmeSysClk_ik = PERIOD "VmeSysClk_ik" 40 MHz HIGH 50%;
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 100 MHz HIGH 50%;
NET "Si57x_ikn" TNM_NET = Si57x_ikn;
TIMESPEC TS_Si57x_ikn = PERIOD "Si57x_ikn" 100 MHz HIGH 50%;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 100 MHz HIGH 50%;
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
View file @ 12b83ada
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 13:48:22 2010
Mon Dec 20 17:36:28 2010
All signals are completely routed.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_guide.ncd
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map
View file @ 12b83ada
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 13:46:59 2010
Mapped Date : Mon Dec 20 17:35:13 2010
Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
......@@ -87,20 +87,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 13 secs
Total REAL time at the beginning of Placer: 14 secs
Total CPU time at the beginning of Placer: 13 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:f1e2766b) REAL time: 17 secs
Phase 1.1 Initial Placement Analysis (Checksum:b839f44f) REAL time: 18 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:f1e2766b) REAL time: 18 secs
Phase 2.7 Design Feasibility Check (Checksum:b839f44f) REAL time: 19 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f1e2766b) REAL time: 18 secs
Phase 3.31 Local Placement Optimization (Checksum:b839f44f) REAL time: 19 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
......@@ -118,42 +118,40 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:e552917b) REAL time: 24 secs
(Checksum:9f9006dc) REAL time: 25 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:e552917b) REAL time: 24 secs
Phase 5.36 Local Placement Optimization (Checksum:9f9006dc) REAL time: 25 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:e552917b) REAL time: 24 secs
Phase 6.30 Global Clock Region Assignment (Checksum:9f9006dc) REAL time: 25 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:c1877a) REAL time: 25 secs
Phase 7.3 Local Placement Optimization (Checksum:a3e805b0) REAL time: 26 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:e57e7026) REAL time: 25 secs
Phase 8.5 Local Placement Optimization (Checksum:9fbbfedd) REAL time: 26 secs
Phase 9.8 Global Placement
............
.......................
.......................
.....
Phase 9.8 Global Placement (Checksum:c376d41a) REAL time: 32 secs
.............
.......
Phase 9.8 Global Placement (Checksum:2989ec26) REAL time: 29 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:c376d41a) REAL time: 32 secs
Phase 10.5 Local Placement Optimization (Checksum:2989ec26) REAL time: 29 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:12757c2b) REAL time: 42 secs
Phase 11.18 Placement Optimization (Checksum:7e859587) REAL time: 31 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:12757c2b) REAL time: 42 secs
Phase 12.5 Local Placement Optimization (Checksum:7e859587) REAL time: 31 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:7e9272bf) REAL time: 42 secs
Phase 13.34 Placement Validation (Checksum:9557604f) REAL time: 31 secs
Total REAL time to Placer completion: 47 secs
Total CPU time to Placer completion: 47 secs
Total REAL time to Placer completion: 36 secs
Total CPU time to Placer completion: 35 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_Core/WriteCycle is
......@@ -268,16 +266,16 @@ Design Summary:
Number of errors: 0
Number of warnings: 86
Slice Logic Utilization:
Number of Slice Registers: 843 out of 184,304 1%
Number used as Flip Flops: 843
Number of Slice Registers: 834 out of 184,304 1%
Number used as Flip Flops: 834
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 993 out of 92,152 1%
Number used as logic: 951 out of 92,152 1%
Number using O6 output only: 595
Number using O5 output only: 196
Number using O5 and O6: 160
Number of Slice LUTs: 965 out of 92,152 1%
Number used as logic: 934 out of 92,152 1%
Number using O6 output only: 579
Number using O5 output only: 187
Number using O5 and O6: 168
Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -289,20 +287,20 @@ Slice Logic Utilization:
Number using O6 output only: 6
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 28
Number with same-slice register load: 18
Number used exclusively as route-thrus: 17
Number with same-slice register load: 7
Number with same-slice carry load: 10
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 395 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,152
Number with an unused Flip Flop: 387 out of 1,152 33%
Number with an unused LUT: 159 out of 1,152 13%
Number of fully used LUT-FF pairs: 606 out of 1,152 52%
Number of occupied Slices: 383 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,137
Number with an unused Flip Flop: 369 out of 1,137 32%
Number with an unused LUT: 172 out of 1,137 15%
Number of fully used LUT-FF pairs: 596 out of 1,137 52%
Number of unique control sets: 34
Number of slice register sites lost
to control set restrictions: 91 out of 184,304 1%
to control set restrictions: 76 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -343,11 +341,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02
Average Fanout of Non-Clock Nets: 3.00
Peak Memory Usage: 632 MB
Total REAL time to MAP completion: 49 secs
Total CPU time to MAP completion: 48 secs
Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 38 secs
Total CPU time to MAP completion: 36 secs
Mapping completed.
See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp
View file @ 12b83ada
......@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 13:46:59 2010
Mapped Date : Mon Dec 20 17:35:13 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 86
Slice Logic Utilization:
Number of Slice Registers: 843 out of 184,304 1%
Number used as Flip Flops: 843
Number of Slice Registers: 834 out of 184,304 1%
Number used as Flip Flops: 834
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 993 out of 92,152 1%
Number used as logic: 951 out of 92,152 1%
Number using O6 output only: 595
Number using O5 output only: 196
Number using O5 and O6: 160
Number of Slice LUTs: 965 out of 92,152 1%
Number used as logic: 934 out of 92,152 1%
Number using O6 output only: 579
Number using O5 output only: 187
Number using O5 and O6: 168
Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -38,20 +38,20 @@ Slice Logic Utilization:
Number using O6 output only: 6
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 28
Number with same-slice register load: 18
Number used exclusively as route-thrus: 17
Number with same-slice register load: 7
Number with same-slice carry load: 10
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 395 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,152
Number with an unused Flip Flop: 387 out of 1,152 33%
Number with an unused LUT: 159 out of 1,152 13%
Number of fully used LUT-FF pairs: 606 out of 1,152 52%
Number of occupied Slices: 383 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,137
Number with an unused Flip Flop: 369 out of 1,137 32%
Number with an unused LUT: 172 out of 1,137 15%
Number of fully used LUT-FF pairs: 596 out of 1,137 52%
Number of unique control sets: 34
Number of slice register sites lost
to control set restrictions: 91 out of 184,304 1%
to control set restrictions: 76 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02
Average Fanout of Non-Clock Nets: 3.00
Peak Memory Usage: 632 MB
Total REAL time to MAP completion: 49 secs
Total CPU time to MAP completion: 48 secs
Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 38 secs
Total CPU time to MAP completion: 36 secs
Table of Contents
-----------------
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ncd
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ngm
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.xrpt
View file @ 12b83ada
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Mon Dec 20 13:47:48 2010">
<application stringID="Map" timeStamp="Mon Dec 20 17:35:52 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -64,16 +64,16 @@
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/>
</section>
<task stringID="MAP_PACK_REPORT">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="843">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="843"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="834">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="834"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="975">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="196"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="595"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="160"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="958">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="187"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="579"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="168"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
......@@ -116,21 +116,21 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="86"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="647668"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="49 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="48 secs "/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="644020"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="38 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="36 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="843">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="843"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="834">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="834"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="993">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="196"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="595"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="160"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="965">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="187"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="579"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="168"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
......@@ -144,21 +144,21 @@
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="6"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="10"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="18"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="18"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="10"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="395">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="91"/>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="383">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="88"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="300"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="291"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1152">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="387"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="159"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="606"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1137">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="369"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="172"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="596"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt
View file @ 12b83ada
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Mon Dec 20 13:46:57 2010">
<application stringID="NgdBuild" timeStamp="Mon Dec 20 17:35:12 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -66,28 +66,28 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="195"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="102"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="351"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="342"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="75"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="76"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="206"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="197"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="168"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="113"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="145"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="304"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="229"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="116"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="298"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="220"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
......@@ -96,7 +96,7 @@
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="225"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="216"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/>
......@@ -104,22 +104,22 @@
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="102"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="351"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="342"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="156"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="157"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="206"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="197"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="168"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="113"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="145"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="304"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="229"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="116"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="298"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="220"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
......@@ -129,7 +129,7 @@
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="225"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="216"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ 12b83ada
#Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Mon Dec 20 13:48:21 2010
#Mon Dec 20 17:36:28 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ 12b83ada
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 13:48:21 2010
Mon Dec 20 17:36:28 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_par.xrpt
View file @ 12b83ada
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Mon Dec 20 13:47:59 2010">
<application stringID="par" timeStamp="Mon Dec 20 17:36:03 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -59,12 +59,12 @@
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="29 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="29 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="32 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="30 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="31 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="31 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="35 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="33 secs "/>
</section>
</task>
<task stringID="PAR_par">
......@@ -79,48 +79,48 @@
<column label="Net Skew(ns)" stringID="NET_SKEW"/>
<column label="Max Delay(ns)" stringID="MAX_DELAY"/>
<row stringID="row" value="1">
<item label="Clock Net" stringID="CLOCK_NET" value="Si57x_BUFG"/>
<item label="Clock Net" stringID="CLOCK_NET" value="VcTcXo_ik_IBUF_BUFG"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y16"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="227.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.253000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.701000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="210.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.329000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.697000"/>
</row>
<row stringID="row" value="2">
<item label="Clock Net" stringID="CLOCK_NET" value="VmeSysClk_ik_BUFGP"/>
<item label="Clock Net" stringID="CLOCK_NET" value="Si57x_BUFG"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y10"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="6.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.084000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.643000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.008000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.686000"/>
</row>
<row stringID="row" value="3">
<item label="Clock Net" stringID="CLOCK_NET" value="VcTcXo_ik_BUFGP"/>
<item label="Clock Net" stringID="CLOCK_NET" value="VmeSysClk_ik_BUFGP"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y16"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y10"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="6.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.084000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.642000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.639000"/>
</row>
<row stringID="row" value="4">
<item label="Clock Net" stringID="CLOCK_NET" value="SysAppClk_ik_BUFGP"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="14.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.177000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.188000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.690000"/>
</row>
<row stringID="row" value="5">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/Rst_rq"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="211.000000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="197.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.695000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="3.235000"/>
</row>
<row stringID="row" value="6">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/WriteCycle"/>
......@@ -128,7 +128,7 @@
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="1.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="3.167000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.542000"/>
</row>
<row stringID="row" value="7">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/stb_o"/>
......@@ -136,7 +136,7 @@
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="19.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="5.423000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.912000"/>
</row>
</table>
</section>
......@@ -6295,7 +6295,7 @@
</task>
</application>
<application stringID="Par" timeStamp="Mon Dec 20 13:47:59 2010">
<application stringID="Par" timeStamp="Mon Dec 20 17:36:04 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -6341,16 +6341,16 @@
</section>
<task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
<section stringID="PAR_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="843">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="843"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="834">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="834"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="993">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="196"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="595"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="160"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="965">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="187"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="579"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="168"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
......@@ -6364,21 +6364,21 @@
<item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="6"/>
<item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="10"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="18"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="7"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="18"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="7"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="10"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="395">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="91"/>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="383">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="88"/>
<item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="300"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="291"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1152">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="387"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="159"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="606"/>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1137">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="369"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="172"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="596"/>
</item>
</section>
<section stringID="PAR_IOB_REPORTING">
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.html
View file @ 12b83ada
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (12/20/2010 - 13:49:08)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (12/20/2010 - 17:37:16)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>SystemFpga.xise</TD>
......@@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>334 Warnings (2 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>334 Warnings (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
......@@ -60,13 +60,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>843</TD>
<TD ALIGN=RIGHT>834</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>843</TD>
<TD ALIGN=RIGHT>834</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -90,31 +90,31 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>993</TD>
<TD ALIGN=RIGHT>965</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>951</TD>
<TD ALIGN=RIGHT>934</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>595</TD>
<TD ALIGN=RIGHT>579</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>196</TD>
<TD ALIGN=RIGHT>187</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>160</TD>
<TD ALIGN=RIGHT>168</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -186,13 +186,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>28</TD>
<TD ALIGN=RIGHT>17</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>18</TD>
<TD ALIGN=RIGHT>7</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -210,32 +210,32 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>395</TD>
<TD ALIGN=RIGHT>383</TD>
<TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>1,152</TD>
<TD ALIGN=RIGHT>1,137</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>387</TD>
<TD ALIGN=RIGHT>1,152</TD>
<TD ALIGN=RIGHT>33%</TD>
<TD ALIGN=RIGHT>369</TD>
<TD ALIGN=RIGHT>1,137</TD>
<TD ALIGN=RIGHT>32%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>159</TD>
<TD ALIGN=RIGHT>1,152</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD ALIGN=RIGHT>172</TD>
<TD ALIGN=RIGHT>1,137</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>606</TD>
<TD ALIGN=RIGHT>1,152</TD>
<TD ALIGN=RIGHT>596</TD>
<TD ALIGN=RIGHT>1,137</TD>
<TD ALIGN=RIGHT>52%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
......@@ -246,7 +246,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>91</TD>
<TD ALIGN=RIGHT>76</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -426,7 +426,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.02</TD>
<TD ALIGN=RIGHT>3.00</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -463,23 +463,23 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 13:46:53 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>130 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (2 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 13:46:57 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 13:47:48 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>86 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 13:48:22 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:23:02 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>130 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (2 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:35:12 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:35:52 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>86 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:36:29 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 13:48:34 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 13:49:03 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>52 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:36:41 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 17:37:11 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu 16. Dec 17:57:34 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 15. Dec 15:16:36 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 20. Dec 13:49:03 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 20. Dec 13:49:08 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 20. Dec 17:37:11 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 20. Dec 17:37:16 2010</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 12/20/2010 - 15:32:38</center>
<br><center><b>Date Generated:</b> 12/20/2010 - 17:37:17</center>
</BODY></HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ 12b83ada
......@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="21">
<DesignSummary rev="27">
<CmdHistory>
</CmdHistory>
</DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_usage.xml
View file @ 12b83ada
......@@ -4,802 +4,802 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="21">
<DesignStatistics TimeStamp="Mon Dec 20 13:49:02 2010"><group name="NetStatistics">
<item name="NumNets_Active" rev="21">
<attrib name="value" value="1920"/></item>
<item name="NumNets_Gnd" rev="21">
<DeviceUsageSummary rev="27">
<DesignStatistics TimeStamp="Mon Dec 20 17:37:10 2010"><group name="NetStatistics">
<item name="NumNets_Active" rev="27">
<attrib name="value" value="1908"/></item>
<item name="NumNets_Gnd" rev="27">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="21">
<item name="NumNets_Vcc" rev="27">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="21">
<attrib name="value" value="36"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="21">
<attrib name="value" value="238"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="21">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="21">
<attrib name="value" value="17"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="21">
<attrib name="value" value="256"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="21">
<attrib name="value" value="23"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="21">
<attrib name="value" value="320"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="21">
<attrib name="value" value="2039"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="21">
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="27">
<attrib name="value" value="25"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="27">
<attrib name="value" value="200"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="27">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="27">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="27">
<attrib name="value" value="241"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="27">
<attrib name="value" value="26"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="27">
<attrib name="value" value="287"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="27">
<attrib name="value" value="2086"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="27">
<attrib name="value" value="354"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="21">
<attrib name="value" value="150"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="21">
<attrib name="value" value="63"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="21">
<item name="NumNodesOfType_Active_GLOBAL" rev="27">
<attrib name="value" value="181"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="27">
<attrib name="value" value="60"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="27">
<attrib name="value" value="243"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="21">
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="27">
<attrib name="value" value="243"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="21">
<attrib name="value" value="3771"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="21">
<attrib name="value" value="1596"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="21">
<attrib name="value" value="1469"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="21">
<item name="NumNodesOfType_Active_LUTINPUT" rev="27">
<attrib name="value" value="3723"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="27">
<attrib name="value" value="1593"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="27">
<attrib name="value" value="1471"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="27">
<attrib name="value" value="137"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="21">
<item name="NumNodesOfType_Active_PADOUTPUT" rev="27">
<attrib name="value" value="114"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="21">
<attrib name="value" value="874"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="21">
<attrib name="value" value="4346"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="21">
<attrib name="value" value="5321"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="21">
<attrib name="value" value="287"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="21">
<attrib name="value" value="2269"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="21">
<item name="NumNodesOfType_Active_PINBOUNCE" rev="27">
<attrib name="value" value="839"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="27">
<attrib name="value" value="4266"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="27">
<attrib name="value" value="5699"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="27">
<attrib name="value" value="293"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="27">
<attrib name="value" value="2377"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="27">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="21">
<item name="NumNodesOfType_Vcc_GENERIC" rev="27">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="21">
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="27">
<attrib name="value" value="143"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="21">
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="27">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="21">
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="27">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="21">
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="27">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="21">
<attrib name="value" value="390"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="21">
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="27">
<attrib name="value" value="386"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="27">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="21">
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="27">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="21">
<attrib name="value" value="403"/></item>
<item name="NumNodesOfType_Vcc_REGINPUT" rev="21">
<item name="NumNodesOfType_Vcc_PINFEED" rev="27">
<attrib name="value" value="399"/></item>
<item name="NumNodesOfType_Vcc_REGINPUT" rev="27">
<attrib name="value" value="11"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="21">
<item name="BUFG-BUFGMUX" rev="27">
<attrib name="value" value="4"/></item>
<item name="IOB-IOBM" rev="21">
<item name="IOB-IOBM" rev="27">
<attrib name="value" value="162"/></item>
<item name="IOB-IOBS" rev="21">
<item name="IOB-IOBS" rev="27">
<attrib name="value" value="165"/></item>
<item name="SLICEL-SLICEM" rev="21">
<attrib name="value" value="47"/></item>
<item name="SLICEX-SLICEL" rev="21">
<attrib name="value" value="71"/></item>
<item name="SLICEX-SLICEM" rev="21">
<attrib name="value" value="63"/></item>
<item name="SLICEL-SLICEM" rev="27">
<attrib name="value" value="33"/></item>
<item name="SLICEX-SLICEL" rev="27">
<attrib name="value" value="61"/></item>
<item name="SLICEX-SLICEM" rev="27">
<attrib name="value" value="75"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="20">
<item name="AGG_BONDED_IO" rev="26">
<attrib name="value" value="331"/></item>
<item name="AGG_IO" rev="20">
<item name="AGG_IO" rev="26">
<attrib name="value" value="331"/></item>
<item name="AGG_LOCED_IO" rev="20">
<item name="AGG_LOCED_IO" rev="26">
<attrib name="value" value="329"/></item>
<item name="AGG_SLICE" rev="20">
<attrib name="value" value="395"/></item>
<item name="NUM_BONDED_IOB" rev="20">
<item name="AGG_SLICE" rev="26">
<attrib name="value" value="383"/></item>
<item name="NUM_BONDED_IOB" rev="26">
<attrib name="value" value="327"/></item>
<item name="NUM_BONDED_IOBM" rev="20">
<item name="NUM_BONDED_IOBM" rev="26">
<attrib name="value" value="2"/></item>
<item name="NUM_BONDED_IOBS" rev="20">
<item name="NUM_BONDED_IOBS" rev="26">
<attrib name="value" value="2"/></item>
<item name="NUM_BSFULL" rev="20">
<attrib name="value" value="606"/></item>
<item name="NUM_BSLUTONLY" rev="20">
<attrib name="value" value="387"/></item>
<item name="NUM_BSREGONLY" rev="20">
<attrib name="value" value="159"/></item>
<item name="NUM_BSUSED" rev="20">
<attrib name="value" value="1152"/></item>
<item name="NUM_BUFG" rev="20">
<item name="NUM_BSFULL" rev="26">
<attrib name="value" value="596"/></item>
<item name="NUM_BSLUTONLY" rev="26">
<attrib name="value" value="369"/></item>
<item name="NUM_BSREGONLY" rev="26">
<attrib name="value" value="172"/></item>
<item name="NUM_BSUSED" rev="26">
<attrib name="value" value="1137"/></item>
<item name="NUM_BUFG" rev="26">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O5ANDO6" rev="20">
<item name="NUM_DPRAM_O5ANDO6" rev="26">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O6ONLY" rev="20">
<item name="NUM_DPRAM_O6ONLY" rev="26">
<attrib name="value" value="4"/></item>
<item name="NUM_LOCED_IOB" rev="20">
<item name="NUM_LOCED_IOB" rev="26">
<attrib name="value" value="325"/></item>
<item name="NUM_LOCED_IOBM" rev="20">
<item name="NUM_LOCED_IOBM" rev="26">
<attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOBS" rev="20">
<item name="NUM_LOCED_IOBS" rev="26">
<attrib name="value" value="2"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="20">
<attrib name="value" value="160"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="20">
<attrib name="value" value="196"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="20">
<attrib name="value" value="595"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="20">
<attrib name="value" value="10"/></item>
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="20">
<attrib name="value" value="18"/></item>
<item name="NUM_LUT_RT_EXO5" rev="20">
<attrib name="value" value="18"/></item>
<item name="NUM_LUT_RT_EXO6" rev="20">
<item name="NUM_LOGIC_O5ANDO6" rev="26">
<attrib name="value" value="168"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="26">
<attrib name="value" value="187"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="26">
<attrib name="value" value="579"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="26">
<attrib name="value" value="10"/></item>
<item name="NUM_LUT_RT_O5" rev="20">
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="26">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_EXO5" rev="26">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_EXO6" rev="26">
<attrib name="value" value="10"/></item>
<item name="NUM_LUT_RT_O6" rev="20">
<attrib name="value" value="196"/></item>
<item name="NUM_SLICEL" rev="20">
<attrib name="value" value="91"/></item>
<item name="NUM_SLICEM" rev="20">
<attrib name="value" value="4"/></item>
<item name="NUM_SLICEX" rev="20">
<attrib name="value" value="300"/></item>
<item name="NUM_SLICE_CARRY4" rev="20">
<attrib name="value" value="63"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="20">
<item name="NUM_LUT_RT_O5" rev="26">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_O6" rev="26">
<attrib name="value" value="187"/></item>
<item name="NUM_SLICEL" rev="26">
<attrib name="value" value="88"/></item>
<item name="NUM_SLICEM" rev="26">
<attrib name="value" value="4"/></item>
<item name="NUM_SLICEX" rev="26">
<attrib name="value" value="291"/></item>
<item name="NUM_SLICE_CARRY4" rev="26">
<attrib name="value" value="60"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="26">
<attrib name="value" value="34"/></item>
<item name="NUM_SLICE_CYINIT" rev="20">
<attrib name="value" value="1375"/></item>
<item name="NUM_SLICE_F7MUX" rev="20">
<item name="NUM_SLICE_CYINIT" rev="26">
<attrib name="value" value="1343"/></item>
<item name="NUM_SLICE_F7MUX" rev="26">
<attrib name="value" value="28"/></item>
<item name="NUM_SLICE_FF" rev="20">
<attrib name="value" value="843"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="20">
<attrib name="value" value="139"/></item>
<item name="NUM_SRL_O6ONLY" rev="20">
<item name="NUM_SLICE_FF" rev="26">
<attrib name="value" value="834"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="26">
<attrib name="value" value="142"/></item>
<item name="NUM_SRL_O6ONLY" rev="26">
<attrib name="value" value="6"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="20">
<attrib name="value" value="91"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="26">
<attrib name="value" value="76"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Mon Dec 20 13:49:02 2010"><group name="SiteSummary">
<item name="BUFG" rev="21">
<DeviceUsage TimeStamp="Mon Dec 20 17:37:10 2010"><group name="SiteSummary">
<item name="BUFG" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="BUFG_BUFG" rev="21">
<item name="BUFG_BUFG" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="CARRY4" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="63"/></item>
<item name="FF_SR" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="85"/></item>
<item name="HARD0" rev="21">
<item name="CARRY4" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="60"/></item>
<item name="FF_SR" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="73"/></item>
<item name="HARD0" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
<item name="IOB" rev="21">
<item name="IOB" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="327"/></item>
<item name="IOBM" rev="21">
<item name="IOBM" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBM_OUTBUF" rev="21">
<item name="IOBM_OUTBUF" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBS" rev="21">
<item name="IOBS" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB_IMUX" rev="21">
<item name="IOB_IMUX" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="160"/></item>
<item name="IOB_INBUF" rev="21">
<item name="IOB_INBUF" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="160"/></item>
<item name="IOB_OUTBUF" rev="21">
<item name="IOB_OUTBUF" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="198"/></item>
<item name="LUT5" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="384"/></item>
<item name="LUT6" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="961"/></item>
<item name="LUT_OR_MEM5" rev="21">
<item name="LUT5" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="369"/></item>
<item name="LUT6" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="944"/></item>
<item name="LUT_OR_MEM5" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="LUT_OR_MEM6" rev="21">
<item name="LUT_OR_MEM6" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="NULLMUX" rev="21">
<item name="NULLMUX" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="PAD" rev="21">
<item name="PAD" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="331"/></item>
<item name="REG_SR" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="758"/></item>
<item name="SELMUX2_1" rev="21">
<item name="REG_SR" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="761"/></item>
<item name="SELMUX2_1" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="28"/></item>
<item name="SLICEL" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="91"/></item>
<item name="SLICEM" rev="21">
<item name="SLICEL" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="88"/></item>
<item name="SLICEM" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="SLICEX" rev="21">
<attrib name="total" value="1000000"/><attrib name="used" value="300"/></item>
<item name="SLICEX" rev="27">
<attrib name="total" value="1000000"/><attrib name="used" value="291"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Mon Dec 20 13:49:02 2010"><group name="REG_SR">
<item name="CK" rev="21">
<attrib name="CK" value="758"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="21">
<attrib name="FF" value="758"/></item>
<item name="SRINIT" rev="21">
<attrib name="SRINIT0" value="706"/><attrib name="SRINIT1" value="52"/></item>
<item name="SYNC_ATTR" rev="21">
<attrib name="ASYNC" value="245"/><attrib name="SYNC" value="513"/></item>
<ReportConfigData TimeStamp="Mon Dec 20 17:37:10 2010"><group name="REG_SR">
<item name="CK" rev="27">
<attrib name="CK" value="761"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="27">
<attrib name="FF" value="761"/></item>
<item name="SRINIT" rev="27">
<attrib name="SRINIT0" value="709"/><attrib name="SRINIT1" value="52"/></item>
<item name="SYNC_ATTR" rev="27">
<attrib name="ASYNC" value="253"/><attrib name="SYNC" value="508"/></item>
</group>
<group name="LUT_OR_MEM5">
<item name="CLK" rev="21">
<item name="CLK" rev="27">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="21">
<item name="LUT_OR_MEM" rev="27">
<attrib name="RAM" value="4"/></item>
<item name="RAMMODE" rev="21">
<item name="RAMMODE" rev="27">
<attrib name="DPRAM32" value="4"/></item>
</group>
<group name="LUT_OR_MEM6">
<item name="CLK" rev="21">
<item name="CLK" rev="27">
<attrib name="CLK" value="14"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="21">
<item name="LUT_OR_MEM" rev="27">
<attrib name="RAM" value="14"/></item>
<item name="RAMMODE" rev="21">
<item name="RAMMODE" rev="27">
<attrib name="SRL16" value="6"/><attrib name="DPRAM32" value="4"/><attrib name="DPRAM64" value="4"/></item>
</group>
<group name="IOBM_OUTBUF">
<item name="SUSPEND" rev="21">
<item name="SUSPEND" rev="27">
<attrib name="3STATE" value="2"/></item>
</group>
<group name="SLICEL">
<item name="CLK" rev="21">
<attrib name="CLK" value="54"/><attrib name="CLK_INV" value="0"/></item>
<item name="CLK" rev="27">
<attrib name="CLK" value="47"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="SLICEM">
<item name="CLK" rev="21">
<item name="CLK" rev="27">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="21">
<item name="DRIVEATTRBOX" rev="27">
<attrib name="12" value="167"/></item>
<item name="SLEW" rev="21">
<item name="SLEW" rev="27">
<attrib name="SLOW" value="167"/></item>
<item name="SUSPEND" rev="21">
<item name="SUSPEND" rev="27">
<attrib name="3STATE" value="198"/></item>
</group>
<group name="SLICEX">
<item name="CLK" rev="21">
<attrib name="CLK" value="198"/><attrib name="CLK_INV" value="0"/></item>
<item name="CLK" rev="27">
<attrib name="CLK" value="190"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_INBUF">
<item name="DIFF_TERM" rev="21">
<item name="DIFF_TERM" rev="27">
<attrib name="TRUE" value="1"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="21">
<attrib name="CK" value="85"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="21">
<attrib name="SRINIT0" value="74"/><attrib name="SRINIT1" value="11"/></item>
<item name="SYNC_ATTR" rev="21">
<attrib name="ASYNC" value="53"/><attrib name="SYNC" value="32"/></item>
<item name="CK" rev="27">
<attrib name="CK" value="73"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="27">
<attrib name="SRINIT0" value="62"/><attrib name="SRINIT1" value="11"/></item>
<item name="SYNC_ATTR" rev="27">
<attrib name="ASYNC" value="45"/><attrib name="SYNC" value="28"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Mon Dec 20 13:49:02 2010"><group name="NULLMUX">
<item name="0" rev="21">
<ReportPinData TimeStamp="Mon Dec 20 17:37:10 2010"><group name="NULLMUX">
<item name="0" rev="27">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="21">
<item name="OUT" rev="27">
<attrib name="value" value="3"/></item>
</group>
<group name="REG_SR">
<item name="CE" rev="21">
<attrib name="value" value="435"/></item>
<item name="CK" rev="21">
<attrib name="value" value="758"/></item>
<item name="D" rev="21">
<attrib name="value" value="758"/></item>
<item name="Q" rev="21">
<attrib name="value" value="758"/></item>
<item name="SR" rev="21">
<attrib name="value" value="514"/></item>
<item name="CE" rev="27">
<attrib name="value" value="434"/></item>
<item name="CK" rev="27">
<attrib name="value" value="761"/></item>
<item name="D" rev="27">
<attrib name="value" value="761"/></item>
<item name="Q" rev="27">
<attrib name="value" value="761"/></item>
<item name="SR" rev="27">
<attrib name="value" value="509"/></item>
</group>
<group name="LUT_OR_MEM5">
<item name="A1" rev="21">
<item name="A1" rev="27">
<attrib name="value" value="4"/></item>
<item name="A2" rev="21">
<item name="A2" rev="27">
<attrib name="value" value="4"/></item>
<item name="A3" rev="21">
<item name="A3" rev="27">
<attrib name="value" value="4"/></item>
<item name="A4" rev="21">
<item name="A4" rev="27">
<attrib name="value" value="4"/></item>
<item name="A5" rev="21">
<item name="A5" rev="27">
<attrib name="value" value="4"/></item>
<item name="CLK" rev="21">
<item name="CLK" rev="27">
<attrib name="value" value="4"/></item>
<item name="DI1" rev="21">
<item name="DI1" rev="27">
<attrib name="value" value="4"/></item>
<item name="O5" rev="21">
<item name="O5" rev="27">
<attrib name="value" value="4"/></item>
<item name="WA1" rev="21">
<item name="WA1" rev="27">
<attrib name="value" value="4"/></item>
<item name="WA2" rev="21">
<item name="WA2" rev="27">
<attrib name="value" value="4"/></item>
<item name="WA3" rev="21">
<item name="WA3" rev="27">
<attrib name="value" value="4"/></item>
<item name="WA4" rev="21">
<item name="WA4" rev="27">
<attrib name="value" value="4"/></item>
<item name="WA5" rev="21">
<item name="WA5" rev="27">
<attrib name="value" value="4"/></item>
<item name="WE" rev="21">
<item name="WE" rev="27">
<attrib name="value" value="4"/></item>
</group>
<group name="LUT_OR_MEM6">
<item name="A1" rev="21">
<item name="A1" rev="27">
<attrib name="value" value="14"/></item>
<item name="A2" rev="21">
<item name="A2" rev="27">
<attrib name="value" value="14"/></item>
<item name="A3" rev="21">
<item name="A3" rev="27">
<attrib name="value" value="14"/></item>
<item name="A4" rev="21">
<item name="A4" rev="27">
<attrib name="value" value="14"/></item>
<item name="A5" rev="21">
<item name="A5" rev="27">
<attrib name="value" value="14"/></item>
<item name="A6" rev="21">
<item name="A6" rev="27">
<attrib name="value" value="14"/></item>
<item name="CLK" rev="21">
<item name="CLK" rev="27">
<attrib name="value" value="14"/></item>
<item name="DI1" rev="21">
<item name="DI1" rev="27">
<attrib name="value" value="4"/></item>
<item name="DI2" rev="21">
<item name="DI2" rev="27">
<attrib name="value" value="10"/></item>
<item name="O6" rev="21">
<item name="O6" rev="27">
<attrib name="value" value="11"/></item>
<item name="WA1" rev="21">
<item name="WA1" rev="27">
<attrib name="value" value="8"/></item>
<item name="WA2" rev="21">
<item name="WA2" rev="27">
<attrib name="value" value="8"/></item>
<item name="WA3" rev="21">
<item name="WA3" rev="27">
<attrib name="value" value="8"/></item>
<item name="WA4" rev="21">
<item name="WA4" rev="27">
<attrib name="value" value="8"/></item>
<item name="WA5" rev="21">
<item name="WA5" rev="27">
<attrib name="value" value="8"/></item>
<item name="WA6" rev="21">
<item name="WA6" rev="27">
<attrib name="value" value="8"/></item>
<item name="WE" rev="21">
<item name="WE" rev="27">
<attrib name="value" value="14"/></item>
</group>
<group name="IOBM_OUTBUF">
<item name="IN" rev="21">
<item name="IN" rev="27">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="21">
<item name="OUT" rev="27">
<attrib name="value" value="2"/></item>
<item name="OUTN" rev="21">
<item name="OUTN" rev="27">
<attrib name="value" value="2"/></item>
</group>
<group name="SLICEL">
<item name="A" rev="21">
<attrib name="value" value="13"/></item>
<item name="A1" rev="21">
<attrib name="value" value="9"/></item>
<item name="A2" rev="21">
<attrib name="value" value="17"/></item>
<item name="A3" rev="21">
<attrib name="value" value="19"/></item>
<item name="A4" rev="21">
<attrib name="value" value="64"/></item>
<item name="A5" rev="21">
<attrib name="value" value="33"/></item>
<item name="A6" rev="21">
<attrib name="value" value="77"/></item>
<item name="AMUX" rev="21">
<attrib name="value" value="17"/></item>
<item name="AQ" rev="21">
<attrib name="value" value="52"/></item>
<item name="AX" rev="21">
<item name="A" rev="27">
<attrib name="value" value="13"/></item>
<item name="B" rev="21">
<attrib name="value" value="11"/></item>
<item name="B1" rev="21">
<item name="A1" rev="27">
<attrib name="value" value="11"/></item>
<item name="B2" rev="21">
<attrib name="value" value="13"/></item>
<item name="B3" rev="21">
<item name="A2" rev="27">
<attrib name="value" value="15"/></item>
<item name="B4" rev="21">
<item name="A3" rev="27">
<attrib name="value" value="19"/></item>
<item name="A4" rev="27">
<attrib name="value" value="61"/></item>
<item name="B5" rev="21">
<item name="A5" rev="27">
<attrib name="value" value="33"/></item>
<item name="A6" rev="27">
<attrib name="value" value="74"/></item>
<item name="AMUX" rev="27">
<attrib name="value" value="19"/></item>
<item name="AQ" rev="27">
<attrib name="value" value="47"/></item>
<item name="AX" rev="27">
<attrib name="value" value="9"/></item>
<item name="B" rev="27">
<attrib name="value" value="11"/></item>
<item name="B1" rev="27">
<attrib name="value" value="10"/></item>
<item name="B2" rev="27">
<attrib name="value" value="12"/></item>
<item name="B3" rev="27">
<attrib name="value" value="14"/></item>
<item name="B4" rev="27">
<attrib name="value" value="58"/></item>
<item name="B5" rev="27">
<attrib name="value" value="30"/></item>
<item name="B6" rev="21">
<item name="B6" rev="27">
<attrib name="value" value="71"/></item>
<item name="BMUX" rev="21">
<item name="BMUX" rev="27">
<attrib name="value" value="18"/></item>
<item name="BQ" rev="21">
<attrib name="value" value="51"/></item>
<item name="BX" rev="21">
<attrib name="value" value="9"/></item>
<item name="C1" rev="21">
<item name="BQ" rev="27">
<attrib name="value" value="46"/></item>
<item name="BX" rev="27">
<attrib name="value" value="7"/></item>
<item name="C1" rev="27">
<attrib name="value" value="6"/></item>
<item name="C2" rev="27">
<attrib name="value" value="8"/></item>
<item name="C2" rev="21">
<attrib name="value" value="10"/></item>
<item name="C3" rev="21">
<item name="C3" rev="27">
<attrib name="value" value="20"/></item>
<item name="C4" rev="21">
<item name="C4" rev="27">
<attrib name="value" value="71"/></item>
<item name="C5" rev="21">
<item name="C5" rev="27">
<attrib name="value" value="45"/></item>
<item name="C6" rev="21">
<attrib name="value" value="85"/></item>
<item name="CE" rev="21">
<attrib name="value" value="30"/></item>
<item name="CIN" rev="21">
<attrib name="value" value="50"/></item>
<item name="CLK" rev="21">
<attrib name="value" value="54"/></item>
<item name="CMUX" rev="21">
<item name="C6" rev="27">
<attrib name="value" value="82"/></item>
<item name="CE" rev="27">
<attrib name="value" value="22"/></item>
<item name="CIN" rev="27">
<attrib name="value" value="47"/></item>
<item name="CLK" rev="27">
<attrib name="value" value="47"/></item>
<item name="CMUX" rev="27">
<attrib name="value" value="42"/></item>
<item name="COUT" rev="21">
<attrib name="value" value="50"/></item>
<item name="CQ" rev="21">
<attrib name="value" value="49"/></item>
<item name="CX" rev="21">
<item name="COUT" rev="27">
<attrib name="value" value="47"/></item>
<item name="CQ" rev="27">
<attrib name="value" value="47"/></item>
<item name="CX" rev="27">
<attrib name="value" value="31"/></item>
<item name="D1" rev="21">
<item name="D1" rev="27">
<attrib name="value" value="7"/></item>
<item name="D2" rev="21">
<item name="D2" rev="27">
<attrib name="value" value="31"/></item>
<item name="D3" rev="21">
<attrib name="value" value="34"/></item>
<item name="D4" rev="21">
<attrib name="value" value="74"/></item>
<item name="D5" rev="21">
<attrib name="value" value="44"/></item>
<item name="D6" rev="21">
<attrib name="value" value="82"/></item>
<item name="DMUX" rev="21">
<item name="D3" rev="27">
<attrib name="value" value="33"/></item>
<item name="D4" rev="27">
<attrib name="value" value="70"/></item>
<item name="D5" rev="27">
<attrib name="value" value="43"/></item>
<item name="D6" rev="27">
<attrib name="value" value="78"/></item>
<item name="DMUX" rev="27">
<attrib name="value" value="15"/></item>
<item name="DQ" rev="21">
<attrib name="value" value="48"/></item>
<item name="DX" rev="21">
<attrib name="value" value="9"/></item>
<item name="SR" rev="21">
<attrib name="value" value="36"/></item>
<item name="DQ" rev="27">
<attrib name="value" value="42"/></item>
<item name="DX" rev="27">
<attrib name="value" value="7"/></item>
<item name="SR" rev="27">
<attrib name="value" value="28"/></item>
</group>
<group name="SLICEM">
<item name="A" rev="21">
<item name="A" rev="27">
<attrib name="value" value="2"/></item>
<item name="A1" rev="21">
<item name="A1" rev="27">
<attrib name="value" value="3"/></item>
<item name="A2" rev="21">
<item name="A2" rev="27">
<attrib name="value" value="3"/></item>
<item name="A3" rev="21">
<item name="A3" rev="27">
<attrib name="value" value="3"/></item>
<item name="A4" rev="21">
<item name="A4" rev="27">
<attrib name="value" value="3"/></item>
<item name="A5" rev="21">
<item name="A5" rev="27">
<attrib name="value" value="3"/></item>
<item name="A6" rev="21">
<item name="A6" rev="27">
<attrib name="value" value="3"/></item>
<item name="AI" rev="21">
<item name="AI" rev="27">
<attrib name="value" value="2"/></item>
<item name="AMUX" rev="21">
<item name="AMUX" rev="27">
<attrib name="value" value="1"/></item>
<item name="AQ" rev="21">
<item name="AQ" rev="27">
<attrib name="value" value="1"/></item>
<item name="AX" rev="21">
<item name="AX" rev="27">
<attrib name="value" value="2"/></item>
<item name="B" rev="21">
<item name="B" rev="27">
<attrib name="value" value="2"/></item>
<item name="B1" rev="21">
<item name="B1" rev="27">
<attrib name="value" value="3"/></item>
<item name="B2" rev="21">
<item name="B2" rev="27">
<attrib name="value" value="3"/></item>
<item name="B3" rev="21">
<item name="B3" rev="27">
<attrib name="value" value="3"/></item>
<item name="B4" rev="21">
<item name="B4" rev="27">
<attrib name="value" value="3"/></item>
<item name="B5" rev="21">
<item name="B5" rev="27">
<attrib name="value" value="3"/></item>
<item name="B6" rev="21">
<item name="B6" rev="27">
<attrib name="value" value="3"/></item>
<item name="BI" rev="21">
<item name="BI" rev="27">
<attrib name="value" value="2"/></item>
<item name="BMUX" rev="21">
<item name="BMUX" rev="27">
<attrib name="value" value="1"/></item>
<item name="BQ" rev="21">
<item name="BQ" rev="27">
<attrib name="value" value="1"/></item>
<item name="BX" rev="21">
<item name="BX" rev="27">
<attrib name="value" value="1"/></item>
<item name="C" rev="21">
<item name="C" rev="27">
<attrib name="value" value="1"/></item>
<item name="C1" rev="21">
<item name="C1" rev="27">
<attrib name="value" value="4"/></item>
<item name="C2" rev="21">
<item name="C2" rev="27">
<attrib name="value" value="4"/></item>
<item name="C3" rev="21">
<item name="C3" rev="27">
<attrib name="value" value="4"/></item>
<item name="C4" rev="21">
<item name="C4" rev="27">
<attrib name="value" value="4"/></item>
<item name="C5" rev="21">
<item name="C5" rev="27">
<attrib name="value" value="4"/></item>
<item name="C6" rev="21">
<item name="C6" rev="27">
<attrib name="value" value="4"/></item>
<item name="CE" rev="21">
<item name="CE" rev="27">
<attrib name="value" value="4"/></item>
<item name="CI" rev="21">
<item name="CI" rev="27">
<attrib name="value" value="3"/></item>
<item name="CLK" rev="21">
<item name="CLK" rev="27">
<attrib name="value" value="4"/></item>
<item name="CMUX" rev="21">
<item name="CMUX" rev="27">
<attrib name="value" value="1"/></item>
<item name="CQ" rev="21">
<item name="CQ" rev="27">
<attrib name="value" value="2"/></item>
<item name="CX" rev="21">
<item name="CX" rev="27">
<attrib name="value" value="2"/></item>
<item name="D1" rev="21">
<item name="D1" rev="27">
<attrib name="value" value="4"/></item>
<item name="D2" rev="21">
<item name="D2" rev="27">
<attrib name="value" value="4"/></item>
<item name="D3" rev="21">
<item name="D3" rev="27">
<attrib name="value" value="4"/></item>
<item name="D4" rev="21">
<item name="D4" rev="27">
<attrib name="value" value="4"/></item>
<item name="D5" rev="21">
<item name="D5" rev="27">
<attrib name="value" value="4"/></item>
<item name="D6" rev="21">
<item name="D6" rev="27">
<attrib name="value" value="4"/></item>
<item name="DI" rev="21">
<item name="DI" rev="27">
<attrib name="value" value="3"/></item>
<item name="DMUX" rev="21">
<item name="DMUX" rev="27">
<attrib name="value" value="1"/></item>
<item name="DQ" rev="21">
<item name="DQ" rev="27">
<attrib name="value" value="2"/></item>
<item name="DX" rev="21">
<item name="DX" rev="27">
<attrib name="value" value="2"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="21">
<item name="IN" rev="27">
<attrib name="value" value="198"/></item>
<item name="OUT" rev="21">
<item name="OUT" rev="27">
<attrib name="value" value="198"/></item>
<item name="TRI" rev="21">
<item name="TRI" rev="27">
<attrib name="value" value="44"/></item>
</group>
<group name="SLICEX">
<item name="A" rev="21">
<attrib name="value" value="109"/></item>
<item name="A1" rev="21">
<attrib name="value" value="95"/></item>
<item name="A2" rev="21">
<attrib name="value" value="133"/></item>
<item name="A3" rev="21">
<attrib name="value" value="175"/></item>
<item name="A4" rev="21">
<attrib name="value" value="193"/></item>
<item name="A5" rev="21">
<attrib name="value" value="192"/></item>
<item name="A6" rev="21">
<attrib name="value" value="199"/></item>
<item name="AMUX" rev="21">
<item name="A" rev="27">
<attrib name="value" value="114"/></item>
<item name="A1" rev="27">
<attrib name="value" value="101"/></item>
<item name="A2" rev="27">
<attrib name="value" value="143"/></item>
<item name="A3" rev="27">
<attrib name="value" value="182"/></item>
<item name="A4" rev="27">
<attrib name="value" value="200"/></item>
<item name="A5" rev="27">
<attrib name="value" value="197"/></item>
<item name="A6" rev="27">
<attrib name="value" value="205"/></item>
<item name="AMUX" rev="27">
<attrib name="value" value="44"/></item>
<item name="AQ" rev="21">
<attrib name="value" value="161"/></item>
<item name="AX" rev="21">
<attrib name="value" value="57"/></item>
<item name="B" rev="21">
<attrib name="value" value="77"/></item>
<item name="B1" rev="21">
<attrib name="value" value="73"/></item>
<item name="B2" rev="21">
<attrib name="value" value="103"/></item>
<item name="B3" rev="21">
<attrib name="value" value="136"/></item>
<item name="B4" rev="21">
<attrib name="value" value="144"/></item>
<item name="B5" rev="21">
<attrib name="value" value="150"/></item>
<item name="B6" rev="21">
<attrib name="value" value="145"/></item>
<item name="BMUX" rev="21">
<attrib name="value" value="37"/></item>
<item name="BQ" rev="21">
<attrib name="value" value="128"/></item>
<item name="BX" rev="21">
<attrib name="value" value="59"/></item>
<item name="C" rev="21">
<attrib name="value" value="52"/></item>
<item name="C1" rev="21">
<attrib name="value" value="70"/></item>
<item name="C2" rev="21">
<attrib name="value" value="88"/></item>
<item name="C3" rev="21">
<attrib name="value" value="119"/></item>
<item name="C4" rev="21">
<attrib name="value" value="130"/></item>
<item name="C5" rev="21">
<item name="AQ" rev="27">
<attrib name="value" value="169"/></item>
<item name="AX" rev="27">
<attrib name="value" value="65"/></item>
<item name="B" rev="27">
<attrib name="value" value="72"/></item>
<item name="B1" rev="27">
<attrib name="value" value="64"/></item>
<item name="B2" rev="27">
<attrib name="value" value="99"/></item>
<item name="B3" rev="27">
<attrib name="value" value="129"/></item>
<item name="B4" rev="27">
<attrib name="value" value="140"/></item>
<item name="B5" rev="27">
<attrib name="value" value="142"/></item>
<item name="B6" rev="27">
<attrib name="value" value="142"/></item>
<item name="BMUX" rev="27">
<attrib name="value" value="35"/></item>
<item name="BQ" rev="27">
<attrib name="value" value="135"/></item>
<item name="C6" rev="21">
<attrib name="value" value="131"/></item>
<item name="CE" rev="21">
<attrib name="value" value="109"/></item>
<item name="CLK" rev="21">
<attrib name="value" value="198"/></item>
<item name="CMUX" rev="21">
<item name="BX" rev="27">
<attrib name="value" value="61"/></item>
<item name="C" rev="27">
<attrib name="value" value="52"/></item>
<item name="C1" rev="27">
<attrib name="value" value="78"/></item>
<item name="C2" rev="27">
<attrib name="value" value="98"/></item>
<item name="C3" rev="27">
<attrib name="value" value="123"/></item>
<item name="C4" rev="27">
<attrib name="value" value="132"/></item>
<item name="C5" rev="27">
<attrib name="value" value="134"/></item>
<item name="C6" rev="27">
<attrib name="value" value="133"/></item>
<item name="CE" rev="27">
<attrib name="value" value="101"/></item>
<item name="CLK" rev="27">
<attrib name="value" value="190"/></item>
<item name="CMUX" rev="27">
<attrib name="value" value="33"/></item>
<item name="CQ" rev="21">
<attrib name="value" value="137"/></item>
<item name="CX" rev="21">
<attrib name="value" value="54"/></item>
<item name="D" rev="21">
<attrib name="value" value="94"/></item>
<item name="D1" rev="21">
<attrib name="value" value="64"/></item>
<item name="D2" rev="21">
<attrib name="value" value="107"/></item>
<item name="D3" rev="21">
<attrib name="value" value="139"/></item>
<item name="D4" rev="21">
<attrib name="value" value="150"/></item>
<item name="D5" rev="21">
<attrib name="value" value="154"/></item>
<item name="D6" rev="21">
<attrib name="value" value="157"/></item>
<item name="DMUX" rev="21">
<attrib name="value" value="43"/></item>
<item name="DQ" rev="21">
<attrib name="value" value="126"/></item>
<item name="DX" rev="21">
<item name="CQ" rev="27">
<attrib name="value" value="146"/></item>
<item name="CX" rev="27">
<attrib name="value" value="58"/></item>
<item name="D" rev="27">
<attrib name="value" value="86"/></item>
<item name="D1" rev="27">
<attrib name="value" value="68"/></item>
<item name="D2" rev="27">
<attrib name="value" value="98"/></item>
<item name="D3" rev="27">
<attrib name="value" value="128"/></item>
<item name="D4" rev="27">
<attrib name="value" value="138"/></item>
<item name="D5" rev="27">
<attrib name="value" value="140"/></item>
<item name="D6" rev="27">
<attrib name="value" value="145"/></item>
<item name="DMUX" rev="27">
<attrib name="value" value="39"/></item>
<item name="DQ" rev="27">
<attrib name="value" value="123"/></item>
<item name="DX" rev="27">
<attrib name="value" value="60"/></item>
<item name="SR" rev="21">
<attrib name="value" value="143"/></item>
<item name="SR" rev="27">
<attrib name="value" value="134"/></item>
</group>
<group name="BUFG_BUFG">
<item name="I0" rev="21">
<item name="I0" rev="27">
<attrib name="value" value="4"/></item>
<item name="O" rev="21">
<item name="O" rev="27">
<attrib name="value" value="4"/></item>
</group>
<group name="PAD">
<item name="PAD" rev="21">
<item name="PAD" rev="27">
<attrib name="value" value="331"/></item>
</group>
<group name="IOB_INBUF">
<item name="DIFFI_IN" rev="21">
<item name="DIFFI_IN" rev="27">
<attrib name="value" value="1"/></item>
<item name="OUT" rev="21">
<item name="OUT" rev="27">
<attrib name="value" value="160"/></item>
<item name="PAD" rev="21">
<item name="PAD" rev="27">
<attrib name="value" value="160"/></item>
</group>
<group name="IOBM">
<item name="DIFFO_OUT" rev="21">
<item name="DIFFO_OUT" rev="27">
<attrib name="value" value="2"/></item>
<item name="O" rev="21">
<item name="O" rev="27">
<attrib name="value" value="2"/></item>
<item name="PAD" rev="21">
<item name="PAD" rev="27">
<attrib name="value" value="2"/></item>
</group>
<group name="CARRY4">
<item name="CIN" rev="21">
<attrib name="value" value="50"/></item>
<item name="CO1" rev="21">
<item name="CIN" rev="27">
<attrib name="value" value="47"/></item>
<item name="CO1" rev="27">
<attrib name="value" value="2"/></item>
<item name="CO2" rev="21">
<item name="CO2" rev="27">
<attrib name="value" value="1"/></item>
<item name="CO3" rev="21">
<attrib name="value" value="51"/></item>
<item name="CYINIT" rev="21">
<item name="CO3" rev="27">
<attrib name="value" value="48"/></item>
<item name="CYINIT" rev="27">
<attrib name="value" value="13"/></item>
<item name="DI0" rev="21">
<attrib name="value" value="62"/></item>
<item name="DI1" rev="21">
<attrib name="value" value="58"/></item>
<item name="DI2" rev="21">
<item name="DI0" rev="27">
<attrib name="value" value="59"/></item>
<item name="DI1" rev="27">
<attrib name="value" value="58"/></item>
<item name="DI3" rev="21">
<item name="DI2" rev="27">
<attrib name="value" value="55"/></item>
<item name="DI3" rev="27">
<attrib name="value" value="48"/></item>
<item name="O0" rev="27">
<attrib name="value" value="56"/></item>
<item name="O1" rev="27">
<attrib name="value" value="55"/></item>
<item name="O2" rev="27">
<attrib name="value" value="54"/></item>
<item name="O3" rev="27">
<attrib name="value" value="51"/></item>
<item name="O0" rev="21">
<item name="S0" rev="27">
<attrib name="value" value="60"/></item>
<item name="S1" rev="27">
<attrib name="value" value="59"/></item>
<item name="O1" rev="21">
<item name="S2" rev="27">
<attrib name="value" value="58"/></item>
<item name="O2" rev="21">
<attrib name="value" value="54"/></item>
<item name="O3" rev="21">
<item name="S3" rev="27">
<attrib name="value" value="54"/></item>
<item name="S0" rev="21">
<attrib name="value" value="63"/></item>
<item name="S1" rev="21">
<attrib name="value" value="62"/></item>
<item name="S2" rev="21">
<attrib name="value" value="58"/></item>
<item name="S3" rev="21">
<attrib name="value" value="57"/></item>
</group>
<group name="IOBS">
<item name="DIFFO_IN" rev="21">
<item name="DIFFO_IN" rev="27">
<attrib name="value" value="2"/></item>
<item name="PAD" rev="21">
<item name="PAD" rev="27">
<attrib name="value" value="2"/></item>
</group>
<group name="LUT5">
<item name="A1" rev="21">
<attrib name="value" value="32"/></item>
<item name="A2" rev="21">
<attrib name="value" value="57"/></item>
<item name="A3" rev="21">
<attrib name="value" value="110"/></item>
<item name="A4" rev="21">
<attrib name="value" value="123"/></item>
<item name="A5" rev="21">
<attrib name="value" value="84"/></item>
<item name="O5" rev="21">
<attrib name="value" value="384"/></item>
<item name="A1" rev="27">
<attrib name="value" value="46"/></item>
<item name="A2" rev="27">
<attrib name="value" value="48"/></item>
<item name="A3" rev="27">
<attrib name="value" value="126"/></item>
<item name="A4" rev="27">
<attrib name="value" value="131"/></item>
<item name="A5" rev="27">
<attrib name="value" value="65"/></item>
<item name="O5" rev="27">
<attrib name="value" value="369"/></item>
</group>
<group name="LUT6">
<item name="A1" rev="21">
<attrib name="value" value="308"/></item>
<item name="A2" rev="21">
<attrib name="value" value="461"/></item>
<item name="A3" rev="21">
<attrib name="value" value="581"/></item>
<item name="A4" rev="21">
<attrib name="value" value="887"/></item>
<item name="A5" rev="21">
<attrib name="value" value="763"/></item>
<item name="A6" rev="21">
<attrib name="value" value="947"/></item>
<item name="O6" rev="21">
<attrib name="value" value="961"/></item>
<item name="A1" rev="27">
<attrib name="value" value="302"/></item>
<item name="A2" rev="27">
<attrib name="value" value="472"/></item>
<item name="A3" rev="27">
<attrib name="value" value="572"/></item>
<item name="A4" rev="27">
<attrib name="value" value="870"/></item>
<item name="A5" rev="27">
<attrib name="value" value="755"/></item>
<item name="A6" rev="27">
<attrib name="value" value="930"/></item>
<item name="O6" rev="27">
<attrib name="value" value="944"/></item>
</group>
<group name="SELMUX2_1">
<item name="0" rev="21">
<item name="0" rev="27">
<attrib name="value" value="28"/></item>
<item name="1" rev="21">
<item name="1" rev="27">
<attrib name="value" value="28"/></item>
<item name="OUT" rev="21">
<item name="OUT" rev="27">
<attrib name="value" value="28"/></item>
<item name="S0" rev="21">
<item name="S0" rev="27">
<attrib name="value" value="28"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="21">
<item name="I" rev="27">
<attrib name="value" value="160"/></item>
<item name="OUT" rev="21">
<item name="OUT" rev="27">
<attrib name="value" value="160"/></item>
</group>
<group name="IOB">
<item name="DIFFI_IN" rev="21">
<item name="DIFFI_IN" rev="27">
<attrib name="value" value="1"/></item>
<item name="I" rev="21">
<item name="I" rev="27">
<attrib name="value" value="160"/></item>
<item name="O" rev="21">
<item name="O" rev="27">
<attrib name="value" value="198"/></item>
<item name="PAD" rev="21">
<item name="PAD" rev="27">
<attrib name="value" value="327"/></item>
<item name="PADOUT" rev="21">
<item name="PADOUT" rev="27">
<attrib name="value" value="1"/></item>
<item name="T" rev="21">
<item name="T" rev="27">
<attrib name="value" value="44"/></item>
</group>
<group name="HARD0">
<item name="0" rev="21">
<item name="0" rev="27">
<attrib name="value" value="12"/></item>
</group>
<group name="FF_SR">
<item name="CE" rev="21">
<attrib name="value" value="44"/></item>
<item name="CK" rev="21">
<attrib name="value" value="85"/></item>
<item name="D" rev="21">
<attrib name="value" value="85"/></item>
<item name="Q" rev="21">
<attrib name="value" value="85"/></item>
<item name="SR" rev="21">
<attrib name="value" value="32"/></item>
<item name="CE" rev="27">
<attrib name="value" value="36"/></item>
<item name="CK" rev="27">
<attrib name="value" value="73"/></item>
<item name="D" rev="27">
<attrib name="value" value="73"/></item>
<item name="Q" rev="27">
<attrib name="value" value="73"/></item>
<item name="SR" rev="27">
<attrib name="value" value="28"/></item>
</group>
<group name="BUFG">
<item name="I0" rev="21">
<item name="I0" rev="27">
<attrib name="value" value="4"/></item>
<item name="O" rev="21">
<item name="O" rev="27">
<attrib name="value" value="4"/></item>
</group>
</ReportPinData>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt
View file @ 12b83ada
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Mon Dec 20 13:46:35 2010">
<application stringID="Xst" timeStamp="Mon Dec 20 17:22:46 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -175,8 +175,8 @@
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="837">
<item dataType="int" stringID="XST_FLIPFLOPS" value="837"/>
<item dataType="int" stringID="XST_REGISTERS" value="828">
<item dataType="int" stringID="XST_FLIPFLOPS" value="828"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="6">
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="2"/>
......@@ -193,26 +193,26 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SFpga.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="1582">
<item dataType="int" stringID="XST_BELS" value="1555">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="32"/>
<item dataType="int" stringID="XST_LUT1" value="206"/>
<item dataType="int" stringID="XST_LUT1" value="197"/>
<item dataType="int" stringID="XST_LUT2" value="168"/>
<item dataType="int" stringID="XST_LUT3" value="130"/>
<item dataType="int" stringID="XST_LUT4" value="113"/>
<item dataType="int" stringID="XST_LUT5" value="145"/>
<item dataType="int" stringID="XST_LUT6" value="304"/>
<item dataType="int" stringID="XST_MUXCY" value="229"/>
<item dataType="int" stringID="XST_LUT4" value="116"/>
<item dataType="int" stringID="XST_LUT5" value="148"/>
<item dataType="int" stringID="XST_LUT6" value="298"/>
<item dataType="int" stringID="XST_MUXCY" value="220"/>
<item dataType="int" stringID="XST_MUXF7" value="28"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="225"/>
<item dataType="int" stringID="XST_XORCY" value="216"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="843">
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="834">
<item dataType="int" stringID="XST_FD" value="195"/>
<item dataType="int" stringID="XST_FDE" value="102"/>
<item dataType="int" stringID="XST_FDPE" value="1"/>
<item dataType="int" stringID="XST_FDR" value="135"/>
<item dataType="int" stringID="XST_FDRE" value="351"/>
<item dataType="int" stringID="XST_FDRE" value="342"/>
<item dataType="int" stringID="XST_FDS" value="26"/>
<item dataType="int" stringID="XST_FDSE" value="33"/>
</item>
......@@ -223,11 +223,11 @@
<item dataType="int" stringID="XST_SRLC16E" value="6"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="4">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
<item dataType="int" stringID="XST_BUFGP" value="3"/>
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="2"/>
<item dataType="int" stringID="XST_BUFGP" value="2"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="302">
<item dataType="int" stringID="XST_IBUF" value="75"/>
<item dataType="int" stringID="XST_IO_BUFFERS" value="303">
<item dataType="int" stringID="XST_IBUF" value="76"/>
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/>
<item dataType="int" stringID="XST_OBUF" value="152"/>
<item dataType="int" stringID="XST_OBUFT" value="32"/>
......@@ -236,15 +236,15 @@
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx150tfgg676-3"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="843"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="1112"/>
<item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="1098"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="834"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="1103"/>
<item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="1089"/>
<item AVAILABLE="21680" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="14"/>
<item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="6"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1328"/>
<item AVAILABLE="1328" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="485"/>
<item AVAILABLE="1328" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="216"/>
<item AVAILABLE="1328" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="627"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1319"/>
<item AVAILABLE="1319" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="485"/>
<item AVAILABLE="1319" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="216"/>
<item AVAILABLE="1319" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="618"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="34"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="365"/>
<item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="316"/>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise
View file @ 12b83ada
......@@ -110,11 +110,10 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292849214" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292849194">
<transform xil_pn:end_ts="1292862183" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292862165">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SFpga.lso"/>
......@@ -129,26 +128,24 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1292576389" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1292576389">
<transform xil_pn:end_ts="1292862908" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1292862908">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292849218" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292849214">
<transform xil_pn:end_ts="1292862913" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292862908">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="SFpga.bld"/>
<outfile xil_pn:name="SFpga.ngd"/>
<outfile xil_pn:name="SFpga_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292849269" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292849218">
<transform xil_pn:end_ts="1292862953" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292862913">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SFpga.pcf"/>
......@@ -161,11 +158,10 @@
<outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292849315" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292849269">
<transform xil_pn:end_ts="1292863002" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292862953">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="SFpga.ncd"/>
<outfile xil_pn:name="SFpga.pad"/>
<outfile xil_pn:name="SFpga.par"/>
......@@ -177,11 +173,10 @@
<outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292849348" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292849315">
<transform xil_pn:end_ts="1292863036" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292863002">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="SFpga.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="sfpga.bgn"/>
......@@ -194,38 +189,34 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1292848594" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1292848592">
<transform xil_pn:end_ts="1292864265" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1292864264">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="sfpga.isc"/>
</transform>
<transform xil_pn:end_ts="1292832753" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292832751">
<transform xil_pn:end_ts="1292863315" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292863313">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1292849315" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292849303">
<transform xil_pn:end_ts="1292862605" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1292862604">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1292863002" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292862990">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="SFpga.twr"/>
<outfile xil_pn:name="SFpga.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......@@ -234,7 +225,6 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
......@@ -242,11 +232,10 @@
<outfile xil_pn:name="SFpga_preroute.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292576356" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1292576356">
<transform xil_pn:end_ts="1292862688" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1292862688">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>
......
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ 12b83ada
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292849212
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292862182
OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/bitgen.xmsgs
View file @ 12b83ada
......@@ -8,7 +8,7 @@
<msg type="warning" file="Bitgen" num="244" delta="old" >A StartupClk setting other than JtagClk is being used to generate a bitstream in IEEE1532 format. The IEEE1532 option implies that JTAG configuration will be used. Using a StartupClk setting other than JtagClk could prevent proper device startup.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/WriteCycle</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/WriteCycle</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/map.xmsgs
View file @ 12b83ada
......@@ -143,7 +143,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/WriteCycle</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/WriteCycle</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs
View file @ 12b83ada
......@@ -8,38 +8,5 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/AddrDecoderWBSys.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Debouncer.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4InputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/InterruptManagerWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Monostable.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Slv2SerWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SpiMasterWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/VmeInterfaceWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v\&quot; into library work</arg>
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/xst.xmsgs
View file @ 12b83ada
......@@ -14,10 +14,10 @@
<msg type="warning" file="HDLCompiler" num="572" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro &lt;<arg fmt="%s" index="1">dly</arg>&gt; is redefined.
</msg>
<msg type="warning" file="HDLCompiler" num="224" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 588: Assignment to input <arg fmt="%s" index="1">AFpgaProgDone_io</arg>
<msg type="warning" file="HDLCompiler" num="224" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to input <arg fmt="%s" index="1">AFpgaProgDone_io</arg>
</msg>
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 487: Port <arg fmt="%s" index="1">osc_clk</arg> is not connected to this instance
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 507: Port <arg fmt="%s" index="1">osc_clk</arg> is not connected to this instance
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 325: Assignment to <arg fmt="%s" index="1">DdrLDQS_io</arg> ignored, since the identifier is never used
......@@ -26,10 +26,10 @@
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 326: Assignment to <arg fmt="%s" index="1">DdrUDQS_io</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 548: Assignment to <arg fmt="%s" index="1">GenericOutputReg3</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 568: Assignment to <arg fmt="%s" index="1">GenericOutputReg3</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 588: Assignment to <arg fmt="%s" index="1">AFpgaProgDone_io</arg> ignored, since the identifier is never used
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 608: Assignment to <arg fmt="%s" index="1">AFpgaProgDone_io</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net &lt;<arg fmt="%s" index="1">GenericInputReg1[31]</arg>&gt; does not have a driver.
......@@ -278,10 +278,10 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">487</arg>: Output port &lt;<arg fmt="%s" index="3">osc_clk</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_InterruptManager</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">507</arg>: Output port &lt;<arg fmt="%s" index="3">osc_clk</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_InterruptManager</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">535</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Generic4OutputRegs</arg>&gt; is unconnected or connected to loadless signal.
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">555</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Generic4OutputRegs</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">GenericInputReg1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport
View file @ 12b83ada
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2010-12-20T15:32:38</DateModified>
<DateModified>2010-12-20T16:40:12</DateModified>
<ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-20T13:49:08</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html
View file @ 12b83ada
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1539</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4834</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4834</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4369</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>14.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>20.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>29.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>29.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>15.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>6.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>9.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>6.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1527</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4741</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4741</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4348</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>15.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>21.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>27.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>30.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>30.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>14.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>9.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>6.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>12.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>13.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>15.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>8.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.1013</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0653</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
trunk/firmware/XilinxISE/SystemFpga/planAhead.ngc2edif.log
View file @ 12b83ada
......@@ -130,3 +130,14 @@ Processing design ...
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 75544 kilobytes
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn
View file @ 12b83ada
......@@ -5,7 +5,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf.
Mon Dec 20 13:48:40 2010
Mon Dec 20 17:36:48 2010
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc
View file @ 12b83ada
Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 13:48:40 2010
Mon Dec 20 17:36:48 2010
drc -z SFpga.ncd SFpga.pcf
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.isc
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/sfpga.rbt
View file @ 12b83ada
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html
View file @ 12b83ada
......@@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">9</xtag-property></TD>
<TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">12</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD>
</TR>
......@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2010-12-20T13:49:03</xtag-property></TD>
<TD><xtag-property name="Date Generated">2010-12-20T17:37:11</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
......@@ -87,8 +87,8 @@
<xtag-group><xtag-group-name name="Counters=11">Counters=11</xtag-group-name>
<UL>
<LI><xtag-item1>16-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>23-bit up counter=3</xtag-item1></LI>
<LI><xtag-item1>24-bit up counter=3</xtag-item1></LI>
<LI><xtag-item1>26-bit up counter=3</xtag-item1></LI>
<LI><xtag-item1>3-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>4-bit updown counter=1</xtag-item1></LI>
<LI><xtag-item1>9-bit up counter=1</xtag-item1></LI>
......@@ -136,82 +136,82 @@
<LI><xtag-item1>AGG_BONDED_IO=331</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=331</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=329</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=395</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=383</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=327</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=606</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=387</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=159</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1152</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=596</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=369</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=172</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1137</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=325</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=160</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=196</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=595</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=168</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=187</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=579</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=10</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=18</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=18</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=10</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=10</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=196</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=91</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=187</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=88</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=300</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=63</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=291</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=60</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=34</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1375</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1343</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_F7MUX=28</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=843</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=139</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=834</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=142</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=6</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=91</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=76</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=1920</xtag-item1></LI>
<LI><xtag-item1>NumNets_Active=1908</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=36</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=238</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=25</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=200</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=17</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=256</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=23</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=320</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2039</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=241</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=26</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=287</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2086</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=354</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=150</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=63</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=181</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=60</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=243</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=243</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3771</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1596</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1469</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3723</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1593</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1471</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=137</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=114</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=874</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4346</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5321</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=287</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2269</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=839</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4266</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5699</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=293</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2377</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=143</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=390</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=386</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=403</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=399</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=11</xtag-item1></LI>
</UL>
</xtag-group>
......@@ -220,9 +220,9 @@
<LI><xtag-item1>BUFG-BUFGMUX=4</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=162</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=47</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=71</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=63</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=33</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=61</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=75</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
......@@ -233,8 +233,8 @@
<UL>
<LI><xtag-item2>BUFG=4</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=4</xtag-item2></LI>
<LI><xtag-item2>CARRY4=63</xtag-item2></LI>
<LI><xtag-item2>FF_SR=85</xtag-item2></LI>
<LI><xtag-item2>CARRY4=60</xtag-item2></LI>
<LI><xtag-item2>FF_SR=73</xtag-item2></LI>
<LI><xtag-item2>HARD0=12</xtag-item2></LI>
<LI><xtag-item2>IOB=327</xtag-item2></LI>
<LI><xtag-item2>IOBM=2</xtag-item2></LI>
......@@ -243,17 +243,17 @@
<LI><xtag-item2>IOB_IMUX=160</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=160</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI>
<LI><xtag-item2>LUT5=384</xtag-item2></LI>
<LI><xtag-item2>LUT6=961</xtag-item2></LI>
<LI><xtag-item2>LUT5=369</xtag-item2></LI>
<LI><xtag-item2>LUT6=944</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM5=4</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM6=14</xtag-item2></LI>
<LI><xtag-item2>NULLMUX=3</xtag-item2></LI>
<LI><xtag-item2>PAD=331</xtag-item2></LI>
<LI><xtag-item2>REG_SR=758</xtag-item2></LI>
<LI><xtag-item2>REG_SR=761</xtag-item2></LI>
<LI><xtag-item2>SELMUX2_1=28</xtag-item2></LI>
<LI><xtag-item2>SLICEL=91</xtag-item2></LI>
<LI><xtag-item2>SLICEL=88</xtag-item2></LI>
<LI><xtag-item2>SLICEM=4</xtag-item2></LI>
<LI><xtag-item2>SLICEX=300</xtag-item2></LI>
<LI><xtag-item2>SLICEX=291</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
......@@ -265,9 +265,9 @@
<TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:85] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:74] [SRINIT1:11]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:53] [SYNC:32]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:73] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:62] [SRINIT1:11]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:45] [SYNC:28]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name>
......@@ -307,17 +307,17 @@
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:758] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:758]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:706] [SRINIT1:52]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:245] [SYNC:513]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:761] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:761]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:709] [SRINIT1:52]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:253] [SYNC:508]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:54] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:47] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
......@@ -327,7 +327,7 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:198] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:190] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
......@@ -351,32 +351,32 @@
</xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL>
<LI><xtag-item1>CIN=50</xtag-item1></LI>
<LI><xtag-item1>CIN=47</xtag-item1></LI>
<LI><xtag-item1>CO1=2</xtag-item1></LI>
<LI><xtag-item1>CO2=1</xtag-item1></LI>
<LI><xtag-item1>CO3=51</xtag-item1></LI>
<LI><xtag-item1>CO3=48</xtag-item1></LI>
<LI><xtag-item1>CYINIT=13</xtag-item1></LI>
<LI><xtag-item1>DI0=62</xtag-item1></LI>
<LI><xtag-item1>DI0=59</xtag-item1></LI>
<LI><xtag-item1>DI1=58</xtag-item1></LI>
<LI><xtag-item1>DI2=58</xtag-item1></LI>
<LI><xtag-item1>DI3=51</xtag-item1></LI>
<LI><xtag-item1>O0=59</xtag-item1></LI>
<LI><xtag-item1>O1=58</xtag-item1></LI>
<LI><xtag-item1>DI2=55</xtag-item1></LI>
<LI><xtag-item1>DI3=48</xtag-item1></LI>
<LI><xtag-item1>O0=56</xtag-item1></LI>
<LI><xtag-item1>O1=55</xtag-item1></LI>
<LI><xtag-item1>O2=54</xtag-item1></LI>
<LI><xtag-item1>O3=54</xtag-item1></LI>
<LI><xtag-item1>S0=63</xtag-item1></LI>
<LI><xtag-item1>S1=62</xtag-item1></LI>
<LI><xtag-item1>O3=51</xtag-item1></LI>
<LI><xtag-item1>S0=60</xtag-item1></LI>
<LI><xtag-item1>S1=59</xtag-item1></LI>
<LI><xtag-item1>S2=58</xtag-item1></LI>
<LI><xtag-item1>S3=57</xtag-item1></LI>
<LI><xtag-item1>S3=54</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=44</xtag-item1></LI>
<LI><xtag-item1>CK=85</xtag-item1></LI>
<LI><xtag-item1>D=85</xtag-item1></LI>
<LI><xtag-item1>Q=85</xtag-item1></LI>
<LI><xtag-item1>SR=32</xtag-item1></LI>
<LI><xtag-item1>CE=36</xtag-item1></LI>
<LI><xtag-item1>CK=73</xtag-item1></LI>
<LI><xtag-item1>D=73</xtag-item1></LI>
<LI><xtag-item1>Q=73</xtag-item1></LI>
<LI><xtag-item1>SR=28</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
......@@ -436,23 +436,23 @@
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A1=32</xtag-item1></LI>
<LI><xtag-item1>A2=57</xtag-item1></LI>
<LI><xtag-item1>A3=110</xtag-item1></LI>
<LI><xtag-item1>A4=123</xtag-item1></LI>
<LI><xtag-item1>A5=84</xtag-item1></LI>
<LI><xtag-item1>O5=384</xtag-item1></LI>
<LI><xtag-item1>A1=46</xtag-item1></LI>
<LI><xtag-item1>A2=48</xtag-item1></LI>
<LI><xtag-item1>A3=126</xtag-item1></LI>
<LI><xtag-item1>A4=131</xtag-item1></LI>
<LI><xtag-item1>A5=65</xtag-item1></LI>
<LI><xtag-item1>O5=369</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=308</xtag-item1></LI>
<LI><xtag-item1>A2=461</xtag-item1></LI>
<LI><xtag-item1>A3=581</xtag-item1></LI>
<LI><xtag-item1>A4=887</xtag-item1></LI>
<LI><xtag-item1>A5=763</xtag-item1></LI>
<LI><xtag-item1>A6=947</xtag-item1></LI>
<LI><xtag-item1>O6=961</xtag-item1></LI>
<LI><xtag-item1>A1=302</xtag-item1></LI>
<LI><xtag-item1>A2=472</xtag-item1></LI>
<LI><xtag-item1>A3=572</xtag-item1></LI>
<LI><xtag-item1>A4=870</xtag-item1></LI>
<LI><xtag-item1>A5=755</xtag-item1></LI>
<LI><xtag-item1>A6=930</xtag-item1></LI>
<LI><xtag-item1>O6=944</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -509,11 +509,11 @@
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=435</xtag-item1></LI>
<LI><xtag-item1>CK=758</xtag-item1></LI>
<LI><xtag-item1>D=758</xtag-item1></LI>
<LI><xtag-item1>Q=758</xtag-item1></LI>
<LI><xtag-item1>SR=514</xtag-item1></LI>
<LI><xtag-item1>CE=434</xtag-item1></LI>
<LI><xtag-item1>CK=761</xtag-item1></LI>
<LI><xtag-item1>D=761</xtag-item1></LI>
<LI><xtag-item1>Q=761</xtag-item1></LI>
<LI><xtag-item1>SR=509</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name>
......@@ -527,48 +527,48 @@
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A=13</xtag-item1></LI>
<LI><xtag-item1>A1=9</xtag-item1></LI>
<LI><xtag-item1>A2=17</xtag-item1></LI>
<LI><xtag-item1>A1=11</xtag-item1></LI>
<LI><xtag-item1>A2=15</xtag-item1></LI>
<LI><xtag-item1>A3=19</xtag-item1></LI>
<LI><xtag-item1>A4=64</xtag-item1></LI>
<LI><xtag-item1>A4=61</xtag-item1></LI>
<LI><xtag-item1>A5=33</xtag-item1></LI>
<LI><xtag-item1>A6=77</xtag-item1></LI>
<LI><xtag-item1>AMUX=17</xtag-item1></LI>
<LI><xtag-item1>AQ=52</xtag-item1></LI>
<LI><xtag-item1>AX=13</xtag-item1></LI>
<LI><xtag-item1>A6=74</xtag-item1></LI>
<LI><xtag-item1>AMUX=19</xtag-item1></LI>
<LI><xtag-item1>AQ=47</xtag-item1></LI>
<LI><xtag-item1>AX=9</xtag-item1></LI>
<LI><xtag-item1>B=11</xtag-item1></LI>
<LI><xtag-item1>B1=11</xtag-item1></LI>
<LI><xtag-item1>B2=13</xtag-item1></LI>
<LI><xtag-item1>B3=15</xtag-item1></LI>
<LI><xtag-item1>B4=61</xtag-item1></LI>
<LI><xtag-item1>B1=10</xtag-item1></LI>
<LI><xtag-item1>B2=12</xtag-item1></LI>
<LI><xtag-item1>B3=14</xtag-item1></LI>
<LI><xtag-item1>B4=58</xtag-item1></LI>
<LI><xtag-item1>B5=30</xtag-item1></LI>
<LI><xtag-item1>B6=71</xtag-item1></LI>
<LI><xtag-item1>BMUX=18</xtag-item1></LI>
<LI><xtag-item1>BQ=51</xtag-item1></LI>
<LI><xtag-item1>BX=9</xtag-item1></LI>
<LI><xtag-item1>C1=8</xtag-item1></LI>
<LI><xtag-item1>C2=10</xtag-item1></LI>
<LI><xtag-item1>BQ=46</xtag-item1></LI>
<LI><xtag-item1>BX=7</xtag-item1></LI>
<LI><xtag-item1>C1=6</xtag-item1></LI>
<LI><xtag-item1>C2=8</xtag-item1></LI>
<LI><xtag-item1>C3=20</xtag-item1></LI>
<LI><xtag-item1>C4=71</xtag-item1></LI>
<LI><xtag-item1>C5=45</xtag-item1></LI>
<LI><xtag-item1>C6=85</xtag-item1></LI>
<LI><xtag-item1>CE=30</xtag-item1></LI>
<LI><xtag-item1>CIN=50</xtag-item1></LI>
<LI><xtag-item1>CLK=54</xtag-item1></LI>
<LI><xtag-item1>C6=82</xtag-item1></LI>
<LI><xtag-item1>CE=22</xtag-item1></LI>
<LI><xtag-item1>CIN=47</xtag-item1></LI>
<LI><xtag-item1>CLK=47</xtag-item1></LI>
<LI><xtag-item1>CMUX=42</xtag-item1></LI>
<LI><xtag-item1>COUT=50</xtag-item1></LI>
<LI><xtag-item1>CQ=49</xtag-item1></LI>
<LI><xtag-item1>COUT=47</xtag-item1></LI>
<LI><xtag-item1>CQ=47</xtag-item1></LI>
<LI><xtag-item1>CX=31</xtag-item1></LI>
<LI><xtag-item1>D1=7</xtag-item1></LI>
<LI><xtag-item1>D2=31</xtag-item1></LI>
<LI><xtag-item1>D3=34</xtag-item1></LI>
<LI><xtag-item1>D4=74</xtag-item1></LI>
<LI><xtag-item1>D5=44</xtag-item1></LI>
<LI><xtag-item1>D6=82</xtag-item1></LI>
<LI><xtag-item1>D3=33</xtag-item1></LI>
<LI><xtag-item1>D4=70</xtag-item1></LI>
<LI><xtag-item1>D5=43</xtag-item1></LI>
<LI><xtag-item1>D6=78</xtag-item1></LI>
<LI><xtag-item1>DMUX=15</xtag-item1></LI>
<LI><xtag-item1>DQ=48</xtag-item1></LI>
<LI><xtag-item1>DX=9</xtag-item1></LI>
<LI><xtag-item1>SR=36</xtag-item1></LI>
<LI><xtag-item1>DQ=42</xtag-item1></LI>
<LI><xtag-item1>DX=7</xtag-item1></LI>
<LI><xtag-item1>SR=28</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -624,49 +624,49 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=109</xtag-item1></LI>
<LI><xtag-item1>A1=95</xtag-item1></LI>
<LI><xtag-item1>A2=133</xtag-item1></LI>
<LI><xtag-item1>A3=175</xtag-item1></LI>
<LI><xtag-item1>A4=193</xtag-item1></LI>
<LI><xtag-item1>A5=192</xtag-item1></LI>
<LI><xtag-item1>A6=199</xtag-item1></LI>
<LI><xtag-item1>A=114</xtag-item1></LI>
<LI><xtag-item1>A1=101</xtag-item1></LI>
<LI><xtag-item1>A2=143</xtag-item1></LI>
<LI><xtag-item1>A3=182</xtag-item1></LI>
<LI><xtag-item1>A4=200</xtag-item1></LI>
<LI><xtag-item1>A5=197</xtag-item1></LI>
<LI><xtag-item1>A6=205</xtag-item1></LI>
<LI><xtag-item1>AMUX=44</xtag-item1></LI>
<LI><xtag-item1>AQ=161</xtag-item1></LI>
<LI><xtag-item1>AX=57</xtag-item1></LI>
<LI><xtag-item1>B=77</xtag-item1></LI>
<LI><xtag-item1>B1=73</xtag-item1></LI>
<LI><xtag-item1>B2=103</xtag-item1></LI>
<LI><xtag-item1>B3=136</xtag-item1></LI>
<LI><xtag-item1>B4=144</xtag-item1></LI>
<LI><xtag-item1>B5=150</xtag-item1></LI>
<LI><xtag-item1>B6=145</xtag-item1></LI>
<LI><xtag-item1>BMUX=37</xtag-item1></LI>
<LI><xtag-item1>BQ=128</xtag-item1></LI>
<LI><xtag-item1>BX=59</xtag-item1></LI>
<LI><xtag-item1>AQ=169</xtag-item1></LI>
<LI><xtag-item1>AX=65</xtag-item1></LI>
<LI><xtag-item1>B=72</xtag-item1></LI>
<LI><xtag-item1>B1=64</xtag-item1></LI>
<LI><xtag-item1>B2=99</xtag-item1></LI>
<LI><xtag-item1>B3=129</xtag-item1></LI>
<LI><xtag-item1>B4=140</xtag-item1></LI>
<LI><xtag-item1>B5=142</xtag-item1></LI>
<LI><xtag-item1>B6=142</xtag-item1></LI>
<LI><xtag-item1>BMUX=35</xtag-item1></LI>
<LI><xtag-item1>BQ=135</xtag-item1></LI>
<LI><xtag-item1>BX=61</xtag-item1></LI>
<LI><xtag-item1>C=52</xtag-item1></LI>
<LI><xtag-item1>C1=70</xtag-item1></LI>
<LI><xtag-item1>C2=88</xtag-item1></LI>
<LI><xtag-item1>C3=119</xtag-item1></LI>
<LI><xtag-item1>C4=130</xtag-item1></LI>
<LI><xtag-item1>C5=135</xtag-item1></LI>
<LI><xtag-item1>C6=131</xtag-item1></LI>
<LI><xtag-item1>CE=109</xtag-item1></LI>
<LI><xtag-item1>CLK=198</xtag-item1></LI>
<LI><xtag-item1>C1=78</xtag-item1></LI>
<LI><xtag-item1>C2=98</xtag-item1></LI>
<LI><xtag-item1>C3=123</xtag-item1></LI>
<LI><xtag-item1>C4=132</xtag-item1></LI>
<LI><xtag-item1>C5=134</xtag-item1></LI>
<LI><xtag-item1>C6=133</xtag-item1></LI>
<LI><xtag-item1>CE=101</xtag-item1></LI>
<LI><xtag-item1>CLK=190</xtag-item1></LI>
<LI><xtag-item1>CMUX=33</xtag-item1></LI>
<LI><xtag-item1>CQ=137</xtag-item1></LI>
<LI><xtag-item1>CX=54</xtag-item1></LI>
<LI><xtag-item1>D=94</xtag-item1></LI>
<LI><xtag-item1>D1=64</xtag-item1></LI>
<LI><xtag-item1>D2=107</xtag-item1></LI>
<LI><xtag-item1>D3=139</xtag-item1></LI>
<LI><xtag-item1>D4=150</xtag-item1></LI>
<LI><xtag-item1>D5=154</xtag-item1></LI>
<LI><xtag-item1>D6=157</xtag-item1></LI>
<LI><xtag-item1>DMUX=43</xtag-item1></LI>
<LI><xtag-item1>DQ=126</xtag-item1></LI>
<LI><xtag-item1>CQ=146</xtag-item1></LI>
<LI><xtag-item1>CX=58</xtag-item1></LI>
<LI><xtag-item1>D=86</xtag-item1></LI>
<LI><xtag-item1>D1=68</xtag-item1></LI>
<LI><xtag-item1>D2=98</xtag-item1></LI>
<LI><xtag-item1>D3=128</xtag-item1></LI>
<LI><xtag-item1>D4=138</xtag-item1></LI>
<LI><xtag-item1>D5=140</xtag-item1></LI>
<LI><xtag-item1>D6=145</xtag-item1></LI>
<LI><xtag-item1>DMUX=39</xtag-item1></LI>
<LI><xtag-item1>DQ=123</xtag-item1></LI>
<LI><xtag-item1>DX=60</xtag-item1></LI>
<LI><xtag-item1>SR=143</xtag-item1></LI>
<LI><xtag-item1>SR=134</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -772,13 +772,30 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>8</xtag-total-run-started></td>
<td><xtag-total-run-finished>6</xtag-total-run-finished></td>
<td><xtag-total-run-started>12</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -787,8 +804,8 @@
</tr>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>4</xtag-total-run-started></td>
<td><xtag-total-run-finished>4</xtag-total-run-finished></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -797,8 +814,18 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>4</xtag-total-run-started></td>
<td><xtag-total-run-finished>4</xtag-total-run-finished></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngc2edif</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -807,8 +834,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>4</xtag-total-run-started></td>
<td><xtag-total-run-finished>4</xtag-total-run-finished></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -817,8 +844,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>4</xtag-total-run-started></td>
<td><xtag-total-run-finished>4</xtag-total-run-finished></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -827,8 +854,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>4</xtag-total-run-started></td>
<td><xtag-total-run-finished>4</xtag-total-run-finished></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -837,8 +864,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>4</xtag-total-run-started></td>
<td><xtag-total-run-finished>4</xtag-total-run-finished></td>
<td><xtag-total-run-started>10</xtag-total-run-started></td>
<td><xtag-total-run-finished>10</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -870,7 +897,7 @@
<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>9</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>12</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
......@@ -900,38 +927,38 @@
<xtag-section name="UnisimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>195</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>102</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDPE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>135</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>351</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>342</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>26</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDSE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>33</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>75</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>76</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUFDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>206</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>197</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>168</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>130</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>113</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>145</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>116</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>148</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>304</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>229</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>298</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>220</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>152</xtag-preunisim-param-value></TD>
</TR>
......@@ -944,7 +971,7 @@
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>225</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>216</xtag-preunisim-param-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>195</xtag-postunisim-param-value></TD>
......@@ -953,30 +980,30 @@
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>135</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>351</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>342</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>26</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDSE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>33</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>156</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>157</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>32</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>206</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>197</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>168</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>130</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>113</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>145</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>304</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>116</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>148</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>298</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>229</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>220</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>152</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
......@@ -990,6 +1017,6 @@
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_TS_TIMESPEC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>225</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>216</xtag-postunisim-param-value></TD>
</xtag-section></TABLE>
&nbsp;<BR></BODY></HTML>
trunk/firmware/XilinxISE/SystemFpga/webtalk.log
View file @ 12b83ada
......@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=9
ProjectIteration=12
WebTalk Summary
----------------
......@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-20T13:49:08. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-20T17:37:16. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml
View file @ 12b83ada
......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Mon Dec 20 13:48:35 2010">
<application name="pn" timeStamp="Mon Dec 20 17:36:42 2010">
<section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="9" type="project"/>
<property name="ProjectIteration" value="12" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section>
......@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="9" type="process"/>
<property name="PROP_intWbtProjectIteration" value="12" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
trunk/hdl/design/Generic4OutputRegs.v
View file @ 12b83ada
......@@ -17,16 +17,7 @@ module Generic4OutputRegs
output reg [31:0] Reg0Value_ob32,
output reg [31:0] Reg1Value_ob32,
output reg [31:0] Reg2Value_ob32,
output reg [31:0] Reg3Value_ob32,
output reg Writing_o,
output reg WritingReg3_o,
output reg WritingABC_o);
always @(posedge Clk_ik) begin
Writing_o <= (Cyc_i && We_i && Stb_i);
WritingABC_o <= (Cyc_i && We_i && Stb_i)&& Dat_ib32==32'h0000_0abc;
end
output reg [31:0] Reg3Value_ob32);
always @(posedge Clk_ik)
if (Rst_irq) Reg0Value_ob32 <= #1 Reg0Default;
......@@ -40,14 +31,9 @@ always @(posedge Clk_ik)
if (Rst_irq) Reg2Value_ob32 <= #1 Reg2Default;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b10) Reg2Value_ob32 <= Dat_ib32;
always @(posedge Clk_ik) begin
WritingReg3_o <= 1'b0;
always @(posedge Clk_ik)
if (Rst_irq) Reg3Value_ob32 <= #1 Reg3Default;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==(2'b11)) begin
Reg3Value_ob32 <= Dat_ib32;
WritingReg3_o <= 1'b1;
end
end
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b11) Reg3Value_ob32 <= Dat_ib32;
assign Ack_oa = Stb_i&&Cyc_i;
......
trunk/hdl/design/Monostable.v
View file @ 12b83ada
......@@ -3,7 +3,7 @@ module Monostable (
input Clk_ik,
output reg SynchOutput_oq);
parameter g_CounterBits = 26;
parameter g_CounterBits = 23;
reg AsynchIn_ax = 1'b0;
reg [3:0] AsynchInAX_db4 = 2'b0;
......
trunk/hdl/design/SystemFpga.v
View file @ 12b83ada
......@@ -390,6 +390,21 @@ Monostable i_WriteCycleMonostable(
.Clk_ik(Clk_k),
.SynchOutput_oq(WriteCycleLed));
/*Monostable i_Debug1Monostable(
.AsynchIn_ia(Debug1),
.Clk_ik(Clk_k),
.SynchOutput_oq(DebugForLed1));
Monostable i_Debug2Monostable(
.AsynchIn_ia(Debug2),
.Clk_ik(Clk_k),
.SynchOutput_oq(DebugForLed2));
Monostable i_Debug3Monostable(
.AsynchIn_ia(Debug3),
.Clk_ik(Clk_k),
.SynchOutput_oq(DebugForLed3));*/
assign FpLed_onb8[0] = VmeAccessForLed ? 1'b0 : 1'bz;
assign FpLed_onb8[1] = (|VmeIrq_ob7) ? 1'b0 : 1'bz;
assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz;
......@@ -397,6 +412,9 @@ assign FpLed_onb8[3] = RstForLed ? 1'b0 : 1'bz;
assign FpLed_onb8[4] = Si57xDivided ? 1'bz : 1'b0;
assign FpLed_onb8[5] = VcTcXoDivided ? 1'bz : 1'b0;
assign FpLed_onb8[6] = VmeSysClkDivided ? 1'bz : 1'b0;
//assign FpLed_onb8[4] = DebugForLed1 ? 1'b0 : 1'bz;
//assign FpLed_onb8[5] = DebugForLed1 ? 1'b0 : 1'bz;
//assign FpLed_onb8[6] = DebugForLed1 ? 1'b0 : 1'bz;
assign FpLed_onb8[7] = WriteCycleLed ? 1'b0 : 1'bz;
//####################################
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment