Commit 12b83ada authored by Andrea Boccardi's avatar Andrea Boccardi

changed the clock source to the VCTCXO

parent bd941eab
...@@ -41,7 +41,7 @@ NGDBUILD Design Results Summary: ...@@ -41,7 +41,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 14 Number of warnings: 14
Total memory usage is 154956 kilobytes Total memory usage is 155532 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec Total REAL time to NGDBUILD completion: 3 sec
......
...@@ -93,3 +93,20 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -93,3 +93,20 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 13:48:21 2010 Mon Dec 20 17:36:28 2010
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
......
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Mon Dec 20 13:47:47 2010 // Written by: Map M.70d on Mon Dec 20 17:35:51 2010
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
...@@ -334,19 +334,19 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1; ...@@ -334,19 +334,19 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1; COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1; COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1; COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL TIMEGRP VcTcXo_ik = BEL "i_Core/VcTcXoDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL "i_Core/VcTcXoDivider_c_22" BEL "i_Core/VcTcXoDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL "i_Core/VcTcXoDivider_c_20" BEL "i_Core/VcTcXoDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL "i_Core/VcTcXoDivider_c_18" BEL "i_Core/VcTcXoDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL "i_Core/VcTcXoDivider_c_16" BEL "i_Core/VcTcXoDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL "i_Core/VcTcXoDivider_c_14" BEL "i_Core/VcTcXoDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL "i_Core/VcTcXoDivider_c_12" BEL "i_Core/VcTcXoDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL "i_Core/VcTcXoDivider_c_10" BEL "i_Core/VcTcXoDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL "i_Core/VcTcXoDivider_c_8" BEL "i_Core/VcTcXoDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL "i_Core/VcTcXoDivider_c_6" BEL "i_Core/VcTcXoDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL "i_Core/VcTcXoDivider_c_4" BEL "i_Core/VcTcXoDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL "i_Core/VcTcXoDivider_c_2" BEL "i_Core/VcTcXoDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "i_Core/Rst_rq" BEL "i_Core/VcTcXoDivider_c_0" BEL "i_Core/Rst_rq" BEL
"i_Core/i_VmeInterface/state_FSM_FFd2" BEL "i_Core/i_VmeInterface/state_FSM_FFd2" BEL
"i_Core/i_VmeInterface/stb_d" BEL "i_Core/i_VmeInterface/adr_o_21" BEL "i_Core/i_VmeInterface/stb_d" BEL "i_Core/i_VmeInterface/adr_o_21" BEL
"i_Core/i_VmeInterface/adr_o_20" BEL "i_Core/i_VmeInterface/adr_o_19" "i_Core/i_VmeInterface/adr_o_20" BEL "i_Core/i_VmeInterface/adr_o_19"
...@@ -437,9 +437,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -437,9 +437,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL "i_Core/i_VmeInterface/DataReg_2" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL "i_Core/i_VmeInterface/DataReg_1" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL "i_Core/i_VmeInterface/DataReg_0" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_24" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL "i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL "i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL "i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
...@@ -464,9 +461,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -464,9 +461,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL "i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL "i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL "i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_ClearMonostable/Counter_c_25" BEL
"i_Core/i_ClearMonostable/Counter_c_24" BEL
"i_Core/i_ClearMonostable/Counter_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_22" BEL "i_Core/i_ClearMonostable/Counter_c_22" BEL
"i_Core/i_ClearMonostable/Counter_c_21" BEL "i_Core/i_ClearMonostable/Counter_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_20" BEL "i_Core/i_ClearMonostable/Counter_c_20" BEL
...@@ -491,9 +485,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -491,9 +485,6 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL "i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL "i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL "i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_25" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_24" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_23" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_22" BEL "i_Core/i_WriteCycleMonostable/Counter_c_22" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_21" BEL "i_Core/i_WriteCycleMonostable/Counter_c_21" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_20" BEL "i_Core/i_WriteCycleMonostable/Counter_c_20" BEL
...@@ -996,7 +987,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -996,7 +987,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeInterface/AckTimeout_c_2" BEL "i_Core/i_VmeInterface/AckTimeout_c_2" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL "i_Core/i_VmeInterface/AckTimeout_c_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL "i_Core/i_VmeInterface/AckTimeout_c_3" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL "i_Core/i_VmeInterface/AckTimeout_c_0" BEL "VcTcXo_ik_IBUF_BUFG" BEL
"i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL "i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL "i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL "i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
...@@ -1022,6 +1013,45 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -1022,6 +1013,45 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL "i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL "i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD"; "i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP VmeSysClk_ik = BEL "i_Core/VmeSysClkDivider_c_23" BEL
"i_Core/VmeSysClkDivider_c_22" BEL "i_Core/VmeSysClkDivider_c_21" BEL
"i_Core/VmeSysClkDivider_c_20" BEL "i_Core/VmeSysClkDivider_c_19" BEL
"i_Core/VmeSysClkDivider_c_18" BEL "i_Core/VmeSysClkDivider_c_17" BEL
"i_Core/VmeSysClkDivider_c_16" BEL "i_Core/VmeSysClkDivider_c_15" BEL
"i_Core/VmeSysClkDivider_c_14" BEL "i_Core/VmeSysClkDivider_c_13" BEL
"i_Core/VmeSysClkDivider_c_12" BEL "i_Core/VmeSysClkDivider_c_11" BEL
"i_Core/VmeSysClkDivider_c_10" BEL "i_Core/VmeSysClkDivider_c_9" BEL
"i_Core/VmeSysClkDivider_c_8" BEL "i_Core/VmeSysClkDivider_c_7" BEL
"i_Core/VmeSysClkDivider_c_6" BEL "i_Core/VmeSysClkDivider_c_5" BEL
"i_Core/VmeSysClkDivider_c_4" BEL "i_Core/VmeSysClkDivider_c_3" BEL
"i_Core/VmeSysClkDivider_c_2" BEL "i_Core/VmeSysClkDivider_c_1" BEL
"i_Core/VmeSysClkDivider_c_0" BEL "VmeSysClk_ik_BUFGP/BUFG";
TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_30" BEL "i_Core/i_Slv2SerWB/Dat_xb32_29" "i_Core/i_Slv2SerWB/Dat_xb32_30" BEL "i_Core/i_Slv2SerWB/Dat_xb32_29"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_28" BEL BEL "i_Core/i_Slv2SerWB/Dat_xb32_28" BEL
...@@ -1078,7 +1108,10 @@ TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL ...@@ -1078,7 +1108,10 @@ TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_0" BEL "i_Core/i_Slv2SerWB/DatInShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/AckI_d3_2" BEL "i_Core/i_Slv2SerWB/AckI_d3_1" BEL "i_Core/i_Slv2SerWB/AckI_d3_2" BEL "i_Core/i_Slv2SerWB/AckI_d3_1" BEL
"i_Core/i_Slv2SerWB/AckI_d3_0" BEL "SysAppClk_ik_BUFGP/BUFG"; "i_Core/i_Slv2SerWB/AckI_d3_0" BEL "SysAppClk_ik_BUFGP/BUFG";
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%; TS_VcTcXo_ik = PERIOD TIMEGRP "VcTcXo_ik" 25 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%; TS_VmeSysClk_ik = PERIOD TIMEGRP "VmeSysClk_ik" 40 MHz HIGH 50%;
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 100 MHz HIGH 50%;
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 100 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 100 MHz HIGH 50%;
SCHEMATIC END; SCHEMATIC END;
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.224" best="8.109" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.342" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.902" best="3.431" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.392" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.091" best="4.909" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.482" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="7.730" best="2.270" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VmeSysClk_ik = PERIOD TIMEGRP &quot;VmeSysClk_ik&quot; 40 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="22.874" best="2.126" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="22.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VcTcXo_ik = PERIOD TIMEGRP &quot;VcTcXo_ik&quot; 25 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="27.265" best="12.735" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
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...@@ -695,7 +695,14 @@ NET "WRTxFault_i" IOSTANDARD = LVCMOS33; ...@@ -695,7 +695,14 @@ NET "WRTxFault_i" IOSTANDARD = LVCMOS33;
NET "VmeSysClk_ik" CLOCK_DEDICATED_ROUTE = "FALSE"; NET "VmeSysClk_ik" CLOCK_DEDICATED_ROUTE = "FALSE";
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/16 #Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/16
NET "Si57x_ik" TNM_NET = "Si57x_ik"; NET "Si57x_ik" TNM_NET = "Si57x_ik";
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 120 MHz HIGH 50 %;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/17 #Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/17
NET "SysAppClk_ik" TNM_NET = SysAppClk_ik; NET "SysAppClk_ik" TNM_NET = SysAppClk_ik;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50%; #Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/20
NET "VcTcXo_ik" TNM_NET = VcTcXo_ik;
TIMESPEC TS_VcTcXo_ik = PERIOD "VcTcXo_ik" 25 MHz HIGH 50%;
NET "VmeSysClk_ik" TNM_NET = VmeSysClk_ik;
TIMESPEC TS_VmeSysClk_ik = PERIOD "VmeSysClk_ik" 40 MHz HIGH 50%;
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 100 MHz HIGH 50%;
NET "Si57x_ikn" TNM_NET = Si57x_ikn;
TIMESPEC TS_Si57x_ikn = PERIOD "Si57x_ikn" 100 MHz HIGH 50%;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 100 MHz HIGH 50%;
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 13:48:22 2010 Mon Dec 20 17:36:28 2010
All signals are completely routed. All signals are completely routed.
......
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 13:46:59 2010 Mapped Date : Mon Dec 20 17:35:13 2010
Mapping design into LUTs... Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
...@@ -87,20 +87,20 @@ Updating timing models... ...@@ -87,20 +87,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 13 secs Total REAL time at the beginning of Placer: 14 secs
Total CPU time at the beginning of Placer: 13 secs Total CPU time at the beginning of Placer: 13 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:f1e2766b) REAL time: 17 secs Phase 1.1 Initial Placement Analysis (Checksum:b839f44f) REAL time: 18 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:f1e2766b) REAL time: 18 secs Phase 2.7 Design Feasibility Check (Checksum:b839f44f) REAL time: 19 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f1e2766b) REAL time: 18 secs Phase 3.31 Local Placement Optimization (Checksum:b839f44f) REAL time: 19 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
... ...
...@@ -118,42 +118,40 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found ...@@ -118,42 +118,40 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design. that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:e552917b) REAL time: 24 secs (Checksum:9f9006dc) REAL time: 25 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:e552917b) REAL time: 24 secs Phase 5.36 Local Placement Optimization (Checksum:9f9006dc) REAL time: 25 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:e552917b) REAL time: 24 secs Phase 6.30 Global Clock Region Assignment (Checksum:9f9006dc) REAL time: 25 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
... ...
Phase 7.3 Local Placement Optimization (Checksum:c1877a) REAL time: 25 secs Phase 7.3 Local Placement Optimization (Checksum:a3e805b0) REAL time: 26 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:e57e7026) REAL time: 25 secs Phase 8.5 Local Placement Optimization (Checksum:9fbbfedd) REAL time: 26 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
............ .............
....................... .......
....................... Phase 9.8 Global Placement (Checksum:2989ec26) REAL time: 29 secs
.....
Phase 9.8 Global Placement (Checksum:c376d41a) REAL time: 32 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:c376d41a) REAL time: 32 secs Phase 10.5 Local Placement Optimization (Checksum:2989ec26) REAL time: 29 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:12757c2b) REAL time: 42 secs Phase 11.18 Placement Optimization (Checksum:7e859587) REAL time: 31 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:12757c2b) REAL time: 42 secs Phase 12.5 Local Placement Optimization (Checksum:7e859587) REAL time: 31 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:7e9272bf) REAL time: 42 secs Phase 13.34 Placement Validation (Checksum:9557604f) REAL time: 31 secs
Total REAL time to Placer completion: 47 secs Total REAL time to Placer completion: 36 secs
Total CPU time to Placer completion: 47 secs Total CPU time to Placer completion: 35 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_Core/WriteCycle is WARNING:PhysDesignRules:372 - Gated clock. Clock net i_Core/WriteCycle is
...@@ -268,16 +266,16 @@ Design Summary: ...@@ -268,16 +266,16 @@ Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 86 Number of warnings: 86
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 843 out of 184,304 1% Number of Slice Registers: 834 out of 184,304 1%
Number used as Flip Flops: 843 Number used as Flip Flops: 834
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 993 out of 92,152 1% Number of Slice LUTs: 965 out of 92,152 1%
Number used as logic: 951 out of 92,152 1% Number used as logic: 934 out of 92,152 1%
Number using O6 output only: 595 Number using O6 output only: 579
Number using O5 output only: 196 Number using O5 output only: 187
Number using O5 and O6: 160 Number using O5 and O6: 168
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1% Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -289,20 +287,20 @@ Slice Logic Utilization: ...@@ -289,20 +287,20 @@ Slice Logic Utilization:
Number using O6 output only: 6 Number using O6 output only: 6
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 28 Number used exclusively as route-thrus: 17
Number with same-slice register load: 18 Number with same-slice register load: 7
Number with same-slice carry load: 10 Number with same-slice carry load: 10
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 395 out of 23,038 1% Number of occupied Slices: 383 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,152 Number of LUT Flip Flop pairs used: 1,137
Number with an unused Flip Flop: 387 out of 1,152 33% Number with an unused Flip Flop: 369 out of 1,137 32%
Number with an unused LUT: 159 out of 1,152 13% Number with an unused LUT: 172 out of 1,137 15%
Number of fully used LUT-FF pairs: 606 out of 1,152 52% Number of fully used LUT-FF pairs: 596 out of 1,137 52%
Number of unique control sets: 34 Number of unique control sets: 34
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 91 out of 184,304 1% to control set restrictions: 76 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -343,11 +341,11 @@ Specific Feature Utilization: ...@@ -343,11 +341,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02 Average Fanout of Non-Clock Nets: 3.00
Peak Memory Usage: 632 MB Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 49 secs Total REAL time to MAP completion: 38 secs
Total CPU time to MAP completion: 48 secs Total CPU time to MAP completion: 36 secs
Mapping completed. Mapping completed.
See MAP report file "SFpga_map.mrp" for details. See MAP report file "SFpga_map.mrp" for details.
...@@ -10,23 +10,23 @@ Target Device : xc6slx150t ...@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 13:46:59 2010 Mapped Date : Mon Dec 20 17:35:13 2010
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 86 Number of warnings: 86
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 843 out of 184,304 1% Number of Slice Registers: 834 out of 184,304 1%
Number used as Flip Flops: 843 Number used as Flip Flops: 834
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 993 out of 92,152 1% Number of Slice LUTs: 965 out of 92,152 1%
Number used as logic: 951 out of 92,152 1% Number used as logic: 934 out of 92,152 1%
Number using O6 output only: 595 Number using O6 output only: 579
Number using O5 output only: 196 Number using O5 output only: 187
Number using O5 and O6: 160 Number using O5 and O6: 168
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1% Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -38,20 +38,20 @@ Slice Logic Utilization: ...@@ -38,20 +38,20 @@ Slice Logic Utilization:
Number using O6 output only: 6 Number using O6 output only: 6
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 28 Number used exclusively as route-thrus: 17
Number with same-slice register load: 18 Number with same-slice register load: 7
Number with same-slice carry load: 10 Number with same-slice carry load: 10
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 395 out of 23,038 1% Number of occupied Slices: 383 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,152 Number of LUT Flip Flop pairs used: 1,137
Number with an unused Flip Flop: 387 out of 1,152 33% Number with an unused Flip Flop: 369 out of 1,137 32%
Number with an unused LUT: 159 out of 1,152 13% Number with an unused LUT: 172 out of 1,137 15%
Number of fully used LUT-FF pairs: 606 out of 1,152 52% Number of fully used LUT-FF pairs: 596 out of 1,137 52%
Number of unique control sets: 34 Number of unique control sets: 34
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 91 out of 184,304 1% to control set restrictions: 76 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -92,11 +92,11 @@ Specific Feature Utilization: ...@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02 Average Fanout of Non-Clock Nets: 3.00
Peak Memory Usage: 632 MB Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 49 secs Total REAL time to MAP completion: 38 secs
Total CPU time to MAP completion: 48 secs Total CPU time to MAP completion: 36 secs
Table of Contents Table of Contents
----------------- -----------------
......
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Mon Dec 20 13:47:48 2010"> <application stringID="Map" timeStamp="Mon Dec 20 17:35:52 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -64,16 +64,16 @@ ...@@ -64,16 +64,16 @@
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/> <item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/>
</section> </section>
<task stringID="MAP_PACK_REPORT"> <task stringID="MAP_PACK_REPORT">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="843"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="834">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="843"/> <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="834"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="975"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="958">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="196"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="187"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="595"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="579"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="160"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="168"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
...@@ -116,21 +116,21 @@ ...@@ -116,21 +116,21 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/> <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/> <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="86"/> <item dataType="int" stringID="MAP_NUM_WARNINGS" value="86"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="647668"/> <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="644020"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="49 secs "/> <item stringID="MAP_TOTAL_REAL_TIME" value="38 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="48 secs "/> <item stringID="MAP_TOTAL_CPU_TIME" value="36 secs "/>
</section> </section>
<section stringID="MAP_SLICE_REPORTING"> <section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="843"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="834">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="843"/> <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="834"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="993"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="965">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="196"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="187"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="595"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="579"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="160"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="168"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
...@@ -144,21 +144,21 @@ ...@@ -144,21 +144,21 @@
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="6"/> <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="6"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="10"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="10"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="18"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="18"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="10"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="10"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>