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Commit 23b1b4b5 authored by Andrea Boccardi's avatar Andrea Boccardi
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Added the Xilinx ISE project. 

Some Verilog file had to be modified, simulation to be checked
parent e3bedab5
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trunk/firmware/XilinxISE/SystemFpga/SFpga.bld 0 → 100644
View file @ 23b1b4b5
Release 12.3 ngdbuild M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc
SFpga.ngd
Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "SFpga.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N450' has no driver
WARNING:NgdBuild:452 - logical net 'N452' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgClk_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgCsi_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgRdWr_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgInit_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TempIdDQ_io' has no legal driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 14
Total memory usage is 88036 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 6 sec
Total CPU time to NGDBUILD completion: 5 sec
Writing NGDBUILD log file "SFpga.bld"...
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log 0 → 100644
View file @ 23b1b4b5
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf
ibiswriter -intstyle ise -vccaux 2.5 -truncate 20 SFpga.ncd SFpga.ibs
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga_preroute.twx SFpga_map.ncd -o SFpga_preroute.twr SFpga.pcf
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga_preroute.twx SFpga_map.ncd -o SFpga_preroute.twr SFpga.pcf -ucf SFpga.ucf
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.ibs 0 → 100644
View file @ 23b1b4b5
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ncd 0 → 100644
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This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngc 0 → 100644
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This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngd 0 → 100644
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This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ngr 0 → 100644
View file @ 23b1b4b5
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.pad 0 → 100644
View file @ 23b1b4b5
Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:09 2010
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: SFpga_map.ncd
OUTPUT FILE: SFpga.pad
PART TYPE: xc6slx150t
SPEED GRADE: -3
PACKAGE: fgg676
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
A1|||GND||||||||||||
A2|DdsF_ob2<1>|IOB|IO_L14N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
A3|DdsProfile_ob3<2>|IOB|IO_L14P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
A4|DdsProfile_ob3<0>|IOB|IO_L22N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
A5|DdsOsk_o|IOB|IO_L24N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
A6||OPAD|MGTTXN0_101|UNUSED|||||||||||
A7|||MGTAVTTTX_101||||||||||||
A8||OPAD|MGTTXN1_101|UNUSED|||||||||||
A9|||GND||||||||||||
A10||IPAD|MGTREFCLK0N_101|UNUSED|||||||||||
A11|||GND||||||||||||
A12|Si57x_ikn|IOB|IO_L36N_GCLK14_0||LVDS_33|0||||||LOCATED|NO|DIFF_TERM|
A13||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
A14|DdsSyncIn_okn|IOBS|IO_L37N_GCLK12_0||LVDS_33|0||||||LOCATED|NO||
A15|||GND||||||||||||
A16||IPAD|MGTREFCLK1N_123|UNUSED|||||||||||
A17|||GND||||||||||||
A18||OPAD|MGTTXN0_123|UNUSED|||||||||||
A19|||MGTAVTTTX_123||||||||||||
A20||OPAD|MGTTXN1_123|UNUSED|||||||||||
A21|||GND||||||||||||
A22|VmeD_iob32<0>|IOB|IO_L63N_SCP6_0|BIDIR|LVCMOS33|0|12|||NONE||LOCATED|NO|NONE|
A23|VmeD_iob32<2>|IOB|IO_L65N_SCP2_0|BIDIR|LVCMOS33|0|12|||NONE||LOCATED|NO|NONE|
A24|||TCK||||||||||||
A25|VmeD_iob32<5>|IOB|IO_L2N_M5A14_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
A26|||GND||||||||||||
AA1|PcbRev_ib8<0>|IOB|IO_L36N_M3DQ9_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AA2|PcbRev_ib8<1>|IOB|IO_L36P_M3DQ8_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AA3|AFpgaProgD_iob8<2>|IOB|IO_L2N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AA4|AFpgaProgM_iob2<1>|IOB|IO_L2P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AA5|||VCCAUX||||||||2.5||||
AA6|PllFmc1SClk_ok|IOB|IO_L64N_D9_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AA7|PushButton_ion|IOB|IO_L64P_D8_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AA8|PllFmc1RefSel_o|IOB|IO_L52N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AA9|PllFmc1Ld_i|IOB|IO_L47P_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AA10|PllFmc1RefMon_i|IOB|IO_L48P_D7_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AA11|PllFmc1Ref1_ok|IOB|IO_L41N_VREF_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AA12|PllSysSClk_ok|IOB|IO_L33N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AA13|PllSysSynch_on|IOB|IO_L36N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AA14|||VCCO_2|||2|||||3.30||||
AA15|PllSysRef12_ok|IOBM|IO_L28P_2|OUTPUT|LVDS_33|2||||||LOCATED|NO|NONE|
AA16|VmeD_iob32<28>|IOB|IO_L24N_VREF_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
AA17|VmeD_iob32<25>|IOB|IO_L16N_VREF_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
AA18|FlashAFpgaQ_i|IOB|IO_L20P_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AA19|VmeD_iob32<22>|IOB|IO_L18P_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
AA20|||VCCO_2|||2|||||3.30||||
AA21|PllDacSClk_ok|IOB|IO_L15P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AA22|PllDacLDac_on|IOB|IO_L2N_CMPMOSI_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AA23||IOBM|IO_L67P_1|UNUSED||1|||||||||
AA24||IOBS|IO_L67N_1|UNUSED||1|||||||||
AA25||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1|||||||||
AA26||IOBS|IO_L47N_LDC_M1DQ1_1|UNUSED||1|||||||||
AB1|PcbRev_ib8<2>|IOB|IO_L32N_M3DQ15_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AB2|||GND||||||||||||
AB3|AFpgaProgClk_io|IOB|IO_L32P_M3DQ14_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AB4|AFpgaProgCsi_io|IOB|IO_L8P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AB5|AFpgaProgD_iob8<0>|IOB|IO_L1P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AB6|||VCCO_2|||2|||||3.30||||
AB7|PllFmc1Synch_on|IOB|IO_L53P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AB8|||VCCAUX||||||||2.5||||
AB9|PllFmc1Status_i|IOB|IO_L47N_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AB10|||MGTRREF_245||||||||||||
AB11|PllSysCs_on|IOB|IO_L48N_RDWR_B_VREF_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AB12|||MGTAVTTRCAL_245||||||||||||
AB13|PllSysRefSel_o|IOB|IO_L36P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AB14|PllSysStatus_i|IOB|IO_L30P_GCLK1_D13_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AB15|PllSysRef12_okn|IOBS|IO_L28N_2||LVDS_33|2||||||LOCATED|NO||
AB16|||GND||||||||||||
AB17|FlashAFpgaCs_on|IOB|IO_L20N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AB18|||VCCAUX||||||||2.5||||
AB19|VmeD_iob32<21>|IOB|IO_L18N_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
AB20|||GND||||||||||||
AB21|PllDacDin_o|IOB|IO_L15N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AB22|PllDacSynch_on|IOB|IO_L5P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AB23|||VCCO_1|||1|||||1.50||||
AB24||IOBM|IO_L49P_M1DQ10_1|UNUSED||1|||||||||
AB25|||GND||||||||||||
AB26||IOBS|IO_L49N_M1DQ11_1|UNUSED||1|||||||||
AC1|PcbRev_ib8<3>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AC2|PcbRev_ib8<4>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AC3|PllDdsRefSel_o|IOB|IO_L8N_3|OUTPUT|LVCMOS25*|3|12|||||UNLOCATED|NO|NONE|
AC4|SysAppSlow_iob2<1>|IOB|IO_L1N_VREF_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
AC5|PllFmc1Reset_orn|IOB|IO_L61P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AC6|PllFmc1Sdo_i|IOB|IO_L53N_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AC7|||VCCAUX||||||||2.5||||
AC8||IPAD|MGTRXP0_245|UNUSED|||||||||||
AC9|||MGTAVTTRX_245||||||||||||
AC10||IPAD|MGTRXP1_245|UNUSED|||||||||||
AC11|||GND||||||||||||
AC12||IPAD|MGTREFCLK1P_245|UNUSED|||||||||||
AC13|||GND||||||||||||
AC14|PllSysLd_i|IOB|IO_L30N_GCLK0_USERCCLK_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AC15|||GND||||||||||||
AC16||IPAD|MGTREFCLK0P_267|UNUSED|||||||||||
AC17|||GND||||||||||||
AC18||IPAD|MGTRXP0_267|UNUSED|||||||||||
AC19|||MGTAVTTRX_267||||||||||||
AC20||IPAD|MGTRXP1_267|UNUSED|||||||||||
AC21|||VCCAUX||||||||2.5||||
AC22|FlashAFpgaClk_ok|IOB|IO_L5N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AC23||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
AC24||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
AC25|DdrUDQS_io|IOB|IO_L50P_M1UDQS_1|TRISTATE|DIFF_SSTL15_II|1||||||LOCATED|NO|NONE|
AC26|DdrUDQS_ion|IOB|IO_L50N_M1UDQSN_1|TRISTATE|DIFF_SSTL15_II|1||||||LOCATED|NO|NONE|
AD1|PcbRev_ib8<5>|IOB|IO_L33N_M3DQ13_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AD2|||VCCO_3|||3|||||2.50||||
AD3|AFpgaProgM_iob2<0>|IOB|IO_L33P_M3DQ12_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AD4|PllFmc1Pd_on|IOB|IO_L63P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AD5|PllFmc1SDio_io|IOB|IO_L61N_VREF_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AD6|PllFmc1Cs_on|IOB|IO_L49P_D3_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AD7|||GND||||||||||||
AD8||IPAD|MGTRXN0_245|UNUSED|||||||||||
AD9|||GND||||||||||||
AD10||IPAD|MGTRXN1_245|UNUSED|||||||||||
AD11|||MGTAVCC_245||||||||||||
AD12||IPAD|MGTREFCLK1N_245|UNUSED|||||||||||
AD13|||MGTAVCCPLL1_245||||||||||||
AD14|PllSysRefMon_i|IOB|IO_L32P_GCLK29_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AD15|||MGTAVCCPLL0_267||||||||||||
AD16||IPAD|MGTREFCLK0N_267|UNUSED|||||||||||
AD17|||MGTAVCC_267||||||||||||
AD18||IPAD|MGTRXN0_267|UNUSED|||||||||||
AD19|||GND||||||||||||
AD20||IPAD|MGTRXN1_267|UNUSED|||||||||||
AD21|||GND||||||||||||
AD22||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
AD23|FlashSFpgaQ_i|IOB|IO_L3P_D0_DIN_MISO_MISO1_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AD24||IOBM|IO_L48P_HDC_M1DQ8_1|UNUSED||1|||||||||
AD25|||VCCO_1|||1|||||1.50||||
AD26||IOBS|IO_L48N_M1DQ9_1|UNUSED||1|||||||||
AE1|PcbRev_ib8<6>|IOB|IO_L35N_M3DQ11_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AE2|PcbRev_ib8<7>|IOB|IO_L35P_M3DQ10_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AE3||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
AE4|||VCCO_2|||2|||||3.30||||
AE5|PllSysReset_orn|IOB|IO_L51P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AE6|||GND||||||||||||
AE7||OPAD|MGTTXP0_245|UNUSED|||||||||||
AE8|||GND||||||||||||
AE9||OPAD|MGTTXP1_245|UNUSED|||||||||||
AE10|||GND||||||||||||
AE11||IPAD|MGTREFCLK0P_245|UNUSED|||||||||||
AE12|||MGTAVCCPLL0_245||||||||||||
AE13||IOBM|IO_L31P_GCLK31_D14_2|UNUSED||2|||||||||
AE14|||VCCO_2|||2|||||3.30||||
AE15|VmeP0LvdsBunchClkIn_i|IOB|IO_L29P_GCLK3_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AE16|||MGTAVCCPLL1_267||||||||||||
AE17||IPAD|MGTREFCLK1P_267|UNUSED|||||||||||
AE18|||GND||||||||||||
AE19||OPAD|MGTTXP0_267|UNUSED|||||||||||
AE20|||GND||||||||||||
AE21||OPAD|MGTTXP1_267|UNUSED|||||||||||
AE22|||GND||||||||||||
AE23|||VCCO_2|||2|||||3.30||||
AE24|FlashSFpgaClk_ok|IOB|IO_L1P_CCLK_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AE25||IOBM|IO_L52P_M1DQ14_1|UNUSED||1|||||||||
AE26||IOBS|IO_L52N_M1DQ15_1|UNUSED||1|||||||||
AF1|||GND||||||||||||
AF2|||PROGRAM_B_2||||||||||||
AF3|FlashSFpgaCs_on|IOB|IO_L65N_CSO_B_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AF4|PllSysPd_on|IOB|IO_L63N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AF5|PllSysSDio_io|IOB|IO_L51N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AF6|PllSysSdo_i|IOB|IO_L49N_D4_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AF7||OPAD|MGTTXN0_245|UNUSED|||||||||||
AF8|||MGTAVTTTX_245||||||||||||
AF9||OPAD|MGTTXN1_245|UNUSED|||||||||||
AF10|||GND||||||||||||
AF11||IPAD|MGTREFCLK0N_245|UNUSED|||||||||||
AF12|||GND||||||||||||
AF13||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
AF14|VcTcXo_ik|IOB|IO_L32N_GCLK28_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
AF15|VmeP0LvdsBunchClkOut_o|IOB|IO_L29N_GCLK2_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AF16|||GND||||||||||||
AF17||IPAD|MGTREFCLK1N_267|UNUSED|||||||||||
AF18|||GND||||||||||||
AF19||OPAD|MGTTXN0_267|UNUSED|||||||||||
AF20|||MGTAVTTTX_267||||||||||||
AF21||OPAD|MGTTXN1_267|UNUSED|||||||||||
AF22|FlashAFpgaD_o|IOB|IO_L13N_D10_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AF23|FlashSFpgaD_o|IOB|IO_L3N_MOSI_CSI_B_MISO0_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AF24||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
AF25|||DONE_2||||||||||||
AF26|||GND||||||||||||
B1|FpGpIo34OutputMode_o|IOB|IO_L75N_M4BA1_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
B2|TempIdDQ_io|IOB|IO_L75P_M4BA0_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
B3|DdsF_ob2<0>|IOB|IO_L4N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
B4|DdsProfile_ob3<1>|IOB|IO_L22P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
B5||IOBM|IO_L24P_0|UNUSED||0|||||||||
B6||OPAD|MGTTXP0_101|UNUSED|||||||||||
B7|||GND||||||||||||
B8||OPAD|MGTTXP1_101|UNUSED|||||||||||
B9|||GND||||||||||||
B10||IPAD|MGTREFCLK0P_101|UNUSED|||||||||||
B11|||MGTAVCCPLL0_101||||||||||||
B12|Si57x_ik|IOB|IO_L36P_GCLK15_0|INPUT|LVDS_33|0||||NONE||LOCATED|NO|DIFF_TERM|
B13|||VCCO_0|||0|||||3.30||||
B14|DdsSyncIn_ok|IOBM|IO_L37P_GCLK13_0|OUTPUT|LVDS_33|0||||||LOCATED|NO|NONE|
B15|||MGTAVCCPLL1_123||||||||||||
B16||IPAD|MGTREFCLK1P_123|UNUSED|||||||||||
B17|||GND||||||||||||
B18||OPAD|MGTTXP0_123|UNUSED|||||||||||
B19|||GND||||||||||||
B20||OPAD|MGTTXP1_123|UNUSED|||||||||||
B21|VmeTdo_o|IOB|IO_L59N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
B22|VmeD_iob32<1>|IOB|IO_L63P_SCP7_0|BIDIR|LVCMOS33|0|12|||NONE||LOCATED|NO|NONE|
B23|VmeD_iob32<3>|IOB|IO_L65P_SCP3_0|BIDIR|LVCMOS33|0|12|||NONE||LOCATED|NO|NONE|
B24|VmeD_iob32<4>|IOB|IO_L2P_M5A13_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
B25|VmeD_iob32<6>|IOB|IO_L11P_M5CLK_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
B26|VmeD_iob32<7>|IOB|IO_L11N_M5CLKN_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
C1|FpGpIo1OutputMode_o|IOB|IO_L79N_M4A9_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
C2|FpGpIo2OutputMode_o|IOB|IO_L79P_M4A8_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
C3|DdsD_ob16<14>|IOB|IO_L4P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
C4|||VCCO_0|||0|||||3.30||||
C5|DdsD_ob16<9>|IOB|IO_L16N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
C6|||GND||||||||||||
C7||IPAD|MGTRXN0_101|UNUSED|||||||||||
C8|||GND||||||||||||
C9||IPAD|MGTRXN1_101|UNUSED|||||||||||
C10|||MGTAVCC_101||||||||||||
C11||IPAD|MGTREFCLK1N_101|UNUSED|||||||||||
C12|||MGTAVCCPLL1_101||||||||||||
C13||IOBM|IO_L35P_GCLK17_0|UNUSED||0|||||||||
C14|||MGTAVCCPLL0_123||||||||||||
C15||IPAD|MGTREFCLK0N_123|UNUSED|||||||||||
C16|||MGTAVCC_123||||||||||||
C17||IPAD|MGTRXN0_123|UNUSED|||||||||||
C18|||GND||||||||||||
C19||IPAD|MGTRXN1_123|UNUSED|||||||||||
C20|||GND||||||||||||
C21|VmeTdi_i|IOB|IO_L59P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
C22|||VCCO_0|||0|||||3.30||||
C23|||TDI||||||||||||
C24|VmeA_iob31<20>|IOB|IO_L4N_M5A12_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
C25|VmeD_iob32<8>|IOB|IO_L10P_M5A0_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
C26|VmeD_iob32<9>|IOB|IO_L10N_M5A1_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
D1|PllDdsCs_on|IOB|IO_L68N_M4DQ5_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
D2|||VCCO_4|||4|||||3.30||||
D3|PllDdsSdo_i|IOB|IO_L68P_M4DQ4_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
D4|||GND||||||||||||
D5|DdsD_ob16<10>|IOB|IO_L16P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
D6|||VCCAUX||||||||2.5||||
D7||IPAD|MGTRXP0_101|UNUSED|||||||||||
D8|||MGTAVTTRX_101||||||||||||
D9||IPAD|MGTRXP1_101|UNUSED|||||||||||
D10|||GND||||||||||||
D11||IPAD|MGTREFCLK1P_101|UNUSED|||||||||||
D12|||GND||||||||||||
D13|DdsPdClk_ik|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
D14|||GND||||||||||||
D15||IPAD|MGTREFCLK0P_123|UNUSED|||||||||||
D16|||GND||||||||||||
D17||IPAD|MGTRXP0_123|UNUSED|||||||||||
D18|||MGTAVTTRX_123||||||||||||
D19||IPAD|MGTRXP1_123|UNUSED|||||||||||
D20|||VCCAUX||||||||2.5||||
D21|VmeTms_i|IOB|IO_L66P_SCP1_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
D22|VmeTck_i|IOB|IO_L66N_SCP0_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
D23|VmeA_iob31<21>|IOB|IO_L4P_M5CKE_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
D24|VmeA_iob31<22>|IOB|IO_L17P_M5DQ6_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
D25|||VCCO_5|||5|||||3.30||||
D26|VmeD_iob32<10>|IOB|IO_L17N_M5DQ7_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
E1|PllDdsSynch_on|IOB|IO_L67N_M4DQ7_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
E2|PllDdsSClk_ok|IOB|IO_L67P_M4DQ6_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
E3|PllDdsReset_orn|IOB|IO_L81N_M4A11_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
E4|PllDdsSDio_io|IOB|IO_L81P_M4RESET_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
E5|DdsD_ob16<11>|IOB|IO_L8N_VREF_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E6|DdsD_ob16<6>|IOB|IO_L8P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E7|||GND||||||||||||
E8|DdsD_ob16<3>|IOB|IO_L15N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E9|||MGTRREF_101||||||||||||
E10|DdsD_ob16<8>|IOB|IO_L23N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E11|||MGTAVTTRCAL_101||||||||||||
E12|DdsSDio_io|IOB|IO_L31N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E13|DdsSyncClk_ik|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
E14||IOBS|IO_L40N_0|UNUSED||0|||||||||
E15|||GND||||||||||||
E16|VmeP0HwLowByteOe_o|IOB|IO_L49N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E17|||VCCAUX||||||||2.5||||
E18|Si57xOe_o|IOB|IO_L51N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E19|||GND||||||||||||
E20|VmeWrite_in|IOB|IO_L57N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
E21|||VCCO_0|||0|||||3.30||||
E22|||GND||||||||||||
E23|VmeA_iob31<19>|IOB|IO_L8P_M5A7_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
E24|VmeA_iob31<18>|IOB|IO_L8N_M5A2_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
E25|VmeD_iob32<11>|IOB|IO_L16P_M5DQ4_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
E26|VmeD_iob32<12>|IOB|IO_L16N_M5DQ5_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
F1|PllDdsStatus_i|IOB|IO_L66N_M4LDQSN_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
F2|||GND||||||||||||
F3|PllDdsPd_on|IOB|IO_L66P_M4LDQS_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
F4|||VCCO_4|||4|||||3.30||||
F5|DdsD_ob16<12>|IOB|IO_L5N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F6|DdsD_ob16<7>|IOB|IO_L3N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F7|DdsD_ob16<4>|IOB|IO_L3P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F8|||VCCO_0|||0|||||3.30||||
F9|DdsD_ob16<1>|IOB|IO_L15P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F10|DdsD_ob16<0>|IOB|IO_L23P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F11|DdsSClk_o|IOB|IO_L30N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F12|DdsSDo_i|IOB|IO_L31P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
F13|||VCCO_0|||0|||||3.30||||
F14|Si57xSCl_ok|IOB|IO_L40P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F15|VmeP0BunchSelectOe_o|IOB|IO_L50N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F16|VmeP0HwLowByteDir_o|IOB|IO_L49P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F17|VmeRetryOe_oe|IOB|IO_L56N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F18|VmeIack_in|IOB|IO_L51P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
F19|VmeAOeN_oen|IOB|IO_L64N_SCP4_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F20|VmeADirVfcToVme_o|IOB|IO_L57P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
F21|||TMS||||||||||||
F22|VmeA_iob31<17>|IOB|IO_L6P_M5A10_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
F23|VmeA_iob31<15>|IOB|IO_L14P_M5RASN_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
F24|VmeA_iob31<16>|IOB|IO_L18P_M5LDQS_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
F25|||GND||||||||||||
F26|VmeD_iob32<13>|IOB|IO_L18N_M5LDQSN_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
G1|PllDdsRefMon_i|IOB|IO_L65N_M4DQ3_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
G2|PllDdsLd_i|IOB|IO_L65P_M4DQ2_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
G3|Sfp2TxDisable_o|IOB|IO_L77N_M4BA2_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
G4|Sfp2TxFault_i|IOB|IO_L77P_M4WE_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
G5|||VCCAUX||||||||2.5||||
G6|DdsD_ob16<13>|IOB|IO_L5P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
G7|DdsD_ob16<5>|IOB|IO_L1N_VREF_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
G8|DdsTxEnable_o|IOB|IO_L2N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
G9|DdsD_ob16<2>|IOB|IO_L13N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
G10|DdsPllLock_i|IOB|IO_L21N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
G11|DdsIoReset_or|IOB|IO_L32N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
G12|DdsDrHold_o|IOB|IO_L30P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
G13|DdsDrOver_i|IOB|IO_L33N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
G14|||GND||||||||||||
G15|VmeP0BunchSelectDir_o|IOB|IO_L50P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
G16|VmeAm_ib6<1>|IOB|IO_L56P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
G17|VmeRetry_on|IOB|IO_L58N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
G18|||VCCO_0|||0|||||3.30||||
G19|VmeAm_ib6<0>|IOB|IO_L64P_SCP5_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
G20|VmeDs_inb2<1>|IOB|IO_L1N_A24_VREF_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
G21|||TDO||||||||||||
G22|||VCCO_5|||5|||||3.30||||
G23|VmeA_iob31<14>|IOB|IO_L6N_M5A4_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
G24|VmeA_iob31<13>|IOB|IO_L14N_M5CASN_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
G25|VmeD_iob32<14>|IOB|IO_L20P_M5DQ0_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
G26|VmeD_iob32<15>|IOB|IO_L20N_M5DQ1_5|BIDIR|LVCMOS33|5|12|||NONE||LOCATED|NO|NONE|
H1|VAdjCs_on|IOB|IO_L64N_M4DQ1_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
H2|||VCCO_4|||4|||||3.30||||
H3|Sfp2ModeDef0_i|IOB|IO_L64P_M4DQ0_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
H4|||GND||||||||||||
H5|Sfp2ModeDef1_i|IOB|IO_L83N_VREF_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
H6||IOBM|IO_L83P_4|UNUSED||4|||||||||
H7||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0|||||||||
H8|DdsSyncSmpErr_i|IOB|IO_L2P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
H9|DdsMasterRst_or|IOB|IO_L13P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
H10|DdsPowerDown_o|IOB|IO_L21P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
H11|||VCCO_0|||0|||||3.30||||
H12|DdsDrCtl_o|IOB|IO_L33P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
H13|VmeD_iob32<16>|IOB|IO_L39N_0|BIDIR|LVCMOS33|0|12|||NONE||LOCATED|NO|NONE|
H14|VmeP0HwHighByteDir_o|IOB|IO_L41N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
H15|VmeD_iob32<17>|IOB|IO_L43N_0|BIDIR|LVCMOS33|0|12|||NONE||LOCATED|NO|NONE|
H16|||VCCO_0|||0|||||3.30||||
H17|VmeAm_ib6<4>|IOB|IO_L58P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
H18|VmeAm_ib6<3>|IOB|IO_L62P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
H19|VmeAm_ib6<2>|IOB|IO_L62N_VREF_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
H20|VmeDs_inb2<2>|IOB|IO_L1P_A25_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
H21|VmeA_iob31<10>|IOB|IO_L5P_M5A8_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
H22|VmeA_iob31<12>|IOB|IO_L5N_M5A9_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
H23|||GND||||||||||||
H24|VmeA_iob31<11>|IOB|IO_L19P_M5DQ2_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
H25|||VCCO_5|||5|||||3.30||||
H26|VmeTrst_i|IOB|IO_L19N_M5DQ3_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
J1|VAdjDin_o|IOB|IO_L63N_M4DQ9_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
J2|VAdjSClk_ok|IOB|IO_L63P_M4DQ8_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
J3|Sfp2LoS_i|IOB|IO_L69N_M4LDM_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
J4|Sfp2RateSelect|IOB|IO_L69P_M4UDM_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
J5|WRTxFault_i|IOB|IO_L73N_M4CLKN_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
J6|||VCCO_4|||4|||||3.30||||
J7|VmeIrq_ob7<2>|IOB|IO_L78N_M4A4_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
J8|||GND||||||||||||
J9|VmeDtAckOe_oe|IOB|IO_L78P_M4A10_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
J10|||VCCAUX||||||||2.5||||
J11|DdsRamSwpOvr_i|IOB|IO_L32P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
J12|VmeP0BuslineDir_o|IOB|IO_L38N_VREF_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
J13|VmeP0BuslineOe_o|IOB|IO_L39P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
J14|||VCCO_0|||0|||||3.30||||
J15|VmeD_iob32<18>|IOB|IO_L43P_0|BIDIR|LVCMOS33|0|12|||NONE||LOCATED|NO|NONE|
J16|VmeSysReset_in|IOB|IO_L48P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
J17|VmeAm_ib6<5>|IOB|IO_L48N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
J18|||VCCAUX||||||||2.5||||
J19|||GND||||||||||||
J20|VmeA_iob31<25>|IOB|IO_L7P_M5WE_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
J21|||VCCO_5|||5|||||3.30||||
J22|VmeA_iob31<7>|IOB|IO_L7N_M5BA2_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
J23|VmeA_iob31<9>|IOB|IO_L15P_M5UDM_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
J24|VmeA_iob31<8>|IOB|IO_L15N_M5LDM_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
J25|VmeGaP_in|IOB|IO_L22P_M5DQ10_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
J26|VmeGa_ib5n<0>|IOB|IO_L22N_M5DQ11_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
K1|VAdjSpi_o|IOB|IO_L62N_M4DQ11_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
K2|||GND||||||||||||
K3||IOBM|IO_L62P_M4DQ10_4|UNUSED||4|||||||||
K4|||VCCO_4|||4|||||3.30||||
K5|WRTxDisable_o|IOB|IO_L73P_M4CLK_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
K6|WRModeDef1_i|IOB|IO_L82N_M4A14_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
K7|VmeIrq_ob7<3>|IOB|IO_L82P_M4A13_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
K8|VmeTdoOe_oe|IOB|IO_L80N_M4A12_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
K9|VmeDOeN_oen|IOB|IO_L80P_M4CKE_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
K10|VmeP0LvdsTClkOut_o|IOB|IO_L76N_M4A2_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
K11|||VCCINT||||||||1.2||||
K12|DdsD_ob16<15>|IOB|IO_L38P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
K13|||VCCAUX||||||||2.5||||
K14|VmeP0HwHighByteOe_o|IOB|IO_L41P_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
K15|||VCCAUX||||||||2.5||||
K16|||GND||||||||||||
K17|||VCCINT||||||||1.2||||
K18|VmeA_iob31<24>|IOB|IO_L3P_M5RESET_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
K19|VmeA_iob31<26>|IOB|IO_L3N_M5A11_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
K20|VmeA_iob31<27>|IOB|IO_L9N_M5BA1_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
K21|VmeA_iob31<6>|IOB|IO_L12P_M5A3_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
K22|VmeA_iob31<4>|IOB|IO_L12N_M5ODT_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
K23|||VCCO_5|||5|||||3.30||||
K24|VmeA_iob31<5>|IOB|IO_L21P_M5DQ8_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
K25|||GND||||||||||||
K26|VmeGa_ib5n<1>|IOB|IO_L21N_M5DQ9_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
L1||IOBS|IO_L61N_M4UDQSN_4|UNUSED||4|||||||||
L2||IOBM|IO_L61P_M4UDQS_4|UNUSED||4|||||||||
L3|WRModeDef0_i|IOB|IO_L71N_M4A6_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
L4|WRRateSelect_o|IOB|IO_L71P_M4A5_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
L5|||VCCAUX||||||||2.5||||
L6|WRLoS_i|IOB|IO_L74N_M4A1_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
L7|VmeIrq_ob7<1>|IOB|IO_L74P_M4A0_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
L8|VmeSysClk_ik|IOB|IO_L70N_M4CASN_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
L9|VmeDDirVfcToVme_o|IOB|IO_L70P_M4RASN_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
L10|VmeP0LvdsTClkIn_i|IOB|IO_L76P_M4A7_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
L11|||GND||||||||||||
L12|||VCCINT||||||||1.2||||
L13|||GND||||||||||||
L14|||VCCINT||||||||1.2||||
L15|||GND||||||||||||
L16|||VCCINT||||||||1.2||||
L17|||GND||||||||||||
L18|||VCCAUX||||||||2.5||||
L19|VmeA_iob31<28>|IOB|IO_L9P_M5BA0_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
L20|VmeA_iob31<29>|IOB|IO_L27P_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
L21|VmeA_iob31<3>|IOB|IO_L27N_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
L22|||VCCAUX||||||||2.5||||
L23|DdrA_ob14<13>|IOB|IO_L29P_A23_M1A13_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
L24||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1|||||||||
L25|VmeGa_ib5n<2>|IOB|IO_L24P_M5DQ12_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
L26|VmeGa_ib5n<3>|IOB|IO_L24N_M5DQ13_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
M1|Fmc2SCl_ok|IOB|IO_L60N_M4DQ13_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
M2|||VCCO_4|||4|||||3.30||||
M3|VmeIrq_ob7<4>|IOB|IO_L60P_M4DQ12_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
M4|VmeIrq_ob7<5>|IOB|IO_L58P_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
M5|||GND||||||||||||
M6|VmeIrq_ob7<7>|IOB|IO_L72N_M4ODT_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
M7|||VCCO_4|||4|||||3.30||||
M8|VmeAs_in|IOB|IO_L72P_M4A3_4|INPUT|LVCMOS33|4||||NONE||LOCATED|NO|NONE|
M9||IOBS|IO_L57N_VREF_3|UNUSED||3|||||||||
M10||IOBM|IO_L57P_3|UNUSED||3|||||||||
M11|||VCCINT||||||||1.2||||
M12|||VCCINT||||||||1.2||||
M13|||VCCINT||||||||1.2||||
M14|||VCCINT||||||||1.2||||
M15|||VCCINT||||||||1.2||||
M16|||VCCINT||||||||1.2||||
M17|||VCCAUX||||||||2.5||||
M18|VmeA_iob31<30>|IOB|IO_L13P_M5A5_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
M19|VmeA_iob31<31>|IOB|IO_L13N_M5A6_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
M20|||VCCO_5|||5|||||3.30||||
M21|VmeA_iob31<2>|IOB|IO_L26P_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
M22|||GND||||||||||||
M23|VmeLword_io|IOB|IO_L26N_VREF_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
M24|VmeA_iob31<1>|IOB|IO_L23P_M5UDQS_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
M25|||VCCO_5|||5|||||3.30||||
M26|VmeGa_ib5n<4>|IOB|IO_L23N_M5UDQSN_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
N1|Fmc1SCl_ok|IOB|IO_L59N_M4DQ15_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
N2||IOBM|IO_L59P_M4DQ14_4|UNUSED||4|||||||||
N3|VmeIrq_ob7<6>|IOB|IO_L58N_VREF_4|OUTPUT|LVCMOS33|4|12|||||LOCATED|NO|NONE|
N4||IOBS|IO_L54N_M3A11_3|UNUSED||3|||||||||
N5||IOBM|IO_L54P_M3RESET_3|UNUSED||3|||||||||
N6||IOBM|IO_L49P_M3A7_3|UNUSED||3|||||||||
N7||IOBS|IO_L51N_M3A4_3|UNUSED||3|||||||||
N8||IOBM|IO_L51P_M3A10_3|UNUSED||3|||||||||
N9||IOBS|IO_L55N_M3A14_3|UNUSED||3|||||||||
N10|||VCCAUX||||||||2.5||||
N11|||GND||||||||||||
N12|||VCCINT||||||||1.2||||
N13|||VCCINT||||||||1.2||||
N14|||GND||||||||||||
N15|||VCCINT||||||||1.2||||
N16|||VCCINT||||||||1.2||||
N17||IOBM|IO_L28P_1|UNUSED||1|||||||||
N18||IOBS|IO_L28N_VREF_1|UNUSED||1|||||||||
N19|DdrReset_or|IOB|IO_L30P_A21_M1RESET_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
N20|DdrA_ob14<11>|IOB|IO_L30N_A20_M1A11_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
N21|DdrCkE_o|IOB|IO_L31P_A19_M1CKE_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
N22|DdrA_ob14<12>|IOB|IO_L31N_A18_M1A12_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
N23|DdrA_ob14<10>|IOB|IO_L33P_A15_M1A10_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
N24|DdrA_ob14<4>|IOB|IO_L33N_A14_M1A4_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
N25|VmeDtAck_on|IOB|IO_L25P_M5DQ14_5|OUTPUT|LVCMOS33|5|12|||||LOCATED|NO|NONE|
N26|VmeA_iob31<23>|IOB|IO_L25N_M5DQ15_5|INPUT|LVCMOS33|5||||NONE||LOCATED|NO|NONE|
P1||IOBS|IO_L48N_M3BA1_3|UNUSED||3|||||||||
P2|||GND||||||||||||
P3||IOBM|IO_L48P_M3BA0_3|UNUSED||3|||||||||
P4|||VCCO_3|||3|||||2.50||||
P5|FpLed_onb8<0>|IOB|IO_L50P_M3WE_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
P6|FpLed_onb8<3>|IOB|IO_L49N_M3A2_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
P7|||GND||||||||||||
P8||IOBS|IO_L53N_M3A12_3|UNUSED||3|||||||||
P9|||VCCO_3|||3|||||2.50||||
P10|ManualAddress_ib5<4>|IOB|IO_L55P_M3A13_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
P11|||VCCINT||||||||1.2||||
P12|||VCCINT||||||||1.2||||
P13|||GND||||||||||||
P14|||VCCINT||||||||1.2||||
P15|||VCCINT||||||||1.2||||
P16|||GND||||||||||||
P17|DdrA_ob14<8>|IOB|IO_L32P_A17_M1A8_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
P18|||VCCO_1|||1|||||1.50||||
P19|DdrA_ob14<9>|IOB|IO_L32N_A16_M1A9_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
P20|||GND||||||||||||
P21|DdrA_ob14<7>|IOB|IO_L35P_A11_M1A7_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
P22|DdrA_ob14<2>|IOB|IO_L35N_A10_M1A2_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
P23|||VCCO_1|||1|||||1.50||||
P24|DdrA_ob14<0>|IOB|IO_L37P_A7_M1A0_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
P25|||GND||||||||||||
P26|DdrA_ob14<1>|IOB|IO_L37N_A6_M1A1_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
R1||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3|||||||||
R2||IOBM|IO_L44P_GCLK21_M3A5_3|UNUSED||3|||||||||
R3|FpLed_onb8<2>|IOB|IO_L52N_M3A9_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R4|FpLed_onb8<1>|IOB|IO_L52P_M3A8_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R5|FpLed_onb8<4>|IOB|IO_L50N_M3BA2_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R6|SysAppClk_ik|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
R7|SysAppClk_ok|IOB|IO_L43P_GCLK23_M3RASN_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R8|ManualAddress_ib5<0>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
R9|ManualAddress_ib5<2>|IOB|IO_L53P_M3CKE_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
R10|UseGa_i|IOB|IO_L47P_M3A0_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
R11|||VCCINT||||||||1.2||||
R12|||VCCINT||||||||1.2||||
R13|||VCCINT||||||||1.2||||
R14|||VCCINT||||||||1.2||||
R15|||VCCINT||||||||1.2||||
R16|||VCCINT||||||||1.2||||
R17|||VCCINT||||||||1.2||||
R18|DdrWe_o|IOB|IO_L34P_A13_M1WE_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
R19|DdrBA_ob3<2>|IOB|IO_L34N_A12_M1BA2_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
R20|DdrBA_ob3<0>|IOB|IO_L36P_A9_M1BA0_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
R21|DdrBA_ob3<1>|IOB|IO_L36N_A8_M1BA1_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
R22|||VCCAUX||||||||2.5||||
R23|DdrCk_ok|IOB|IO_L38P_A5_M1CLK_1|OUTPUT|DIFF_SSTL15_II|1||||||LOCATED|NO|NONE|
R24|DdrCk_okn|IOB|IO_L38N_A4_M1CLKN_1|OUTPUT|DIFF_SSTL15_II|1||||||LOCATED|NO|NONE|
R25|DdrRAS_o|IOB|IO_L41P_GCLK9_IRDY1_M1RASN_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
R26|DdrCAS_o|IOB|IO_L41N_GCLK8_M1CASN_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
T1||IOBS|IO_L41N_GCLK26_M3DQ5_3|UNUSED||3|||||||||
T2|||VCCO_3|||3|||||2.50||||
T3||IOBM|IO_L41P_GCLK27_M3DQ4_3|UNUSED||3|||||||||
T4|FpLed_onb8<7>|IOB|IO_L46N_M3CLKN_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
T5|||GND||||||||||||
T6|SysAppSlow_iob2<2>|IOB|IO_L31N_VREF_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
T7|||VCCO_3|||3|||||2.50||||
T8|ManualAddress_ib5<1>|IOB|IO_L45N_M3ODT_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
T9|ManualAddress_ib5<3>|IOB|IO_L47N_M3A1_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
T10|||GND||||||||||||
T11|||VCCINT||||||||1.2||||
T12|||GND||||||||||||
T13|||VCCINT||||||||1.2||||
T14|||GND||||||||||||
T15|||VCCINT||||||||1.2||||
T16|||GND||||||||||||
T17|||VCCINT||||||||1.2||||
T18|||GND||||||||||||
T19||IOBM|IO_L66P_1|UNUSED||1|||||||||
T20||IOBS|IO_L66N_1|UNUSED||1|||||||||
T21|||GND||||||||||||
T22|DdrA_ob14<3>|IOB|IO_L39P_M1A3_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
T23|DdrODT_o|IOB|IO_L39N_M1ODT_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
T24||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1|||||||||
T25|||VCCO_1|||1|||||1.50||||
T26||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
U1|Fmc2PrsntM2C_in|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U2|Fmc2PGC2M_in|IOB|IO_L40P_M3DQ6_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U3|FpLed_onb8<5>|IOB|IO_L10N_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U4|FpLed_onb8<6>|IOB|IO_L10P_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U5|AFpgaProgD_iob8<4>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U6|||VCCAUX||||||||2.5||||
U7||IOBM|IO_L31P_3|UNUSED||3|||||||||
U8|AFpgaProgInit_io|IOB|IO_L18N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U9||IOBM|IO_L18P_3|UNUSED||3|||||||||
U10|||VCCINT||||||||1.2||||
U11|||GND||||||||||||
U12|||VCCAUX||||||||2.5||||
U13|PllFmc2Cs_on|IOB|IO_L27P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
U14|||VCCAUX||||||||2.5||||
U15|PllFmc2Reset_orn|IOB|IO_L17P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
U16|||VCCINT||||||||1.2||||
U17|||GND||||||||||||
U18|||VCCAUX||||||||2.5||||
U19||IOBM|IO_L68P_1|UNUSED||1|||||||||
U20||IOBS|IO_L68N_1|UNUSED||1|||||||||
U21||IOBM|IO_L53P_1|UNUSED||1|||||||||
U22||IOBS|IO_L53N_VREF_1|UNUSED||1|||||||||
U23|DdrA_ob14<5>|IOB|IO_L40P_GCLK11_M1A5_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
U24|DdrA_ob14<6>|IOB|IO_L40N_GCLK10_M1A6_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
U25||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1|||||||||
U26||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1|||||||||
V1|Fmc1PrsntM2C_in|IOB|IO_L39N_M3LDQSN_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
V2|||GND||||||||||||
V3|AFpgaProgD_iob8<3>|IOB|IO_L39P_M3LDQS_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
V4||IOBM|IO_L42P_GCLK25_TRDY2_M3UDM_3|UNUSED||3|||||||||
V5|AFpgaProgD_iob8<6>|IOB|IO_L17P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
V6|Switch_ib2<0>|IOB|IO_L9N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
V7|Switch_ib2<1>|IOB|IO_L9P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
V8|||GND||||||||||||
V9|||VCCAUX||||||||2.5||||
V10|VmeIackOut_on|IOB|IO_L46N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
V11|PllFmc2SClk_ok|IOB|IO_L46P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
V12|PllFmc2Synch_on|IOB|IO_L35P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
V13|PllFmc2RefSel_o|IOB|IO_L27N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
V14|PllFmc2Sdo_i|IOB|IO_L26P_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
V15|PllFmc2SDio_io|IOB|IO_L26N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
V16|PllFmc2Pd_on|IOB|IO_L17N_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
V17|||VCCAUX||||||||2.5||||
V18|VmeBerr_o|IOB|IO_L12P_D1_MISO2_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
V19|||RFUSE||||||||||||
V20||IOBM|IO_L69P_1|UNUSED||1|||||||||
V21||IOBS|IO_L69N_VREF_1|UNUSED||1|||||||||
V22|||VBATT||||||||||||
V23|DdrUDM_o|IOB|IO_L42P_GCLK7_M1UDM_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
V24|DdrLDQS_io|IOB|IO_L45P_A1_M1LDQS_1|TRISTATE|DIFF_SSTL15_II|1||||||LOCATED|NO|NONE|
V25|||GND||||||||||||
V26|DdrLDQS_ion|IOB|IO_L45N_A0_M1LDQSN_1|TRISTATE|DIFF_SSTL15_II|1||||||LOCATED|NO|NONE|
W1|Fmc1PGC2M_in|IOB|IO_L38N_M3DQ3_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
W2|AFpgaProgD_iob8<5>|IOB|IO_L38P_M3DQ2_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
W3||IOBS|IO_L42N_GCLK24_M3LDM_3|UNUSED||3|||||||||
W4|||VCCO_3|||3|||||2.50||||
W5|AFpgaProgD_iob8<7>|IOB|IO_L17N_VREF_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
W6|||VCCO_3|||3|||||2.50||||
W7|VAdcCs_on|IOB|IO_L62N_D6_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
W8|VAdcSClk_ok|IOB|IO_L62P_D5_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
W9|VAdcDout_i|IOB|IO_L50N_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
W10|VmeIackIn_in|IOB|IO_L50P_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
W11|||VCCO_2|||2|||||3.30||||
W12|PllFmc2Status_i|IOB|IO_L35N_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
W13|||VCCAUX||||||||2.5||||
W14|VmeD_iob32<31>|IOB|IO_L34P_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
W15|||VCCO_2|||2|||||3.30||||
W16|VmeD_iob32<27>|IOB|IO_L19P_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
W17|VmeD_iob32<26>|IOB|IO_L14P_D11_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
W18|VmeD_iob32<23>|IOB|IO_L14N_D12_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
W19|VmeD_iob32<20>|IOB|IO_L12N_D2_MISO3_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
W20|VmeD_iob32<19>|IOB|IO_L4P_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
W21|||VCCO_1|||1|||||1.50||||
W22|||VFS||||||||||||
W23|||VCCO_1|||1|||||1.50||||
W24|DdrLDM_o|IOB|IO_L42N_GCLK6_TRDY1_M1LDM_1|OUTPUT|SSTL15_II|1||||||LOCATED|NO|NONE|
W25||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1|||||||||
W26||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1|||||||||
Y1||IOBS|IO_L37N_M3DQ1_3|UNUSED||3|||||||||
Y2|||VCCO_3|||3|||||2.50||||
Y3|AFpgaProgD_iob8<1>|IOB|IO_L37P_M3DQ0_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
Y4|||GND||||||||||||
Y5|AFpgaProgRdWr_io|IOB|IO_L7N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
Y6|PllDdsClk_ok|IOB|IO_L7P_3|OUTPUT|LVCMOS25*|3|12|||||UNLOCATED|NO|NONE|
Y7|||GND||||||||||||
Y8|||VCCO_2|||2|||||3.30||||
Y9|VAdcDin_o|IOB|IO_L52P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
Y10|||GND||||||||||||
Y11|PllFmc2RefMon_i|IOB|IO_L41P_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
Y12|PllFmc2Ref1_ok|IOB|IO_L33P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
Y13|PllFmc2Ld_i|IOB|IO_L34N_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
Y14|||GND||||||||||||
Y15|VmeD_iob32<30>|IOB|IO_L24P_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
Y16|VmeD_iob32<29>|IOB|IO_L19N_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
Y17|VmeD_iob32<24>|IOB|IO_L16P_2|BIDIR|LVCMOS33|2|12|||NONE||LOCATED|NO|NONE|
Y18|||VCCO_2|||2|||||3.30||||
Y19|||CMPCS_B_2||||||||||||
Y20|PllDacDout_i|IOB|IO_L4N_VREF_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
Y21|PllDacClrn_orn|IOB|IO_L2P_CMPCLK_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
Y22|||SUSPEND||||||||||||
Y23|||GND||||||||||||
Y24||IOBM|IO_L51P_M1DQ12_1|UNUSED||1|||||||||
Y25|||VCCO_1|||1|||||1.50||||
Y26||IOBS|IO_L51N_M1DQ13_1|UNUSED||1|||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
trunk/firmware/XilinxISE/SystemFpga/SFpga.par 0 → 100644
View file @ 23b1b4b5
Release 12.3 par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Thu Dec 16 18:43:02 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
Constraints file: SFpga.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 4
Number used as Single Port RAM: 0
Number used as Shift Register: 3
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 15
Number with same-slice register load: 6
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113
Number with an unused Flip Flop: 382 out of 1,113 34%
Number with an unused LUT: 196 out of 1,113 17%
Number of fully used LUT-FF pairs: 535 out of 1,113 48%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2
IOB Slave Pads: 2
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 268 0%
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 0 out of 586 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 24 secs
Finished initial Timing Analysis. REAL time: 24 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsRamSwpOvr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<4>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<5>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<7>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsSyncClk_ik_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal WRModeDef0_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeTrst_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsSDo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PllDacDout_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeP0LvdsTClkIn_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsPllLock_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal Sfp2ModeDef0_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal Sfp2LoS_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal WRTxFault_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeAm_ib6<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeAm_ib6<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal Sfp2TxFault_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgCsi_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgInit_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeP0LvdsBunchClkIn_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TempIdDQ_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsDrOver_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsPdClk_ik_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal WRLoS_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsSyncSmpErr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeTdi_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeTck_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal Fmc1PrsntM2C_in_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeTms_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal Fmc2PrsntM2C_in_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 5215 unrouted; REAL time: 27 secs
Phase 2 : 4592 unrouted; REAL time: 34 secs
Phase 3 : 1753 unrouted; REAL time: 46 secs
Phase 4 : 1753 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 57 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 4 secs
Total REAL time to Router completion: 1 mins 4 secs
Total CPU time to Router completion: 1 mins 2 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 221 | 0.247 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 18 | 0.186 | 1.688 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 217 | 0.000 | 4.055 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.159 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.189ns| 8.144ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.321ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 8 secs
Total CPU time to PAR completion: 1 mins 6 secs
Peak Memory Usage: 371 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 49
Number of info messages: 0
Writing design to file SFpga.ncd
PAR done!
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf 0 → 100644
View file @ 23b1b4b5
//! **************************************************************************
// Written by: Map M.70d on Thu Dec 16 18:42:57 2010
//! **************************************************************************
SCHEMATIC START;
COMP "VmeP0LvdsTClkOut_o" LOCATE = SITE "K10" LEVEL 1;
COMP "VmeA_iob31<1>" LOCATE = SITE "M24" LEVEL 1;
COMP "PllFmc2Pd_on" LOCATE = SITE "V16" LEVEL 1;
COMP "VmeA_iob31<2>" LOCATE = SITE "M21" LEVEL 1;
COMP "DdrODT_o" LOCATE = SITE "T23" LEVEL 1;
COMP "VmeA_iob31<3>" LOCATE = SITE "L21" LEVEL 1;
COMP "VmeA_iob31<4>" LOCATE = SITE "K22" LEVEL 1;
COMP "PllSysPd_on" LOCATE = SITE "AF4" LEVEL 1;
COMP "VmeA_iob31<5>" LOCATE = SITE "K24" LEVEL 1;
COMP "VmeA_iob31<6>" LOCATE = SITE "K21" LEVEL 1;
COMP "DdrLDQS_ion" LOCATE = SITE "V26" LEVEL 1;
COMP "VmeA_iob31<7>" LOCATE = SITE "J22" LEVEL 1;
COMP "VmeA_iob31<8>" LOCATE = SITE "J24" LEVEL 1;
COMP "VmeA_iob31<9>" LOCATE = SITE "J23" LEVEL 1;
COMP "DdrRAS_o" LOCATE = SITE "R25" LEVEL 1;
COMP "VmeA_iob31<10>" LOCATE = SITE "H21" LEVEL 1;
COMP "VmeA_iob31<11>" LOCATE = SITE "H24" LEVEL 1;
COMP "VmeA_iob31<12>" LOCATE = SITE "H22" LEVEL 1;
COMP "VmeA_iob31<20>" LOCATE = SITE "C24" LEVEL 1;
COMP "FlashSFpgaD_o" LOCATE = SITE "AF23" LEVEL 1;
COMP "PllFmc1Sdo_i" LOCATE = SITE "AC6" LEVEL 1;
COMP "VmeA_iob31<13>" LOCATE = SITE "G24" LEVEL 1;
COMP "VmeA_iob31<21>" LOCATE = SITE "D23" LEVEL 1;
COMP "VmeA_iob31<14>" LOCATE = SITE "G23" LEVEL 1;
COMP "VmeA_iob31<22>" LOCATE = SITE "D24" LEVEL 1;
COMP "VmeA_iob31<30>" LOCATE = SITE "M18" LEVEL 1;
COMP "VmeA_iob31<15>" LOCATE = SITE "F23" LEVEL 1;
COMP "VmeA_iob31<23>" LOCATE = SITE "N26" LEVEL 1;
COMP "VmeA_iob31<31>" LOCATE = SITE "M19" LEVEL 1;
COMP "VmeA_iob31<16>" LOCATE = SITE "F24" LEVEL 1;
COMP "VmeA_iob31<24>" LOCATE = SITE "K18" LEVEL 1;
COMP "VmeA_iob31<17>" LOCATE = SITE "F22" LEVEL 1;
COMP "VmeA_iob31<25>" LOCATE = SITE "J20" LEVEL 1;
COMP "VmeA_iob31<18>" LOCATE = SITE "E24" LEVEL 1;
COMP "VmeA_iob31<26>" LOCATE = SITE "K19" LEVEL 1;
COMP "VmeA_iob31<19>" LOCATE = SITE "E23" LEVEL 1;
COMP "VmeA_iob31<27>" LOCATE = SITE "K20" LEVEL 1;
COMP "VmeA_iob31<28>" LOCATE = SITE "L19" LEVEL 1;
COMP "VmeA_iob31<29>" LOCATE = SITE "L20" LEVEL 1;
COMP "DdrCkE_o" LOCATE = SITE "N21" LEVEL 1;
COMP "PllFmc2Ref1_ok" LOCATE = SITE "Y12" LEVEL 1;
COMP "DdrUDM_o" LOCATE = SITE "V23" LEVEL 1;
COMP "PllFmc2Sdo_i" LOCATE = SITE "V14" LEVEL 1;
COMP "VmeDs_inb2<1>" LOCATE = SITE "G20" LEVEL 1;
COMP "PllSysSdo_i" LOCATE = SITE "AF6" LEVEL 1;
COMP "VmeDs_inb2<2>" LOCATE = SITE "H20" LEVEL 1;
COMP "VmeIrq_ob7<1>" LOCATE = SITE "L7" LEVEL 1;
COMP "VmeIrq_ob7<2>" LOCATE = SITE "J7" LEVEL 1;
COMP "VmeIrq_ob7<3>" LOCATE = SITE "K7" LEVEL 1;
COMP "FlashSFpgaQ_i" LOCATE = SITE "AD23" LEVEL 1;
COMP "Fmc1SCl_ok" LOCATE = SITE "N1" LEVEL 1;
COMP "WRRateSelect_o" LOCATE = SITE "L4" LEVEL 1;
COMP "FpGpIo1OutputMode_o" LOCATE = SITE "C1" LEVEL 1;
COMP "VmeIrq_ob7<4>" LOCATE = SITE "M3" LEVEL 1;
COMP "VmeIrq_ob7<5>" LOCATE = SITE "M4" LEVEL 1;
COMP "VmeIrq_ob7<6>" LOCATE = SITE "N3" LEVEL 1;
COMP "VmeIrq_ob7<7>" LOCATE = SITE "M6" LEVEL 1;
COMP "DdsDrCtl_o" LOCATE = SITE "H12" LEVEL 1;
COMP "VmeD_iob32<10>" LOCATE = SITE "D26" LEVEL 1;
COMP "VmeD_iob32<11>" LOCATE = SITE "E25" LEVEL 1;
COMP "VmeD_iob32<12>" LOCATE = SITE "E26" LEVEL 1;
COMP "VmeD_iob32<20>" LOCATE = SITE "W19" LEVEL 1;
COMP "DdsRamSwpOvr_i" LOCATE = SITE "J11" LEVEL 1;
COMP "PcbRev_ib8<0>" LOCATE = SITE "AA1" LEVEL 1;
COMP "VmeD_iob32<13>" LOCATE = SITE "F26" LEVEL 1;
COMP "VmeD_iob32<21>" LOCATE = SITE "AB19" LEVEL 1;
COMP "PcbRev_ib8<1>" LOCATE = SITE "AA2" LEVEL 1;
COMP "VmeD_iob32<14>" LOCATE = SITE "G25" LEVEL 1;
COMP "VmeD_iob32<22>" LOCATE = SITE "AA19" LEVEL 1;
COMP "VmeD_iob32<30>" LOCATE = SITE "Y15" LEVEL 1;
COMP "PcbRev_ib8<2>" LOCATE = SITE "AB1" LEVEL 1;
COMP "VmeD_iob32<15>" LOCATE = SITE "G26" LEVEL 1;
COMP "VmeD_iob32<23>" LOCATE = SITE "W18" LEVEL 1;
COMP "VmeD_iob32<31>" LOCATE = SITE "W14" LEVEL 1;
COMP "PcbRev_ib8<3>" LOCATE = SITE "AC1" LEVEL 1;
COMP "VmeD_iob32<16>" LOCATE = SITE "H13" LEVEL 1;
COMP "VmeD_iob32<24>" LOCATE = SITE "Y17" LEVEL 1;
COMP "PcbRev_ib8<4>" LOCATE = SITE "AC2" LEVEL 1;
COMP "VmeD_iob32<17>" LOCATE = SITE "H15" LEVEL 1;
COMP "VmeD_iob32<25>" LOCATE = SITE "AA17" LEVEL 1;
COMP "PcbRev_ib8<5>" LOCATE = SITE "AD1" LEVEL 1;
COMP "VmeD_iob32<18>" LOCATE = SITE "J15" LEVEL 1;
COMP "VmeD_iob32<26>" LOCATE = SITE "W17" LEVEL 1;
COMP "DdsSyncIn_ok" LOCATE = SITE "B14" LEVEL 1;
COMP "PcbRev_ib8<6>" LOCATE = SITE "AE1" LEVEL 1;
COMP "VmeD_iob32<19>" LOCATE = SITE "W20" LEVEL 1;
COMP "VmeD_iob32<27>" LOCATE = SITE "W16" LEVEL 1;
COMP "PcbRev_ib8<7>" LOCATE = SITE "AE2" LEVEL 1;
COMP "VmeD_iob32<28>" LOCATE = SITE "AA16" LEVEL 1;
COMP "VmeD_iob32<29>" LOCATE = SITE "Y16" LEVEL 1;
COMP "DdsSDio_io" LOCATE = SITE "E12" LEVEL 1;
COMP "DdsProfile_ob3<0>" LOCATE = SITE "A4" LEVEL 1;
COMP "DdsProfile_ob3<1>" LOCATE = SITE "B4" LEVEL 1;
COMP "DdsProfile_ob3<2>" LOCATE = SITE "A3" LEVEL 1;
COMP "VmeADirVfcToVme_o" LOCATE = SITE "F20" LEVEL 1;
COMP "PllFmc1Status_i" LOCATE = SITE "AB9" LEVEL 1;
COMP "VmeWrite_in" LOCATE = SITE "E20" LEVEL 1;
COMP "DdsSyncClk_ik" LOCATE = SITE "E13" LEVEL 1;
COMP "Sfp2RateSelect" LOCATE = SITE "J4" LEVEL 1;
COMP "FpGpIo2OutputMode_o" LOCATE = SITE "C2" LEVEL 1;
COMP "DdrUDQS_ion" LOCATE = SITE "AC26" LEVEL 1;
COMP "Fmc2SCl_ok" LOCATE = SITE "M1" LEVEL 1;
COMP "VmeGaP_in" LOCATE = SITE "J25" LEVEL 1;
COMP "VmeRetry_on" LOCATE = SITE "G17" LEVEL 1;
COMP "WRModeDef0_i" LOCATE = SITE "L3" LEVEL 1;
COMP "WRModeDef1_i" LOCATE = SITE "K6" LEVEL 1;
COMP "VmeTrst_i" LOCATE = SITE "H26" LEVEL 1;
COMP "VAdcDin_o" LOCATE = SITE "Y9" LEVEL 1;
COMP "VmeSysReset_in" LOCATE = SITE "J16" LEVEL 1;
COMP "DdrCk_ok" LOCATE = SITE "R23" LEVEL 1;
COMP "DdsSDo_i" LOCATE = SITE "F12" LEVEL 1;
COMP "Sfp2TxDisable_o" LOCATE = SITE "G3" LEVEL 1;
COMP "FpLed_onb8<0>" LOCATE = SITE "P5" LEVEL 1;
COMP "VmeLword_io" LOCATE = SITE "M23" LEVEL 1;
COMP "FpLed_onb8<1>" LOCATE = SITE "R4" LEVEL 1;
COMP "PllDacDout_i" LOCATE = SITE "Y20" LEVEL 1;
COMP "FpLed_onb8<2>" LOCATE = SITE "R3" LEVEL 1;
COMP "FpLed_onb8<3>" LOCATE = SITE "P6" LEVEL 1;
COMP "FpLed_onb8<4>" LOCATE = SITE "R5" LEVEL 1;
COMP "VAdcCs_on" LOCATE = SITE "W7" LEVEL 1;
COMP "FpLed_onb8<5>" LOCATE = SITE "U3" LEVEL 1;
COMP "FpLed_onb8<6>" LOCATE = SITE "U4" LEVEL 1;
COMP "FpLed_onb8<7>" LOCATE = SITE "T4" LEVEL 1;
COMP "FlashSFpgaClk_ok" LOCATE = SITE "AE24" LEVEL 1;
COMP "Fmc1PGC2M_in" LOCATE = SITE "W1" LEVEL 1;
COMP "DdrBA_ob3<0>" LOCATE = SITE "R20" LEVEL 1;
COMP "DdrBA_ob3<1>" LOCATE = SITE "R21" LEVEL 1;
COMP "DdrBA_ob3<2>" LOCATE = SITE "R19" LEVEL 1;
COMP "PllDacLDac_on" LOCATE = SITE "AA22" LEVEL 1;
COMP "VmeP0HwLowByteOe_o" LOCATE = SITE "E16" LEVEL 1;
COMP "FpGpIo34OutputMode_o" LOCATE = SITE "B1" LEVEL 1;
COMP "PllDacSynch_on" LOCATE = SITE "AB22" LEVEL 1;
COMP "PllDdsLd_i" LOCATE = SITE "G2" LEVEL 1;
COMP "DdrA_ob14<10>" LOCATE = SITE "N23" LEVEL 1;
COMP "DdrA_ob14<11>" LOCATE = SITE "N20" LEVEL 1;
COMP "DdrA_ob14<12>" LOCATE = SITE "N22" LEVEL 1;
COMP "DdrA_ob14<13>" LOCATE = SITE "L23" LEVEL 1;
COMP "PllFmc2Reset_orn" LOCATE = SITE "U15" LEVEL 1;
COMP "VmeP0LvdsTClkIn_i" LOCATE = SITE "L10" LEVEL 1;
COMP "VmeP0BuslineOe_o" LOCATE = SITE "J13" LEVEL 1;
COMP "DdsSyncIn_okn" LOCATE = SITE "A14" LEVEL 1;
COMP "VmeP0BunchSelectOe_o" LOCATE = SITE "F15" LEVEL 1;
COMP "DdrReset_or" LOCATE = SITE "N19" LEVEL 1;
COMP "SysAppSlow_iob2<1>" LOCATE = SITE "AC4" LEVEL 1;
COMP "SysAppSlow_iob2<2>" LOCATE = SITE "T6" LEVEL 1;
COMP "DdsPllLock_i" LOCATE = SITE "G10" LEVEL 1;
COMP "DdsDrHold_o" LOCATE = SITE "G12" LEVEL 1;
COMP "VmeDtAck_on" LOCATE = SITE "N25" LEVEL 1;
COMP "Si57x_ik" LOCATE = SITE "B12" LEVEL 1;
COMP "Sfp2ModeDef0_i" LOCATE = SITE "H3" LEVEL 1;
COMP "Sfp2ModeDef1_i" LOCATE = SITE "H5" LEVEL 1;
COMP "Sfp2LoS_i" LOCATE = SITE "J3" LEVEL 1;
COMP "PllFmc1Ld_i" LOCATE = SITE "AA9" LEVEL 1;
COMP "PllFmc2Status_i" LOCATE = SITE "W12" LEVEL 1;
COMP "PllSysReset_orn" LOCATE = SITE "AE5" LEVEL 1;
COMP "VmeBerr_o" LOCATE = SITE "V18" LEVEL 1;
COMP "PllFmc2Ld_i" LOCATE = SITE "Y13" LEVEL 1;
COMP "VmeAOeN_oen" LOCATE = SITE "F19" LEVEL 1;
COMP "VAdjDin_o" LOCATE = SITE "J1" LEVEL 1;
COMP "WRTxFault_i" LOCATE = SITE "J5" LEVEL 1;
COMP "VmeGa_ib5n<0>" LOCATE = SITE "J26" LEVEL 1;
COMP "VmeGa_ib5n<1>" LOCATE = SITE "K26" LEVEL 1;
COMP "VmeGa_ib5n<2>" LOCATE = SITE "L25" LEVEL 1;
COMP "VmeGa_ib5n<3>" LOCATE = SITE "L26" LEVEL 1;
COMP "VmeGa_ib5n<4>" LOCATE = SITE "M26" LEVEL 1;
COMP "PllSysStatus_i" LOCATE = SITE "AB14" LEVEL 1;
COMP "PushButton_ion" LOCATE = SITE "AA7" LEVEL 1;
COMP "VAdjCs_on" LOCATE = SITE "H1" LEVEL 1;
COMP "PllFmc1Synch_on" LOCATE = SITE "AB7" LEVEL 1;
COMP "VmeDtAckOe_oe" LOCATE = SITE "J9" LEVEL 1;
COMP "AFpgaProgClk_io" LOCATE = SITE "AB3" LEVEL 1;
COMP "FlashAFpgaCs_on" LOCATE = SITE "AB17" LEVEL 1;
COMP "VmeP0LvdsBunchClkOut_o" LOCATE = SITE "AF15" LEVEL 1;
COMP "VmeAm_ib6<0>" LOCATE = SITE "G19" LEVEL 1;
COMP "VmeAm_ib6<1>" LOCATE = SITE "G16" LEVEL 1;
COMP "VmeAm_ib6<2>" LOCATE = SITE "H19" LEVEL 1;
COMP "VmeTdoOe_oe" LOCATE = SITE "K8" LEVEL 1;
COMP "PllFmc1SClk_ok" LOCATE = SITE "AA6" LEVEL 1;
COMP "VmeAm_ib6<3>" LOCATE = SITE "H18" LEVEL 1;
COMP "VmeAm_ib6<4>" LOCATE = SITE "H17" LEVEL 1;
COMP "VmeAm_ib6<5>" LOCATE = SITE "J17" LEVEL 1;
COMP "PllFmc1SDio_io" LOCATE = SITE "AD5" LEVEL 1;
COMP "Fmc2PGC2M_in" LOCATE = SITE "U2" LEVEL 1;
COMP "VmeDDirVfcToVme_o" LOCATE = SITE "L9" LEVEL 1;
COMP "DdsOsk_o" LOCATE = SITE "A5" LEVEL 1;
COMP "DdrCk_okn" LOCATE = SITE "R24" LEVEL 1;
COMP "DdsSClk_o" LOCATE = SITE "F11" LEVEL 1;
COMP "VmeSysClk_ik" LOCATE = SITE "L8" LEVEL 1;
PIN VmeSysClk_ik_pin<0> = BEL "VmeSysClk_ik" PINNAME PAD;
PIN "VmeSysClk_ik_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE;
COMP "AFpgaProgRdWr_io" LOCATE = SITE "Y5" LEVEL 1;
COMP "Sfp2TxFault_i" LOCATE = SITE "G4" LEVEL 1;
COMP "DdsMasterRst_or" LOCATE = SITE "H9" LEVEL 1;
COMP "DdrUDQS_io" LOCATE = SITE "AC25" LEVEL 1;
COMP "VmeP0HwLowByteDir_o" LOCATE = SITE "F16" LEVEL 1;
COMP "VmeD_iob32<0>" LOCATE = SITE "A22" LEVEL 1;
COMP "VmeD_iob32<1>" LOCATE = SITE "B22" LEVEL 1;
COMP "VmeD_iob32<2>" LOCATE = SITE "A23" LEVEL 1;
COMP "PllFmc1RefMon_i" LOCATE = SITE "AA10" LEVEL 1;
COMP "VmeD_iob32<3>" LOCATE = SITE "B23" LEVEL 1;
COMP "VmeD_iob32<4>" LOCATE = SITE "B24" LEVEL 1;
COMP "AFpgaProgD_iob8<0>" LOCATE = SITE "AB5" LEVEL 1;
COMP "VmeD_iob32<5>" LOCATE = SITE "A25" LEVEL 1;
COMP "AFpgaProgD_iob8<1>" LOCATE = SITE "Y3" LEVEL 1;
COMP "VmeD_iob32<6>" LOCATE = SITE "B25" LEVEL 1;
COMP "AFpgaProgD_iob8<2>" LOCATE = SITE "AA3" LEVEL 1;
COMP "VmeD_iob32<7>" LOCATE = SITE "B26" LEVEL 1;
COMP "AFpgaProgD_iob8<3>" LOCATE = SITE "V3" LEVEL 1;
COMP "VmeD_iob32<8>" LOCATE = SITE "C25" LEVEL 1;
COMP "AFpgaProgD_iob8<4>" LOCATE = SITE "U5" LEVEL 1;
COMP "VmeD_iob32<9>" LOCATE = SITE "C26" LEVEL 1;
COMP "PllFmc1RefSel_o" LOCATE = SITE "AA8" LEVEL 1;
COMP "AFpgaProgD_iob8<5>" LOCATE = SITE "W2" LEVEL 1;
COMP "AFpgaProgD_iob8<6>" LOCATE = SITE "V5" LEVEL 1;
COMP "AFpgaProgD_iob8<7>" LOCATE = SITE "W5" LEVEL 1;
COMP "PllDdsStatus_i" LOCATE = SITE "F1" LEVEL 1;
COMP "AFpgaProgCsi_io" LOCATE = SITE "AB4" LEVEL 1;
COMP "AFpgaProgInit_io" LOCATE = SITE "U8" LEVEL 1;
COMP "VmeP0LvdsBunchClkIn_i" LOCATE = SITE "AE15" LEVEL 1;
COMP "TempIdDQ_io" LOCATE = SITE "B2" LEVEL 1;
COMP "FlashSFpgaCs_on" LOCATE = SITE "AF3" LEVEL 1;
COMP "PllFmc2SClk_ok" LOCATE = SITE "V11" LEVEL 1;
COMP "DdsIoReset_or" LOCATE = SITE "G11" LEVEL 1;
COMP "PllFmc2SDio_io" LOCATE = SITE "V15" LEVEL 1;
COMP "VmeRetryOe_oe" LOCATE = SITE "F17" LEVEL 1;
COMP "DdrA_ob14<0>" LOCATE = SITE "P24" LEVEL 1;
COMP "PllSysSClk_ok" LOCATE = SITE "AA12" LEVEL 1;
COMP "DdrA_ob14<1>" LOCATE = SITE "P26" LEVEL 1;
COMP "DdrA_ob14<2>" LOCATE = SITE "P22" LEVEL 1;
COMP "DdrA_ob14<3>" LOCATE = SITE "T22" LEVEL 1;
COMP "DdrA_ob14<4>" LOCATE = SITE "N24" LEVEL 1;
COMP "PllSysSDio_io" LOCATE = SITE "AF5" LEVEL 1;
COMP "PllDdsReset_orn" LOCATE = SITE "E3" LEVEL 1;
COMP "DdrA_ob14<5>" LOCATE = SITE "U23" LEVEL 1;
COMP "DdrA_ob14<6>" LOCATE = SITE "U24" LEVEL 1;
COMP "DdrA_ob14<7>" LOCATE = SITE "P21" LEVEL 1;
COMP "DdrA_ob14<8>" LOCATE = SITE "P17" LEVEL 1;
COMP "DdrA_ob14<9>" LOCATE = SITE "P19" LEVEL 1;
COMP "VmeIackIn_in" LOCATE = SITE "W10" LEVEL 1;
COMP "VmeAs_in" LOCATE = SITE "M8" LEVEL 1;
COMP "DdrWe_o" LOCATE = SITE "R18" LEVEL 1;
COMP "VmeP0BuslineDir_o" LOCATE = SITE "J12" LEVEL 1;
COMP "VAdjSpi_o" LOCATE = SITE "K1" LEVEL 1;
COMP "PllDdsCs_on" LOCATE = SITE "D1" LEVEL 1;
COMP "PllDdsSClk_ok" LOCATE = SITE "E2" LEVEL 1;
COMP "VAdcDout_i" LOCATE = SITE "W9" LEVEL 1;
COMP "PllDdsSDio_io" LOCATE = SITE "E4" LEVEL 1;
COMP "DdsF_ob2<0>" LOCATE = SITE "B3" LEVEL 1;
COMP "DdsF_ob2<1>" LOCATE = SITE "A2" LEVEL 1;
COMP "DdsDrOver_i" LOCATE = SITE "G13" LEVEL 1;
COMP "PllFmc2Synch_on" LOCATE = SITE "V12" LEVEL 1;
COMP "DdsTxEnable_o" LOCATE = SITE "G8" LEVEL 1;
COMP "Si57xOe_o" LOCATE = SITE "E18" LEVEL 1;
COMP "VmeP0BunchSelectDir_o" LOCATE = SITE "G15" LEVEL 1;
COMP "VAdjSClk_ok" LOCATE = SITE "J2" LEVEL 1;
COMP "PllDacClrn_orn" LOCATE = SITE "Y21" LEVEL 1;
COMP "PllSysSynch_on" LOCATE = SITE "AA13" LEVEL 1;
COMP "FlashAFpgaD_o" LOCATE = SITE "AF22" LEVEL 1;
COMP "PllDdsPd_on" LOCATE = SITE "F3" LEVEL 1;
COMP "AFpgaProgM_iob2<0>" LOCATE = SITE "AD3" LEVEL 1;
COMP "AFpgaProgM_iob2<1>" LOCATE = SITE "AA4" LEVEL 1;
COMP "DdrCAS_o" LOCATE = SITE "R26" LEVEL 1;
COMP "PllFmc2RefMon_i" LOCATE = SITE "Y11" LEVEL 1;
COMP "VmeDOeN_oen" LOCATE = SITE "K9" LEVEL 1;
COMP "ManualAddress_ib5<0>" LOCATE = SITE "R8" LEVEL 1;
COMP "DdsPowerDown_o" LOCATE = SITE "H10" LEVEL 1;
COMP "ManualAddress_ib5<1>" LOCATE = SITE "T8" LEVEL 1;
COMP "DdsPdClk_ik" LOCATE = SITE "D13" LEVEL 1;
COMP "ManualAddress_ib5<2>" LOCATE = SITE "R9" LEVEL 1;
COMP "SysAppClk_ik" LOCATE = SITE "R6" LEVEL 1;
COMP "ManualAddress_ib5<3>" LOCATE = SITE "T9" LEVEL 1;
COMP "Si57xSCl_ok" LOCATE = SITE "F14" LEVEL 1;
COMP "WRTxDisable_o" LOCATE = SITE "K5" LEVEL 1;
COMP "ManualAddress_ib5<4>" LOCATE = SITE "P10" LEVEL 1;
COMP "PllFmc2RefSel_o" LOCATE = SITE "V13" LEVEL 1;
COMP "FlashAFpgaQ_i" LOCATE = SITE "AA18" LEVEL 1;
COMP "PllFmc1Reset_orn" LOCATE = SITE "AC5" LEVEL 1;
COMP "VcTcXo_ik" LOCATE = SITE "AF14" LEVEL 1;
COMP "SysAppClk_ok" LOCATE = SITE "R7" LEVEL 1;
COMP "WRLoS_i" LOCATE = SITE "L6" LEVEL 1;
COMP "PllSysRefMon_i" LOCATE = SITE "AD14" LEVEL 1;
COMP "VmeIackOut_on" LOCATE = SITE "V10" LEVEL 1;
COMP "DdsSyncSmpErr_i" LOCATE = SITE "H8" LEVEL 1;
COMP "PllSysRefSel_o" LOCATE = SITE "AB13" LEVEL 1;
COMP "VAdcSClk_ok" LOCATE = SITE "W8" LEVEL 1;
COMP "PllDdsSdo_i" LOCATE = SITE "D3" LEVEL 1;
COMP "VmeP0HwHighByteDir_o" LOCATE = SITE "H14" LEVEL 1;
COMP "VmeTdi_i" LOCATE = SITE "C21" LEVEL 1;
COMP "VmeTck_i" LOCATE = SITE "D22" LEVEL 1;
COMP "PllSysRef12_okn" LOCATE = SITE "AB15" LEVEL 1;
COMP "DdsD_ob16<10>" LOCATE = SITE "D5" LEVEL 1;
COMP "DdsD_ob16<11>" LOCATE = SITE "E5" LEVEL 1;
COMP "PllDdsSynch_on" LOCATE = SITE "E1" LEVEL 1;
COMP "DdsD_ob16<12>" LOCATE = SITE "F5" LEVEL 1;
COMP "DdsD_ob16<13>" LOCATE = SITE "G6" LEVEL 1;
COMP "DdsD_ob16<14>" LOCATE = SITE "C3" LEVEL 1;
COMP "PllSysRef12_ok" LOCATE = SITE "AA15" LEVEL 1;
COMP "Si57x_ikn" LOCATE = SITE "A12" LEVEL 1;
COMP "DdsD_ob16<15>" LOCATE = SITE "K12" LEVEL 1;
COMP "UseGa_i" LOCATE = SITE "R10" LEVEL 1;
COMP "PllFmc1Cs_on" LOCATE = SITE "AD6" LEVEL 1;
COMP "VmeTdo_o" LOCATE = SITE "B21" LEVEL 1;
COMP "PllDacSClk_ok" LOCATE = SITE "AA21" LEVEL 1;
COMP "Switch_ib2<0>" LOCATE = SITE "V6" LEVEL 1;
COMP "Switch_ib2<1>" LOCATE = SITE "V7" LEVEL 1;
COMP "PllSysLd_i" LOCATE = SITE "AC14" LEVEL 1;
COMP "DdsD_ob16<0>" LOCATE = SITE "F10" LEVEL 1;
COMP "DdsD_ob16<1>" LOCATE = SITE "F9" LEVEL 1;
COMP "PllFmc2Cs_on" LOCATE = SITE "U13" LEVEL 1;
COMP "DdsD_ob16<2>" LOCATE = SITE "G9" LEVEL 1;
COMP "DdsD_ob16<3>" LOCATE = SITE "E8" LEVEL 1;
COMP "VmeP0HwHighByteOe_o" LOCATE = SITE "K14" LEVEL 1;
COMP "DdsD_ob16<4>" LOCATE = SITE "F7" LEVEL 1;
COMP "PllSysCs_on" LOCATE = SITE "AB11" LEVEL 1;
COMP "DdsD_ob16<5>" LOCATE = SITE "G7" LEVEL 1;
COMP "VmeIack_in" LOCATE = SITE "F18" LEVEL 1;
COMP "DdsD_ob16<6>" LOCATE = SITE "E6" LEVEL 1;
COMP "DdsD_ob16<7>" LOCATE = SITE "F6" LEVEL 1;
COMP "DdsD_ob16<8>" LOCATE = SITE "E10" LEVEL 1;
COMP "DdrLDM_o" LOCATE = SITE "W24" LEVEL 1;
COMP "DdsD_ob16<9>" LOCATE = SITE "C5" LEVEL 1;
COMP "Fmc1PrsntM2C_in" LOCATE = SITE "V1" LEVEL 1;
COMP "PllFmc1Ref1_ok" LOCATE = SITE "AA11" LEVEL 1;
COMP "PllDdsRefMon_i" LOCATE = SITE "G1" LEVEL 1;
COMP "DdrLDQS_io" LOCATE = SITE "V24" LEVEL 1;
COMP "PllDacDin_o" LOCATE = SITE "AB21" LEVEL 1;
COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
"i_Core/Si57xDivider_c_14" BEL "i_Core/Si57xDivider_c_13" BEL
"i_Core/Si57xDivider_c_12" BEL "i_Core/Si57xDivider_c_11" BEL
"i_Core/Si57xDivider_c_10" BEL "i_Core/Si57xDivider_c_9" BEL
"i_Core/Si57xDivider_c_8" BEL "i_Core/Si57xDivider_c_7" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "i_Core/Rst_rq" BEL
"i_Core/i_VmeInterface/state_FSM_FFd2" BEL
"i_Core/i_VmeInterface/stb_d" BEL "i_Core/i_VmeInterface/adr_o_21" BEL
"i_Core/i_VmeInterface/adr_o_20" BEL "i_Core/i_VmeInterface/adr_o_19"
BEL "i_Core/i_VmeInterface/adr_o_18" BEL
"i_Core/i_VmeInterface/adr_o_17" BEL "i_Core/i_VmeInterface/adr_o_16"
BEL "i_Core/i_VmeInterface/adr_o_15" BEL
"i_Core/i_VmeInterface/adr_o_14" BEL "i_Core/i_VmeInterface/adr_o_13"
BEL "i_Core/i_VmeInterface/adr_o_12" BEL
"i_Core/i_VmeInterface/adr_o_11" BEL "i_Core/i_VmeInterface/adr_o_10"
BEL "i_Core/i_VmeInterface/adr_o_9" BEL
"i_Core/i_VmeInterface/adr_o_8" BEL "i_Core/i_VmeInterface/adr_o_7"
BEL "i_Core/i_VmeInterface/adr_o_6" BEL
"i_Core/i_VmeInterface/adr_o_5" BEL "i_Core/i_VmeInterface/adr_o_4"
BEL "i_Core/i_VmeInterface/adr_o_3" BEL
"i_Core/i_VmeInterface/adr_o_2" BEL "i_Core/i_VmeInterface/adr_o_1"
BEL "i_Core/i_VmeInterface/adr_o_0" BEL
"i_Core/i_VmeInterface/vme_dtack" BEL "i_Core/i_VmeInterface/VmeDOe_o"
BEL "i_Core/i_VmeInterface/dat_o_31" BEL
"i_Core/i_VmeInterface/dat_o_30" BEL "i_Core/i_VmeInterface/dat_o_29"
BEL "i_Core/i_VmeInterface/dat_o_28" BEL
"i_Core/i_VmeInterface/dat_o_27" BEL "i_Core/i_VmeInterface/dat_o_26"
BEL "i_Core/i_VmeInterface/dat_o_25" BEL
"i_Core/i_VmeInterface/dat_o_24" BEL "i_Core/i_VmeInterface/dat_o_23"
BEL "i_Core/i_VmeInterface/dat_o_22" BEL
"i_Core/i_VmeInterface/dat_o_21" BEL "i_Core/i_VmeInterface/dat_o_20"
BEL "i_Core/i_VmeInterface/dat_o_19" BEL
"i_Core/i_VmeInterface/dat_o_18" BEL "i_Core/i_VmeInterface/dat_o_17"
BEL "i_Core/i_VmeInterface/dat_o_16" BEL
"i_Core/i_VmeInterface/dat_o_15" BEL "i_Core/i_VmeInterface/dat_o_14"
BEL "i_Core/i_VmeInterface/dat_o_13" BEL
"i_Core/i_VmeInterface/dat_o_12" BEL "i_Core/i_VmeInterface/dat_o_11"
BEL "i_Core/i_VmeInterface/dat_o_10" BEL
"i_Core/i_VmeInterface/dat_o_9" BEL "i_Core/i_VmeInterface/dat_o_8"
BEL "i_Core/i_VmeInterface/dat_o_7" BEL
"i_Core/i_VmeInterface/dat_o_6" BEL "i_Core/i_VmeInterface/dat_o_5"
BEL "i_Core/i_VmeInterface/dat_o_4" BEL
"i_Core/i_VmeInterface/dat_o_3" BEL "i_Core/i_VmeInterface/dat_o_2"
BEL "i_Core/i_VmeInterface/dat_o_1" BEL
"i_Core/i_VmeInterface/dat_o_0" BEL "i_Core/i_VmeInterface/vme_irqn_7"
BEL "i_Core/i_VmeInterface/vme_irqn_6" BEL
"i_Core/i_VmeInterface/vme_irqn_5" BEL
"i_Core/i_VmeInterface/vme_irqn_4" BEL
"i_Core/i_VmeInterface/vme_irqn_3" BEL
"i_Core/i_VmeInterface/vme_irqn_2" BEL
"i_Core/i_VmeInterface/vme_irqn_1" BEL
"i_Core/i_VmeInterface/as_shr_1" BEL "i_Core/i_VmeInterface/as_shr_0"
BEL "i_Core/i_VmeInterface/VmeBaseAddr_7" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_6" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_5" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_4" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_3" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_2" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_1" BEL
"i_Core/i_VmeInterface/VmeBaseAddr_0" BEL
"i_Core/i_VmeInterface/VmeDDirFpgaToVme_o" BEL
"i_Core/i_VmeInterface/SendIrqVector" BEL
"i_Core/i_VmeInterface/clear_int" BEL "i_Core/i_VmeInterface/we_o" BEL
"i_Core/i_VmeInterface/ack_d" BEL "i_Core/i_VmeInterface/oe_vme_data"
BEL "i_Core/i_VmeInterface/DataReg_31" BEL
"i_Core/i_VmeInterface/DataReg_30" BEL
"i_Core/i_VmeInterface/DataReg_29" BEL
"i_Core/i_VmeInterface/DataReg_28" BEL
"i_Core/i_VmeInterface/DataReg_27" BEL
"i_Core/i_VmeInterface/DataReg_26" BEL
"i_Core/i_VmeInterface/DataReg_25" BEL
"i_Core/i_VmeInterface/DataReg_24" BEL
"i_Core/i_VmeInterface/DataReg_23" BEL
"i_Core/i_VmeInterface/DataReg_22" BEL
"i_Core/i_VmeInterface/DataReg_21" BEL
"i_Core/i_VmeInterface/DataReg_20" BEL
"i_Core/i_VmeInterface/DataReg_19" BEL
"i_Core/i_VmeInterface/DataReg_18" BEL
"i_Core/i_VmeInterface/DataReg_17" BEL
"i_Core/i_VmeInterface/DataReg_16" BEL
"i_Core/i_VmeInterface/DataReg_15" BEL
"i_Core/i_VmeInterface/DataReg_14" BEL
"i_Core/i_VmeInterface/DataReg_13" BEL
"i_Core/i_VmeInterface/DataReg_12" BEL
"i_Core/i_VmeInterface/DataReg_11" BEL
"i_Core/i_VmeInterface/DataReg_10" BEL
"i_Core/i_VmeInterface/DataReg_9" BEL
"i_Core/i_VmeInterface/DataReg_8" BEL
"i_Core/i_VmeInterface/DataReg_7" BEL
"i_Core/i_VmeInterface/DataReg_6" BEL
"i_Core/i_VmeInterface/DataReg_5" BEL
"i_Core/i_VmeInterface/DataReg_4" BEL
"i_Core/i_VmeInterface/DataReg_3" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_19" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_18" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_17" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_16" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_15" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_14" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_13" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_12" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_11" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_10" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_9" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_8" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_7" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_6" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_5" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_4" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_3" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_2" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_1" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_0" BEL
"i_Core/i_ClearMonostable/Counter_c_19" BEL
"i_Core/i_ClearMonostable/Counter_c_18" BEL
"i_Core/i_ClearMonostable/Counter_c_17" BEL
"i_Core/i_ClearMonostable/Counter_c_16" BEL
"i_Core/i_ClearMonostable/Counter_c_15" BEL
"i_Core/i_ClearMonostable/Counter_c_14" BEL
"i_Core/i_ClearMonostable/Counter_c_13" BEL
"i_Core/i_ClearMonostable/Counter_c_12" BEL
"i_Core/i_ClearMonostable/Counter_c_11" BEL
"i_Core/i_ClearMonostable/Counter_c_10" BEL
"i_Core/i_ClearMonostable/Counter_c_9" BEL
"i_Core/i_ClearMonostable/Counter_c_8" BEL
"i_Core/i_ClearMonostable/Counter_c_7" BEL
"i_Core/i_ClearMonostable/Counter_c_6" BEL
"i_Core/i_ClearMonostable/Counter_c_5" BEL
"i_Core/i_ClearMonostable/Counter_c_4" BEL
"i_Core/i_ClearMonostable/Counter_c_3" BEL
"i_Core/i_ClearMonostable/Counter_c_2" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_2" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_1" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_0" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL
"i_Core/i_Debouncer/Counter_c_12" BEL
"i_Core/i_Debouncer/Counter_c_11" BEL
"i_Core/i_Debouncer/Counter_c_10" BEL "i_Core/i_Debouncer/Counter_c_9"
BEL "i_Core/i_Debouncer/Counter_c_8" BEL
"i_Core/i_Debouncer/Counter_c_7" BEL "i_Core/i_Debouncer/Counter_c_6"
BEL "i_Core/i_Debouncer/Counter_c_5" BEL
"i_Core/i_Debouncer/Counter_c_4" BEL "i_Core/i_Debouncer/Counter_c_3"
BEL "i_Core/i_Debouncer/Counter_c_2" BEL
"i_Core/i_Debouncer/Counter_c_1" BEL "i_Core/i_Debouncer/Counter_c_0"
BEL "i_Core/i_InterruptManager/int_pointer_w_2" BEL
"i_Core/i_InterruptManager/int_pointer_w_1" BEL
"i_Core/i_InterruptManager/int_pointer_w_0" BEL
"i_Core/i_InterruptManager/int_pointer_r_2" BEL
"i_Core/i_InterruptManager/int_pointer_r_1" BEL
"i_Core/i_InterruptManager/int_pointer_r_0" BEL
"i_Core/i_InterruptManager/int_counter_3" BEL
"i_Core/i_InterruptManager/int_counter_2" BEL
"i_Core/i_InterruptManager/int_counter_1" BEL
"i_Core/i_InterruptManager/int_counter_0" BEL
"i_Core/i_InterruptManager/osc_clk" BEL
"i_Core/i_InterruptManager/mask_reg_7" BEL
"i_Core/i_InterruptManager/mask_reg_6" BEL
"i_Core/i_InterruptManager/mask_reg_5" BEL
"i_Core/i_InterruptManager/mask_reg_4" BEL
"i_Core/i_InterruptManager/mask_reg_3" BEL
"i_Core/i_InterruptManager/mask_reg_2" BEL
"i_Core/i_InterruptManager/mask_reg_1" BEL
"i_Core/i_InterruptManager/mask_reg_0" BEL
"i_Core/i_InterruptManager/hs_int_mode" BEL
"i_Core/i_InterruptManager/int_masked_old_7" BEL
"i_Core/i_InterruptManager/int_masked_old_6" BEL
"i_Core/i_InterruptManager/int_masked_old_5" BEL
"i_Core/i_InterruptManager/int_masked_old_4" BEL
"i_Core/i_InterruptManager/int_masked_old_3" BEL
"i_Core/i_InterruptManager/int_masked_old_2" BEL
"i_Core/i_InterruptManager/int_masked_old_1" BEL
"i_Core/i_InterruptManager/int_masked_old_0" BEL
"i_Core/i_InterruptManager/Stb_d" BEL
"i_Core/i_InterruptManager/rora_roak" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_0" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_31" BEL "i_Core/i_Slv2SerWB/Dat_ob32_30"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_29" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_28" BEL "i_Core/i_Slv2SerWB/Dat_ob32_27"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_26" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_25" BEL "i_Core/i_Slv2SerWB/Dat_ob32_24"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_23" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_22" BEL "i_Core/i_Slv2SerWB/Dat_ob32_21"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_20" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_19" BEL "i_Core/i_Slv2SerWB/Dat_ob32_18"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_17" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_16" BEL "i_Core/i_Slv2SerWB/Dat_ob32_15"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_14" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_13" BEL "i_Core/i_Slv2SerWB/Dat_ob32_12"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_11" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_10" BEL "i_Core/i_Slv2SerWB/Dat_ob32_9"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_8" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_7" BEL "i_Core/i_Slv2SerWB/Dat_ob32_6"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_5" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_4" BEL "i_Core/i_Slv2SerWB/Dat_ob32_3"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_2" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_1" BEL "i_Core/i_Slv2SerWB/Dat_ob32_0"
BEL "i_Core/i_Slv2SerWB/Ack_o" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_0" BEL "i_Core/i_Slv2SerWB/StbI_d"
BEL "i_Core/i_Slv2SerWB/DatOutShReg_b32_31" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_0" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd2" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd3" BEL
"i_Core/i_SpiMasterWB/WriteAck_q" BEL
"i_Core/i_SpiMasterWB/WaitingNewData_o" BEL
"i_Core/i_SpiMasterWB/ModuleIdle_o" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_15" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_14" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_13" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_12" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_11" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_10" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_9" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_8" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_7" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_6" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_5" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_4" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_3" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_2" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_1" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_0" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_11" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_10" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_9" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_8" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_7" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_6" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_5" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_4" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_3" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_2" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_1" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_0" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_31" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_30" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_29" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_28" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_27" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_26" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_25" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_24" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_23" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_22" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_21" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_20" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_19" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_18" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_17" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_16" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_15" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_14" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_13" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_12" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_11" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_10" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_9" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_8" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_7" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_6" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_5" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_4" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_3" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_2" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_1" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_0" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_31" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_30" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_29" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_28" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_27" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_26" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_25" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_24" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_23" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_22" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_21" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_20" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_19" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_18" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_17" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_16" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_15" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_14" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_13" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_12" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_11" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_10" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_9" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_8" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_7" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_6" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_5" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_4" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_3" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_2" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_1" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_0" BEL
"i_Core/i_InterruptManager/fifo_full" BEL
"i_Core/i_VmeInterface/cyc_o" BEL "i_Core/i_VmeInterface/stb_o" BEL
"i_Core/i_VmeInterface/vme_iack_outn" BEL
"i_Core/i_SpiMasterWB/SClk_o" BEL "i_Core/i_SpiMasterWB/SS_onb32_1"
BEL "i_Core/i_SpiMasterWB/SS_onb32_2" BEL
"i_Core/i_SpiMasterWB/SS_onb32_0" BEL
"i_Core/i_SpiMasterWB/SS_onb32_4" BEL
"i_Core/i_SpiMasterWB/SS_onb32_5" BEL
"i_Core/i_SpiMasterWB/SS_onb32_3" BEL
"i_Core/i_SpiMasterWB/SS_onb32_6" BEL
"i_Core/i_SpiMasterWB/SS_onb32_7" BEL
"i_Core/i_SpiMasterWB/SS_onb32_8" BEL
"i_Core/i_VmeInterface/state_FSM_FFd1" BEL
"i_Core/i_VmeAccessMonostable/SynchOutput_oq" BEL
"i_Core/i_ClearMonostable/SynchOutput_oq" BEL
"i_Core/i_Debouncer/DebouncedSignal_oq" BEL
"i_Core/i_Debouncer/State_q" BEL "i_Core/i_InterruptManager/ready4int"
BEL "i_Core/i_InterruptManager/fifo_empty" BEL
"i_Core/i_SpiMasterWB/StartTx_q" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_31" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_30" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_29" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_28" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_27" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_26" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_25" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_24" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_23" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_22" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_21" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_20" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_19" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_18" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_17" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_16" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_15" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_14" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_13" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_12" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_11" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_10" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_9" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_8" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_7" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_6" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_5" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_4" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_3" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_2" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_1" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_0" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_31" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_30" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_29" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_28" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_27" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_26" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_25" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_24" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_23" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_22" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_21" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_20" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_19" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_18" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_17" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_16" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_15" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_14" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_13" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_12" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_11" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_10" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_9" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_8" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_7" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_6" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_5" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_4" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_3" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_2" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_1" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_0" BEL
"i_Core/i_VmeInterface/adr_o_3_1" BEL
"i_Core/i_VmeInterface/adr_o_21_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_7" BEL
"i_Core/i_VmeInterface/AckTimeout_c_6" BEL
"i_Core/i_VmeInterface/AckTimeout_c_8" BEL
"i_Core/i_VmeInterface/AckTimeout_c_5" BEL
"i_Core/i_VmeInterface/AckTimeout_c_4" BEL
"i_Core/i_VmeInterface/AckTimeout_c_2" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "i_Core/Mshreg_VmeSysReset_dx_1"
BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/SP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo22/DP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo22/SP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMA" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMB_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMB" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
SCHEMATIC END;
trunk/firmware/XilinxISE/SystemFpga/SFpga.prj 0 → 100644
View file @ 23b1b4b5
verilog work "../../../hdl/design/VmeInterfaceWB.v"
verilog work "../../../hdl/design/SpiMasterWB.v"
verilog work "../../../hdl/design/Slv2SerWB.v"
verilog work "../../../hdl/design/Monostable.v"
verilog work "../../../hdl/design/InterruptManagerWB.v"
verilog work "../../../hdl/design/Generic4OutputRegs.v"
verilog work "../../../hdl/design/Generic4InputRegs.v"
verilog work "../../../hdl/design/Debouncer.v"
verilog work "../../../hdl/design/AddrDecoderWBSys.v"
verilog work "../../../hdl/design/SystemFpga.v"
verilog work "../../../hdl/design/XilinxWrappers/SFpga.v"
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.189" best="8.144" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.321" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.syr 0 → 100644
View file @ 23b1b4b5
Release 12.3 - xst M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.16 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs
--> Reading design: SFpga.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "SFpga.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "SFpga"
Output Format : NGC
Target Device : xc6slx150t-3-fgg676
---- Source Options
Top Module Name : SFpga
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/VmeInterfaceWB.v\" into library work
Parsing module <VmeInterfaceWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SpiMasterWB.v\" into library work
Parsing module <SpiMasterWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Slv2SerWB.v\" into library work
Parsing module <Slv2SerWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Monostable.v\" into library work
Parsing module <Monostable>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/InterruptManagerWB.v\" into library work
Parsing module <InterruptManagerWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Generic4OutputRegs.v\" into library work
Parsing module <Generic4OutputRegs>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Generic4InputRegs.v\" into library work
Parsing module <Generic4InputRegs>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Debouncer.v\" into library work
Parsing module <Debouncer>.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Debouncer.v" Line 14: Macro <dly> is redefined.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Debouncer.v" Line 21: Macro <s_Idle> is redefined.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/AddrDecoderWBSys.v\" into library work
Parsing module <AddressDecoderWBSys>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v\" into library work
Parsing module <SystemFpga>.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro <dly> is redefined.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v\" into library work
Parsing module <SFpga>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating module <SFpga>.
WARNING:HDLCompiler:1016 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 485: Port osc_clk is not connected to this instance
Elaborating module <SystemFpga>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 325: Assignment to DdrLDQS_io ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 326: Assignment to DdrUDQS_io ignored, since the identifier is never used
Elaborating module <Monostable>.
Elaborating module <Debouncer(g_CounterWidth=16,g_SynchDepth=3)>.
Elaborating module <VmeInterfaceWB>.
Elaborating module <InterruptManagerWB>.
Elaborating module <AddressDecoderWBSys>.
Elaborating module <Generic4OutputRegs(Reg2Default=32'b01000100010001000)>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 546: Assignment to GenericOutputReg3 ignored, since the identifier is never used
Elaborating module <Generic4InputRegs>.
Elaborating module <Slv2SerWB>.
Elaborating module <SpiMasterWB>.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net <GenericInputReg1[31]> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 273: Net <SpiMiSo_b32[30]> does not have a driver.
WARNING:HDLCompiler:189 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Size mismatch in connection of port <VmeDs_inb2>. Formal port size is 2-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 439: Assignment to WRGBitOut_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 442: Assignment to Sfp2GBitOut_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 444: Assignment to SataTx_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 446: Assignment to Gbit1Sys2App_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 448: Assignment to Gbit2Sys2App_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 451: Assignment to Gbit3Sys2App_o ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 453: Assignment to Gbit4Sys2App_o ignored, since the identifier is never used
Elaborating module <IBUFGDS(DIFF_TERM="TRUE",IOSTANDARD="DEFAULT")>.
Elaborating module <OBUFDS(IOSTANDARD="DEFAULT")>.
Elaborating module <IOBUFDS(IOSTANDARD="DEFAULT")>.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Net <VmeDs_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 440: Net <WRGbitIn_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 441: Net <WRRefClk_ik> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 443: Net <Sfp2GbitIn_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 445: Net <SataRx_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 447: Net <Gbit1App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 449: Net <Gbit2App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 450: Net <Gbit12RefClk_ik> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 452: Net <Gbit3App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 454: Net <Gbit4App2Sys_i> does not have a driver.
WARNING:HDLCompiler:634 - "\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 455: Net <Gbit34RefClk_ik> does not have a driver.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <SFpga>.
Related source file is "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v".
WARNING:Xst:647 - Input <VmeDs_inb2<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <WRGBitOut_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Sfp2GBitOut_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <SataTx_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit1Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit2Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit3Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/xilinxwrappers/sfpga.v" line 233: Output port <Gbit4Sys2App_o> of the instance <i_Core> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <VmeDs_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WRGbitIn_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WRRefClk_ik> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Sfp2GbitIn_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <SataRx_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit1App2Sys_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit2App2Sys_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit12RefClk_ik> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit3App2Sys_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit4App2Sys_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit34RefClk_ik> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Summary:
no macro.
Unit <SFpga> synthesized.
Synthesizing Unit <SystemFpga>.
Related source file is "/vfc_svn/hdl/design/systemfpga.v".
WARNING:Xst:647 - Input <PcbRev_ib8<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTck_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTrst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTdi_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTms_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllFmc12SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllFmc22SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllSys2SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllDds2SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllDacDout_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsSyncSmpErr_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsPllLock_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsSDo_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsRamSwpOvr_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsDrOver_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsSyncClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsPdClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdsSyncOut_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeP0LvdsBunchClkIn_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeP0LvdsTClkIn_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdrLDQS_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DdrUDQS_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRModeDef0_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRTxFault_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRLoS_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sfp2ModeDef0_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sfp2LoS_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sfp2TxFault_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Fmc1PrsntM2C_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Fmc2PrsntM2C_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRGbitIn_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRRefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sfp2GbitIn_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SataRx_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit1App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit2App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit12RefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit3App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit4App2Sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Gbit34RefClk_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 485: Output port <osc_clk> of the instance <i_InterruptManager> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/systemfpga.v" line 533: Output port <Reg3Value_ob32> of the instance <i_Generic4OutputRegs> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <GenericInputReg1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg2> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <GenericInputReg3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <SpiMiSo_b32<30:9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WRGBitOut_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Sfp2GBitOut_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <SataTx_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit1Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit2Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit3Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 22-bit register for signal <VcTcXoDivider_c>.
Found 22-bit register for signal <VmeSysClkDivider_c>.
Found 2-bit register for signal <VmeSysReset_dx>.
Found 1-bit register for signal <Rst_rq>.
Found 22-bit register for signal <Si57xDivider_c>.
Found 22-bit adder for signal <Si57xDivider_c[21]_GND_2_o_add_9_OUT> created at line 380.
Found 22-bit adder for signal <VcTcXoDivider_c[21]_GND_2_o_add_12_OUT> created at line 383.
Found 22-bit adder for signal <VmeSysClkDivider_c[21]_GND_2_o_add_15_OUT> created at line 386.
Found 1-bit 4-to-1 multiplexer for signal <a_FpLed7> created at line 388.
Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 296
Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 300
Found 1-bit tristate buffer for signal <Fmc1SDa_io> created at line 305
Found 1-bit tristate buffer for signal <Fmc2SDa_io> created at line 307
Found 1-bit tristate buffer for signal <DdrDQ_iob16<15>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<14>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<13>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<12>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<11>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<10>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<9>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<8>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<7>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<6>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<5>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<4>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<3>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<2>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<1>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315
Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338
Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 374
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 375
Found 1-bit tristate buffer for signal <FpLed_onb8<2>> created at line 376
Found 1-bit tristate buffer for signal <FpLed_onb8<3>> created at line 377
Found 1-bit tristate buffer for signal <FpLed_onb8<4>> created at line 395
Found 1-bit tristate buffer for signal <FpLed_onb8<5>> created at line 396
Found 1-bit tristate buffer for signal <FpLed_onb8<6>> created at line 397
Found 1-bit tristate buffer for signal <FpLed_onb8<7>> created at line 398
Found 1-bit tristate buffer for signal <AFpgaProgDone_io> created at line 586
Found 1-bit tristate buffer for signal <AFpgaProgProgram_o> created at line 587
Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 634
Summary:
inferred 3 Adder/Subtractor(s).
inferred 69 D-type flip-flop(s).
inferred 1 Multiplexer(s).
inferred 33 Tristate(s).
Unit <SystemFpga> synthesized.
Synthesizing Unit <Monostable>.
Related source file is "/vfc_svn/hdl/design/monostable.v".
g_CounterBits = 20
Found 3-bit register for signal <AsynchInAX_db3>.
Found 20-bit register for signal <Counter_c>.
Found 1-bit register for signal <SynchOutput_oq>.
Found 1-bit register for signal <AsynchIn_ax>.
Found 20-bit adder for signal <Counter_c[19]_GND_25_o_add_6_OUT> created at line 20.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 25 D-type flip-flop(s).
Unit <Monostable> synthesized.
Synthesizing Unit <Debouncer>.
Related source file is "/vfc_svn/hdl/design/debouncer.v".
g_CounterWidth = 16
g_SynchDepth = 3
Found 1-bit register for signal <State_q>.
Found 16-bit register for signal <Counter_c>.
Found 1-bit register for signal <DebouncedSignal_oq>.
Found 3-bit register for signal <BouncingSignal_x>.
Found 16-bit adder for signal <Counter_c[15]_GND_34_o_add_7_OUT> created at line 38.
Found 1-bit comparator equal for signal <n0003> created at line 31
Summary:
inferred 1 Adder/Subtractor(s).
inferred 21 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <Debouncer> synthesized.
Synthesizing Unit <VmeInterfaceWB>.
Related source file is "/vfc_svn/hdl/design/vmeinterfacewb.v".
dly = 1
s_idle = 3'b000
s_read = 3'b001
s_write = 3'b010
s_ack_int = 3'b011
Found 1-bit register for signal <ack_d>.
Found 1-bit register for signal <stb_d>.
Found 9-bit register for signal <AckTimeout_c>.
Found 32-bit register for signal <DataReg>.
Found 2-bit register for signal <as_shr>.
Found 2-bit register for signal <ds1_shr>.
Found 2-bit register for signal <ds2_shr>.
Found 7-bit register for signal <vme_irqn>.
Found 3-bit register for signal <state>.
Found 1-bit register for signal <oe_vme_data>.
Found 1-bit register for signal <vme_dtack>.
Found 1-bit register for signal <vme_iack_outn>.
Found 1-bit register for signal <clear_int>.
Found 1-bit register for signal <VmeDOe_o>.
Found 1-bit register for signal <VmeDDirFpgaToVme_o>.
Found 1-bit register for signal <SendIrqVector>.
Found 22-bit register for signal <adr_o>.
Found 32-bit register for signal <dat_o>.
Found 1-bit register for signal <we_o>.
Found 1-bit register for signal <stb_o>.
Found 1-bit register for signal <cyc_o>.
Found 8-bit register for signal <VmeBaseAddr>.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 50 |
| Inputs | 12 |
| Outputs | 6 |
| Clock | clk_i (rising_edge) |
| Reset | rst_i (positive) |
| Reset type | synchronous |
| Reset State | 000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 9-bit adder for signal <AckTimeout_c[8]_GND_35_o_add_16_OUT> created at line 100.
Found 22-bit adder for signal <adr_o[21]_GND_35_o_add_48_OUT> created at line 200.
Found 1-bit 4-to-1 multiplexer for signal <_n0284> created at line 148.
Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148.
Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<29>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<28>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<27>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<26>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<25>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<24>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<23>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<22>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<21>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<20>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<19>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<18>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<17>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<16>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<15>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<14>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<13>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<12>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<11>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<10>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<9>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<8>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<7>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<6>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<5>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<4>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<3>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<2>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<1>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<0>> created at line 110
Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_35_o_equal_12_o> created at line 75
Found 3-bit comparator equal for signal <vme_addr[3]_intlev_reg[2]_equal_43_o> created at line 178
Summary:
inferred 2 Adder/Subtractor(s).
inferred 128 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 28 Multiplexer(s).
inferred 32 Tristate(s).
inferred 1 Finite State Machine(s).
Unit <VmeInterfaceWB> synthesized.
Synthesizing Unit <InterruptManagerWB>.
Related source file is "/vfc_svn/hdl/design/interruptmanagerwb.v".
dly = 1
int_reg_addr = 2'b00
mask_reg_addr = 2'b01
fpga_status_reg_addr = 2'b10
new_int_mode_addr = 2'b11
WARNING:Xst:647 - Input <Dat_ib32<30:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 8x8-bit dual-port RAM <Mram_int_fifo> for signal <int_fifo>.
Found 8-bit register for signal <mask_reg>.
Found 1-bit register for signal <rora_roak>.
Found 1-bit register for signal <ready4int>.
Found 1-bit register for signal <hs_int_mode>.
Found 8-bit register for signal <int_masked_old>.
Found 4-bit register for signal <int_counter>.
Found 3-bit register for signal <int_pointer_r>.
Found 3-bit register for signal <int_pointer_w>.
Found 1-bit register for signal <fifo_full>.
Found 1-bit register for signal <fifo_empty>.
Found 1-bit register for signal <Stb_d>.
Found 1-bit register for signal <osc_clk>.
Found 4-bit subtractor for signal <int_counter[3]_GND_68_o_sub_23_OUT> created at line 101.
Found 4-bit adder for signal <int_counter[3]_GND_68_o_add_20_OUT> created at line 99.
Found 3-bit adder for signal <int_pointer_w[2]_GND_68_o_add_29_OUT> created at line 115.
Found 3-bit adder for signal <int_pointer_r[2]_GND_68_o_add_31_OUT> created at line 118.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 165.
Found 3-bit comparator equal for signal <int_pointer_w[2]_int_pointer_r[2]_equal_42_o> created at line 132
Found 3-bit comparator equal for signal <n0078> created at line 134
Found 3-bit comparator equal for signal <int_pointer_r[2]_int_pointer_w[2]_equal_45_o> created at line 137
Summary:
inferred 1 RAM(s).
inferred 3 Adder/Subtractor(s).
inferred 33 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 2 Multiplexer(s).
Unit <InterruptManagerWB> synthesized.
Synthesizing Unit <AddressDecoderWBSys>.
Related source file is "/vfc_svn/hdl/design/addrdecoderwbsys.v".
WARNING:Xst:647 - Input <Adr_ib22<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AckGenericInputRegs_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 32-bit 4-to-1 multiplexer for signal <_n0045> created at line 4.
Summary:
inferred 14 Multiplexer(s).
Unit <AddressDecoderWBSys> synthesized.
Synthesizing Unit <Generic4OutputRegs>.
Related source file is "/vfc_svn/hdl/design/generic4outputregs.v".
Reg0Default = 32'b00000000000000000000000000000000
Reg1Default = 32'b00000000000000000000000000000000
Reg2Default = 32'b00000000000000001000100010001000
Reg3Default = 32'b00000000000000000000000000000000
Found 32-bit register for signal <Reg1Value_ob32>.
Found 32-bit register for signal <Reg2Value_ob32>.
Found 32-bit register for signal <Reg3Value_ob32>.
Found 32-bit register for signal <Reg0Value_ob32>.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 41.
Summary:
inferred 128 D-type flip-flop(s).
inferred 2 Multiplexer(s).
Unit <Generic4OutputRegs> synthesized.
Synthesizing Unit <Generic4InputRegs>.
Related source file is "/vfc_svn/hdl/design/generic4inputregs.v".
WARNING:Xst:647 - Input <Rst_irq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Summary:
inferred 1 Multiplexer(s).
Unit <Generic4InputRegs> synthesized.
Synthesizing Unit <Slv2SerWB>.
Related source file is "/vfc_svn/hdl/design/slv2serwb.v".
Found 32-bit register for signal <DatOutShReg_b32>.
Found 32-bit register for signal <CntrlShReg_b32>.
Found 31-bit register for signal <StbShReg_b32<30:0>>.
Found 3-bit register for signal <AckI_d3>.
Found 32-bit register for signal <DatInShReg_b32>.
Found 32-bit register for signal <Dat_xb32>.
Found 1-bit register for signal <AckI_xb3<2>>.
Found 1-bit register for signal <AckI_xb3<1>>.
Found 1-bit register for signal <AckI_xb3<0>>.
Found 32-bit register for signal <Dat_ob32>.
Found 1-bit register for signal <Ack_o>.
Found 1-bit register for signal <StbI_d>.
Summary:
inferred 199 D-type flip-flop(s).
inferred 4 Multiplexer(s).
Unit <Slv2SerWB> synthesized.
Synthesizing Unit <SpiMasterWB>.
Related source file is "/vfc_svn/hdl/design/spimasterwb.v".
Found 1-bit register for signal <WriteAck_q>.
Found 1-bit register for signal <ModuleIdle_o>.
Found 1-bit register for signal <WaitingNewData_o>.
Found 1-bit register for signal <StartTx_q>.
Found 1-bit register for signal <SClk_o>.
Found 1-bit register for signal <SS_onb32<31>>.
Found 1-bit register for signal <SS_onb32<30>>.
Found 1-bit register for signal <SS_onb32<29>>.
Found 1-bit register for signal <SS_onb32<28>>.
Found 1-bit register for signal <SS_onb32<27>>.
Found 1-bit register for signal <SS_onb32<26>>.
Found 1-bit register for signal <SS_onb32<25>>.
Found 1-bit register for signal <SS_onb32<24>>.
Found 1-bit register for signal <SS_onb32<23>>.
Found 1-bit register for signal <SS_onb32<22>>.
Found 1-bit register for signal <SS_onb32<21>>.
Found 1-bit register for signal <SS_onb32<20>>.
Found 1-bit register for signal <SS_onb32<19>>.
Found 1-bit register for signal <SS_onb32<18>>.
Found 1-bit register for signal <SS_onb32<17>>.
Found 1-bit register for signal <SS_onb32<16>>.
Found 1-bit register for signal <SS_onb32<15>>.
Found 1-bit register for signal <SS_onb32<14>>.
Found 1-bit register for signal <SS_onb32<13>>.
Found 1-bit register for signal <SS_onb32<12>>.
Found 1-bit register for signal <SS_onb32<11>>.
Found 1-bit register for signal <SS_onb32<10>>.
Found 1-bit register for signal <SS_onb32<9>>.
Found 1-bit register for signal <SS_onb32<8>>.
Found 1-bit register for signal <SS_onb32<7>>.
Found 1-bit register for signal <SS_onb32<6>>.
Found 1-bit register for signal <SS_onb32<5>>.
Found 1-bit register for signal <SS_onb32<4>>.
Found 1-bit register for signal <SS_onb32<3>>.
Found 1-bit register for signal <SS_onb32<2>>.
Found 1-bit register for signal <SS_onb32<1>>.
Found 1-bit register for signal <SS_onb32<0>>.
Found 16-bit register for signal <TimeCounter_cb16>.
Found 12-bit register for signal <TxCounter_cb12>.
Found 32-bit register for signal <Config1_qb32>.
Found 32-bit register for signal <Config2_qb32>.
Found 32-bit register for signal <ShiftOut_qb32>.
Found 32-bit register for signal <ShiftIn_qb32>.
Found 3-bit register for signal <State_q>.
Found finite state machine <FSM_1> for signal <State_q>.
-----------------------------------------------------------------------
| States | 6 |
| Transitions | 14 |
| Inputs | 5 |
| Outputs | 40 |
| Clock | Clk_ik (rising_edge) |
| Reset | Rst_irq (positive) |
| Reset type | synchronous |
| Reset State | 000 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 12-bit adder for signal <TxCounter_cb12[11]_GND_77_o_add_40_OUT> created at line 138.
Found 16-bit adder for signal <TimeCounter_cb16[15]_GND_77_o_add_67_OUT> created at line 163.
Found 1-bit 32-to-1 multiplexer for signal <a_SpiChannel_b5[4]_MiSo_ib32[31]_Mux_56_o> created at line 150.
Found 32-bit 7-to-1 multiplexer for signal <Dat_oab32> created at line 185.
Found 16-bit comparator equal for signal <TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o> created at line 77
Found 12-bit comparator equal for signal <TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o> created at line 80
Found 16-bit comparator equal for signal <TimeCounter_cb16[15]_a_ClkSemiPeriod_b16[15]_equal_20_o> created at line 84
Summary:
inferred 2 Adder/Subtractor(s).
inferred 193 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 35 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <SpiMasterWB> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x8-bit dual-port RAM : 1
# Adders/Subtractors : 13
12-bit adder : 1
16-bit adder : 2
20-bit adder : 2
22-bit adder : 4
3-bit adder : 2
4-bit addsub : 1
9-bit adder : 1
# Registers : 109
1-bit register : 68
12-bit register : 1
16-bit register : 2
2-bit register : 4
20-bit register : 2
22-bit register : 4
3-bit register : 6
31-bit register : 1
32-bit register : 15
4-bit register : 1
7-bit register : 1
8-bit register : 3
9-bit register : 1
# Comparators : 9
1-bit comparator equal : 1
12-bit comparator equal : 1
16-bit comparator equal : 2
3-bit comparator equal : 4
8-bit comparator equal : 1
# Multiplexers : 87
1-bit 2-to-1 multiplexer : 44
1-bit 32-to-1 multiplexer : 1
1-bit 4-to-1 multiplexer : 3
12-bit 2-to-1 multiplexer : 2
16-bit 2-to-1 multiplexer : 8
22-bit 2-to-1 multiplexer : 2
32-bit 2-to-1 multiplexer : 20
32-bit 4-to-1 multiplexer : 3
32-bit 7-to-1 multiplexer : 1
5-bit 2-to-1 multiplexer : 1
7-bit 2-to-1 multiplexer : 1
9-bit 2-to-1 multiplexer : 1
# Tristates : 65
1-bit tristate buffer : 65
# FSMs : 2
# Xors : 4
1-bit xor3 : 2
1-bit xor6 : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <ds1_shr_0> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ds2_shr_0> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds1_shr_1> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds2_shr_1> (without init value) has a constant value of 0 in block <i_VmeInterface>. This FF/Latch will be trimmed during the optimization process.
Synthesizing (advanced) Unit <Debouncer>.
The following registers are absorbed into counter <Counter_c>: 1 register on signal <Counter_c>.
Unit <Debouncer> synthesized (advanced).
Synthesizing (advanced) Unit <InterruptManagerWB>.
The following registers are absorbed into counter <int_counter>: 1 register on signal <int_counter>.
The following registers are absorbed into counter <int_pointer_r>: 1 register on signal <int_pointer_r>.
The following registers are absorbed into counter <int_pointer_w>: 1 register on signal <int_pointer_w>.
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_int_fifo> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 8-word x 8-bit | |
| clkA | connected to signal <Clk_ik> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <int_pointer_w> | |
| diA | connected to signal <interrupt> | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 8-word x 8-bit | |
| addrB | connected to signal <int_pointer_r> | |
| doB | connected to internal node | |
-----------------------------------------------------------------------
Unit <InterruptManagerWB> synthesized (advanced).
Synthesizing (advanced) Unit <Monostable>.
The following registers are absorbed into counter <Counter_c>: 1 register on signal <Counter_c>.
Unit <Monostable> synthesized (advanced).
Synthesizing (advanced) Unit <SystemFpga>.
The following registers are absorbed into counter <VmeSysClkDivider_c>: 1 register on signal <VmeSysClkDivider_c>.
The following registers are absorbed into counter <VcTcXoDivider_c>: 1 register on signal <VcTcXoDivider_c>.
The following registers are absorbed into counter <Si57xDivider_c>: 1 register on signal <Si57xDivider_c>.
Unit <SystemFpga> synthesized (advanced).
Synthesizing (advanced) Unit <VmeInterfaceWB>.
The following registers are absorbed into counter <AckTimeout_c>: 1 register on signal <AckTimeout_c>.
Unit <VmeInterfaceWB> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x8-bit dual-port distributed RAM : 1
# Adders/Subtractors : 5
12-bit adder : 1
16-bit adder : 1
22-bit adder : 1
3-bit adder : 2
# Counters : 10
16-bit up counter : 1
20-bit up counter : 2
22-bit up counter : 3
3-bit up counter : 2
4-bit updown counter : 1
9-bit up counter : 1
# Registers : 680
Flip-Flops : 680
# Comparators : 9
1-bit comparator equal : 1
12-bit comparator equal : 1
16-bit comparator equal : 2
3-bit comparator equal : 4
8-bit comparator equal : 1
# Multiplexers : 117
1-bit 2-to-1 multiplexer : 44
1-bit 32-to-1 multiplexer : 1
1-bit 4-to-1 multiplexer : 35
12-bit 2-to-1 multiplexer : 2
16-bit 2-to-1 multiplexer : 8
22-bit 2-to-1 multiplexer : 2
32-bit 2-to-1 multiplexer : 20
32-bit 4-to-1 multiplexer : 2
32-bit 7-to-1 multiplexer : 1
5-bit 2-to-1 multiplexer : 1
7-bit 2-to-1 multiplexer : 1
# FSMs : 2
# Xors : 4
1-bit xor3 : 2
1-bit xor6 : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
INFO:Xst:2261 - The FF/Latch <ds1_shr_0> in Unit <VmeInterfaceWB> is equivalent to the following FF/Latch, which will be removed : <ds2_shr_0>
WARNING:Xst:1710 - FF/Latch <ds1_shr_0> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds1_shr_1> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ds2_shr_1> (without init value) has a constant value of 0 in block <VmeInterfaceWB>. This FF/Latch will be trimmed during the optimization process.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <i_Core/i_VmeInterface/FSM_0> on signal <state[1:2]> with sequential encoding.
-------------------
State | Encoding
-------------------
000 | 00
011 | 01
010 | 10
001 | 11
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <i_Core/i_SpiMasterWB/FSM_1> on signal <State_q[1:3]> with user encoding.
-------------------
State | Encoding
-------------------
000 | 000
001 | 001
010 | 010
011 | 011
100 | 100
101 | 101
-------------------
WARNING:Xst:1293 - FF/Latch <CntrlShReg_b32_31> has a constant value of 0 in block <Slv2SerWB>. This FF/Latch will be trimmed during the optimization process.
Optimizing unit <SFpga> ...
Optimizing unit <Monostable> ...
Optimizing unit <Debouncer> ...
Optimizing unit <InterruptManagerWB> ...
Optimizing unit <Generic4OutputRegs> ...
Optimizing unit <Slv2SerWB> ...
Optimizing unit <SpiMasterWB> ...
Optimizing unit <AddressDecoderWBSys> ...
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_9> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_10> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_11> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_12> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_14> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_15> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_13> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_16> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_17> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_19> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_20> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_18> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_22> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_23> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_21> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_25> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_26> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_24> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_27> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_28> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_30> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_31> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_29> of sequential type is unconnected in block <SFpga>.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SFpga, actual ratio is 1.
FlipFlop i_Core/i_VmeInterface/adr_o_21 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/adr_o_3 has been replicated 1 time(s)
Final Macro Processing ...
Processing Unit <SFpga> :
Found 2-bit shift register for signal <i_Core/VmeSysReset_dx_1>.
Found 3-bit shift register for signal <i_Core/i_Debouncer/BouncingSignal_x_2>.
Found 2-bit shift register for signal <i_Core/i_Slv2SerWB/AckI_xb3_0>.
Unit <SFpga> processed.
=========================================================================
Final Register Report
Macro Statistics
# Registers : 793
Flip-Flops : 793
# Shift Registers : 3
2-bit shift register : 2
3-bit shift register : 1
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : SFpga.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1430
# GND : 1
# INV : 29
# LUT1 : 163
# LUT2 : 163
# LUT3 : 121
# LUT4 : 112
# LUT5 : 148
# LUT6 : 307
# MUXCY : 186
# MUXF7 : 18
# VCC : 1
# XORCY : 181
# FlipFlops/Latches : 796
# FD : 189
# FDE : 99
# FDPE : 1
# FDR : 135
# FDRE : 313
# FDS : 26
# FDSE : 33
# RAMS : 3
# RAM16X1D : 2
# RAM32M : 1
# Shift Registers : 3
# SRLC16E : 3
# Clock Buffers : 4
# BUFG : 1
# BUFGP : 3
# IO Buffers : 305
# IBUF : 77
# IBUFGDS : 6
# IOBUF : 32
# IOBUFDS : 2
# OBUF : 152
# OBUFDS : 3
# OBUFT : 33
Device utilization summary:
---------------------------
Selected Device : 6slx150tfgg676-3
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184304 0%
Number of Slice LUTs: 1054 out of 92152 1%
Number used as Logic: 1043 out of 92152 1%
Number used as Memory: 11 out of 21680 0%
Number used as RAM: 8
Number used as SRL: 3
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1274
Number with an unused Flip Flop: 478 out of 1274 37%
Number with an unused LUT: 220 out of 1274 17%
Number of fully used LUT-FF pairs: 576 out of 1274 45%
Number of unique control sets: 32
IO Utilization:
Number of IOs: 365
Number of bonded IOBs: 319 out of 396 80%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 4 out of 16 25%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+-----------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+-----------------------------------------------+-------+
Si57x_ik | IBUFGDS+BUFG | 688 |
VcTcXo_ik | BUFGP | 22 |
VmeSysClk_ik | BUFGP | 22 |
i_Core/i_VmeInterface/stb_o | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax)| 1 |
i_Core/Rst_rq | NONE(i_Core/i_ClearMonostable/AsynchIn_ax) | 1 |
SysAppClk_ik | BUFGP | 68 |
-----------------------------------+-----------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 8.328ns (Maximum Frequency: 120.083MHz)
Minimum input arrival time before clock: 8.362ns
Maximum output required time after clock: 6.030ns
Maximum combinational path delay: 6.896ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'Si57x_ik'
Clock period: 8.328ns (frequency: 120.083MHz)
Total number of paths / destination ports: 44586 / 1579
-------------------------------------------------------------------------
Delay: 8.328ns (Levels of Logic = 5)
Source: i_Core/i_VmeInterface/adr_o_21_1 (FF)
Destination: i_Core/i_VmeInterface/DataReg_31 (FF)
Source Clock: Si57x_ik rising
Destination Clock: Si57x_ik rising
Data Path: i_Core/i_VmeInterface/adr_o_21_1 to i_Core/i_VmeInterface/DataReg_31
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 2 0.525 1.047 i_Core/i_VmeInterface/adr_o_21_1 (i_Core/i_VmeInterface/adr_o_21_1)
LUT6:I1->O 4 0.254 0.912 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1)
LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster)
LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster)
LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o)
FDSE:CE 0.302 i_Core/i_VmeInterface/DataReg_0
----------------------------------------
Total 8.328ns (2.074ns logic, 6.254ns route)
(24.9% logic, 75.1% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 2.319ns (frequency: 431.248MHz)
Total number of paths / destination ports: 253 / 22
-------------------------------------------------------------------------
Delay: 2.319ns (Levels of Logic = 23)
Source: i_Core/VcTcXoDivider_c_0 (FF)
Destination: i_Core/VcTcXoDivider_c_21 (FF)
Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising
Data Path: i_Core/VcTcXoDivider_c_0 to i_Core/VcTcXoDivider_c_21
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.579 i_Core/VcTcXoDivider_c_0 (i_Core/VcTcXoDivider_c_0)
INV:I->O 1 0.255 0.000 i_Core/Mcount_VcTcXoDivider_c_lut<0>_INV_0 (i_Core/Mcount_VcTcXoDivider_c_lut<0>)
MUXCY:S->O 1 0.215 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<0> (i_Core/Mcount_VcTcXoDivider_c_cy<0>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<1> (i_Core/Mcount_VcTcXoDivider_c_cy<1>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<2> (i_Core/Mcount_VcTcXoDivider_c_cy<2>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<3> (i_Core/Mcount_VcTcXoDivider_c_cy<3>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<4> (i_Core/Mcount_VcTcXoDivider_c_cy<4>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<5> (i_Core/Mcount_VcTcXoDivider_c_cy<5>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<6> (i_Core/Mcount_VcTcXoDivider_c_cy<6>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<7> (i_Core/Mcount_VcTcXoDivider_c_cy<7>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<8> (i_Core/Mcount_VcTcXoDivider_c_cy<8>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<9> (i_Core/Mcount_VcTcXoDivider_c_cy<9>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<10> (i_Core/Mcount_VcTcXoDivider_c_cy<10>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<11> (i_Core/Mcount_VcTcXoDivider_c_cy<11>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<12> (i_Core/Mcount_VcTcXoDivider_c_cy<12>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<13> (i_Core/Mcount_VcTcXoDivider_c_cy<13>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<14> (i_Core/Mcount_VcTcXoDivider_c_cy<14>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<15> (i_Core/Mcount_VcTcXoDivider_c_cy<15>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<16> (i_Core/Mcount_VcTcXoDivider_c_cy<16>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<17> (i_Core/Mcount_VcTcXoDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<18> (i_Core/Mcount_VcTcXoDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<19> (i_Core/Mcount_VcTcXoDivider_c_cy<19>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<20> (i_Core/Mcount_VcTcXoDivider_c_cy<20>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VcTcXoDivider_c_xor<21> (i_Core/Result<21>1)
FD:D 0.074 i_Core/VcTcXoDivider_c_21
----------------------------------------
Total 2.319ns (1.740ns logic, 0.579ns route)
(75.0% logic, 25.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'VmeSysClk_ik'
Clock period: 2.319ns (frequency: 431.248MHz)
Total number of paths / destination ports: 253 / 22
-------------------------------------------------------------------------
Delay: 2.319ns (Levels of Logic = 23)
Source: i_Core/VmeSysClkDivider_c_0 (FF)
Destination: i_Core/VmeSysClkDivider_c_21 (FF)
Source Clock: VmeSysClk_ik rising
Destination Clock: VmeSysClk_ik rising
Data Path: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_21
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.579 i_Core/VmeSysClkDivider_c_0 (i_Core/VmeSysClkDivider_c_0)
INV:I->O 1 0.255 0.000 i_Core/Mcount_VmeSysClkDivider_c_lut<0>_INV_0 (i_Core/Mcount_VmeSysClkDivider_c_lut<0>)
MUXCY:S->O 1 0.215 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<0> (i_Core/Mcount_VmeSysClkDivider_c_cy<0>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<1> (i_Core/Mcount_VmeSysClkDivider_c_cy<1>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<2> (i_Core/Mcount_VmeSysClkDivider_c_cy<2>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<3> (i_Core/Mcount_VmeSysClkDivider_c_cy<3>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<4> (i_Core/Mcount_VmeSysClkDivider_c_cy<4>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<5> (i_Core/Mcount_VmeSysClkDivider_c_cy<5>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<6> (i_Core/Mcount_VmeSysClkDivider_c_cy<6>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<7> (i_Core/Mcount_VmeSysClkDivider_c_cy<7>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<8> (i_Core/Mcount_VmeSysClkDivider_c_cy<8>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<9> (i_Core/Mcount_VmeSysClkDivider_c_cy<9>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<10> (i_Core/Mcount_VmeSysClkDivider_c_cy<10>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<11> (i_Core/Mcount_VmeSysClkDivider_c_cy<11>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<12> (i_Core/Mcount_VmeSysClkDivider_c_cy<12>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<13> (i_Core/Mcount_VmeSysClkDivider_c_cy<13>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<14> (i_Core/Mcount_VmeSysClkDivider_c_cy<14>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<15> (i_Core/Mcount_VmeSysClkDivider_c_cy<15>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<16> (i_Core/Mcount_VmeSysClkDivider_c_cy<16>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<17> (i_Core/Mcount_VmeSysClkDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<18> (i_Core/Mcount_VmeSysClkDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<19> (i_Core/Mcount_VmeSysClkDivider_c_cy<19>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<20> (i_Core/Mcount_VmeSysClkDivider_c_cy<20>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VmeSysClkDivider_c_xor<21> (i_Core/Result<21>)
FD:D 0.074 i_Core/VmeSysClkDivider_c_21
----------------------------------------
Total 2.319ns (1.740ns logic, 0.579ns route)
(75.0% logic, 25.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/i_VmeInterface/stb_o'
Clock period: 2.049ns (frequency: 488.019MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 2.049ns (Levels of Logic = 1)
Source: i_Core/i_VmeAccessMonostable/AsynchIn_ax (FF)
Destination: i_Core/i_VmeAccessMonostable/AsynchIn_ax (FF)
Source Clock: i_Core/i_VmeInterface/stb_o rising
Destination Clock: i_Core/i_VmeInterface/stb_o rising
Data Path: i_Core/i_VmeAccessMonostable/AsynchIn_ax to i_Core/i_VmeAccessMonostable/AsynchIn_ax
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.616 i_Core/i_VmeAccessMonostable/AsynchIn_ax (i_Core/i_VmeAccessMonostable/AsynchIn_ax)
INV:I->O 1 0.255 0.579 i_Core/i_VmeAccessMonostable/AsynchIn_ax_INV_1_o1_INV_0 (i_Core/i_VmeAccessMonostable/AsynchIn_ax_INV_1_o)
FD:D 0.074 i_Core/i_VmeAccessMonostable/AsynchIn_ax
----------------------------------------
Total 2.049ns (0.854ns logic, 1.195ns route)
(41.7% logic, 58.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/Rst_rq'
Clock period: 2.049ns (frequency: 488.019MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 2.049ns (Levels of Logic = 1)
Source: i_Core/i_ClearMonostable/AsynchIn_ax (FF)
Destination: i_Core/i_ClearMonostable/AsynchIn_ax (FF)
Source Clock: i_Core/Rst_rq rising
Destination Clock: i_Core/Rst_rq rising
Data Path: i_Core/i_ClearMonostable/AsynchIn_ax to i_Core/i_ClearMonostable/AsynchIn_ax
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.616 i_Core/i_ClearMonostable/AsynchIn_ax (i_Core/i_ClearMonostable/AsynchIn_ax)
INV:I->O 1 0.255 0.579 i_Core/i_ClearMonostable/AsynchIn_ax_INV_1_o1_INV_0 (i_Core/i_ClearMonostable/AsynchIn_ax_INV_1_o)
FD:D 0.074 i_Core/i_ClearMonostable/AsynchIn_ax
----------------------------------------
Total 2.049ns (0.854ns logic, 1.195ns route)
(41.7% logic, 58.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'SysAppClk_ik'
Clock period: 3.056ns (frequency: 327.221MHz)
Total number of paths / destination ports: 129 / 97
-------------------------------------------------------------------------
Delay: 3.056ns (Levels of Logic = 1)
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_31 (FF)
Source Clock: SysAppClk_ik rising
Destination Clock: SysAppClk_ik rising
Data Path: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_31
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 0.525 0.688 i_Core/i_Slv2SerWB/AckI_d3_2 (i_Core/i_Slv2SerWB/AckI_d3_2)
LUT2:I0->O 32 0.250 1.291 i_Core/i_Slv2SerWB/NewAckI_a<2>1 (i_Core/i_Slv2SerWB/NewAckI_a)
FDE:CE 0.302 i_Core/i_Slv2SerWB/Dat_xb32_0
----------------------------------------
Total 3.056ns (1.077ns logic, 1.979ns route)
(35.2% logic, 64.8% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Si57x_ik'
Total number of paths / destination ports: 1705 / 116
-------------------------------------------------------------------------
Offset: 8.362ns (Levels of Logic = 6)
Source: VmeGa_ib5n<0> (PAD)
Destination: i_Core/i_VmeInterface/adr_o_21 (FF)
Destination Clock: Si57x_ik rising
Data Path: VmeGa_ib5n<0> to i_Core/i_VmeInterface/adr_o_21
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N5)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N259)
LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected)
LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv)
FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0
----------------------------------------
Total 8.362ns (2.758ns logic, 5.604ns route)
(33.0% logic, 67.0% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SysAppClk_ik'
Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset: 1.918ns (Levels of Logic = 1)
Source: AFpgaProgD_iob8<4> (PAD)
Destination: i_Core/i_Slv2SerWB/AckI_xb3_2 (FF)
Destination Clock: SysAppClk_ik rising
Data Path: AFpgaProgD_iob8<4> to i_Core/i_Slv2SerWB/AckI_xb3_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.228 0.616 AFpgaProgD_iob8_4_IBUF (AFpgaProgD_iob8_4_IBUF)
FDR:D 0.074 i_Core/i_Slv2SerWB/AckI_d3_0
----------------------------------------
Total 1.918ns (1.302ns logic, 0.616ns route)
(67.9% logic, 32.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Si57x_ik'
Total number of paths / destination ports: 190 / 94
-------------------------------------------------------------------------
Offset: 6.030ns (Levels of Logic = 2)
Source: i_Core/i_SpiMasterWB/Config1_qb32_29 (FF)
Destination: FlashSFpgaD_o (PAD)
Source Clock: Si57x_ik rising
Data Path: i_Core/i_SpiMasterWB/Config1_qb32_29 to FlashSFpgaD_o
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 66 0.525 1.654 i_Core/i_SpiMasterWB/Config1_qb32_29 (i_Core/i_SpiMasterWB/Config1_qb32_29)
LUT3:I2->O 11 0.254 0.882 i_Core/i_SpiMasterWB/Mmux_MoSi_o11 (FlashAFpgaD_o_OBUF)
OBUF:I->O 2.715 PllFmc1SDio_io_OBUF (PllFmc1SDio_io)
----------------------------------------
Total 6.030ns (3.494ns logic, 2.536ns route)
(57.9% logic, 42.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'VmeSysClk_ik'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 4.828ns (Levels of Logic = 2)
Source: i_Core/VmeSysClkDivider_c_21 (FF)
Destination: FpLed_onb8<7> (PAD)
Source Clock: VmeSysClk_ik rising
Data Path: i_Core/VmeSysClkDivider_c_21 to FpLed_onb8<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 3 0.525 0.759 i_Core/VmeSysClkDivider_c_21 (i_Core/VmeSysClkDivider_c_21)
LUT5:I3->O 1 0.250 0.579 i_Core/Mmux_a_FpLed711 (i_Core/a_FpLed7)
OBUFT:T->O 2.715 FpLed_onb8_7_OBUFT (FpLed_onb8<7>)
----------------------------------------
Total 4.828ns (3.490ns logic, 1.338ns route)
(72.3% logic, 27.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 4.724ns (Levels of Logic = 2)
Source: i_Core/VcTcXoDivider_c_21 (FF)
Destination: FpLed_onb8<7> (PAD)
Source Clock: VcTcXo_ik rising
Data Path: i_Core/VcTcXoDivider_c_21 to FpLed_onb8<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 3 0.525 0.651 i_Core/VcTcXoDivider_c_21 (i_Core/VcTcXoDivider_c_21)
LUT5:I4->O 1 0.254 0.579 i_Core/Mmux_a_FpLed711 (i_Core/a_FpLed7)
OBUFT:T->O 2.715 FpLed_onb8_7_OBUFT (FpLed_onb8<7>)
----------------------------------------
Total 4.724ns (3.494ns logic, 1.230ns route)
(74.0% logic, 26.0% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 21 / 8
-------------------------------------------------------------------------
Delay: 6.896ns (Levels of Logic = 4)
Source: VmeGa_ib5n<0> (PAD)
Destination: FpLed_onb8<2> (PAD)
Data Path: VmeGa_ib5n<0> to FpLed_onb8<2>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.823 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT2:I0->O 1 0.250 0.579 i_Core/VmeGa_ib5n[4]_UseGa_i_OR_1_o_inv1 (i_Core/VmeGa_ib5n[4]_UseGa_i_OR_1_o_inv)
OBUFT:T->O 2.715 FpLed_onb8_2_OBUFT (FpLed_onb8<2>)
----------------------------------------
Total 6.896ns (4.447ns logic, 2.449ns route)
(64.5% logic, 35.5% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock Si57x_ik
---------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+
Si57x_ik | 8.328| | | |
SysAppClk_ik | 1.178| | | |
i_Core/Rst_rq | 1.215| | | |
i_Core/i_VmeInterface/stb_o| 1.215| | | |
---------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 3.078| | | |
SysAppClk_ik | 3.056| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VcTcXo_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VcTcXo_ik | 2.319| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VmeSysClk_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VmeSysClk_ik | 2.319| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock i_Core/Rst_rq
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
i_Core/Rst_rq | 2.049| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock i_Core/i_VmeInterface/stb_o
---------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+
i_Core/i_VmeInterface/stb_o| 2.049| | | |
---------------------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 28.00 secs
Total CPU time to Xst completion: 28.30 secs
-->
Total memory usage is 154916 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 126 ( 0 filtered)
Number of infos : 12 ( 0 filtered)
trunk/firmware/XilinxISE/SystemFpga/SFpga.twr 0 → 100644
View file @ 23b1b4b5
--------------------------------------------------------------------------------
Release 12.3 Trace (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
Design file: SFpga.ncd
Physical constraint file: SFpga.pcf
Device,package,speed: xc6slx150t,fgg676,C,-3 (PRODUCTION 1.12c 2010-09-15)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
44725 paths analyzed, 2977 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 8.144ns.
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (SLICE_X63Y77.C4), 310 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.189ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF)
Requirement: 8.333ns
Data Path Delay: 8.211ns (Levels of Logic = 6)
Clock Path Skew: 0.102ns (0.993 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_11 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y101.DQ Tcko 0.476 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_VmeInterface/adr_o_11
SLICE_X87Y100.C1 net (fanout=4) 1.116 i_Core/i_VmeInterface/adr_o<11>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y77.C4 net (fanout=32) 0.621 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y77.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16>
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_16
------------------------------------------------- ---------------------------
Total 8.211ns (2.135ns logic, 6.076ns route)
(26.0% logic, 74.0% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.392ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_9 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF)
Requirement: 8.333ns
Data Path Delay: 8.008ns (Levels of Logic = 6)
Clock Path Skew: 0.102ns (0.993 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_9 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X87Y101.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_9
SLICE_X87Y100.C6 net (fanout=4) 0.959 i_Core/i_VmeInterface/adr_o<9>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y77.C4 net (fanout=32) 0.621 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y77.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16>
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_16
------------------------------------------------- ---------------------------
Total 8.008ns (2.089ns logic, 5.919ns route)
(26.1% logic, 73.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.626ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_6 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF)
Requirement: 8.333ns
Data Path Delay: 7.774ns (Levels of Logic = 6)
Clock Path Skew: 0.102ns (0.993 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_6 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X87Y101.AQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_6
SLICE_X87Y100.C2 net (fanout=4) 0.725 i_Core/i_VmeInterface/adr_o<6>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y77.C4 net (fanout=32) 0.621 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y77.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16>
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_16
------------------------------------------------- ---------------------------
Total 7.774ns (2.089ns logic, 5.685ns route)
(26.9% logic, 73.1% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_21 (SLICE_X67Y77.C6), 310 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.194ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_21 (FF)
Requirement: 8.333ns
Data Path Delay: 8.206ns (Levels of Logic = 6)
Clock Path Skew: 0.102ns (0.993 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_11 to i_Core/i_SpiMasterWB/ShiftIn_qb32_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y101.DQ Tcko 0.476 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_VmeInterface/adr_o_11
SLICE_X87Y100.C1 net (fanout=4) 1.116 i_Core/i_VmeInterface/adr_o<11>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y77.C6 net (fanout=32) 0.616 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y77.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<9>
i_Core/i_SpiMasterWB/ShiftIn_qb32_21_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_21
------------------------------------------------- ---------------------------
Total 8.206ns (2.135ns logic, 6.071ns route)
(26.0% logic, 74.0% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.397ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_9 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_21 (FF)
Requirement: 8.333ns
Data Path Delay: 8.003ns (Levels of Logic = 6)
Clock Path Skew: 0.102ns (0.993 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_9 to i_Core/i_SpiMasterWB/ShiftIn_qb32_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X87Y101.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_9
SLICE_X87Y100.C6 net (fanout=4) 0.959 i_Core/i_VmeInterface/adr_o<9>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y77.C6 net (fanout=32) 0.616 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y77.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<9>
i_Core/i_SpiMasterWB/ShiftIn_qb32_21_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_21
------------------------------------------------- ---------------------------
Total 8.003ns (2.089ns logic, 5.914ns route)
(26.1% logic, 73.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.631ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_6 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_21 (FF)
Requirement: 8.333ns
Data Path Delay: 7.769ns (Levels of Logic = 6)
Clock Path Skew: 0.102ns (0.993 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_6 to i_Core/i_SpiMasterWB/ShiftIn_qb32_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X87Y101.AQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_6
SLICE_X87Y100.C2 net (fanout=4) 0.725 i_Core/i_VmeInterface/adr_o<6>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y77.C6 net (fanout=32) 0.616 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y77.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<9>
i_Core/i_SpiMasterWB/ShiftIn_qb32_21_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_21
------------------------------------------------- ---------------------------
Total 7.769ns (2.089ns logic, 5.680ns route)
(26.9% logic, 73.1% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_30 (SLICE_X67Y75.C6), 310 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.197ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_30 (FF)
Requirement: 8.333ns
Data Path Delay: 8.199ns (Levels of Logic = 6)
Clock Path Skew: 0.098ns (0.989 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_11 to i_Core/i_SpiMasterWB/ShiftIn_qb32_30
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y101.DQ Tcko 0.476 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_VmeInterface/adr_o_11
SLICE_X87Y100.C1 net (fanout=4) 1.116 i_Core/i_VmeInterface/adr_o<11>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y75.C6 net (fanout=32) 0.609 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y75.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<30>
i_Core/i_SpiMasterWB/ShiftIn_qb32_30_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_30
------------------------------------------------- ---------------------------
Total 8.199ns (2.135ns logic, 6.064ns route)
(26.0% logic, 74.0% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.400ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_9 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_30 (FF)
Requirement: 8.333ns
Data Path Delay: 7.996ns (Levels of Logic = 6)
Clock Path Skew: 0.098ns (0.989 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_9 to i_Core/i_SpiMasterWB/ShiftIn_qb32_30
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X87Y101.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_9
SLICE_X87Y100.C6 net (fanout=4) 0.959 i_Core/i_VmeInterface/adr_o<9>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y75.C6 net (fanout=32) 0.609 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y75.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<30>
i_Core/i_SpiMasterWB/ShiftIn_qb32_30_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_30
------------------------------------------------- ---------------------------
Total 7.996ns (2.089ns logic, 5.907ns route)
(26.1% logic, 73.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.634ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_6 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_30 (FF)
Requirement: 8.333ns
Data Path Delay: 7.762ns (Levels of Logic = 6)
Clock Path Skew: 0.098ns (0.989 - 0.891)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_6 to i_Core/i_SpiMasterWB/ShiftIn_qb32_30
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X87Y101.AQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_6
SLICE_X87Y100.C2 net (fanout=4) 0.725 i_Core/i_VmeInterface/adr_o<6>
SLICE_X87Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A2 net (fanout=3) 0.541 i_Core/i_AddressDecoderWB/_n00432
SLICE_X87Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/_n00434_1
SLICE_X79Y90.B3 net (fanout=1) 1.395 i_Core/i_AddressDecoderWB/_n00434
SLICE_X79Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X64Y76.C6 net (fanout=5) 2.102 i_Core/StbSpiMaster
SLICE_X64Y76.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X64Y76.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X64Y76.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y75.C6 net (fanout=32) 0.609 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X67Y75.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<30>
i_Core/i_SpiMasterWB/ShiftIn_qb32_30_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_30
------------------------------------------------- ---------------------------
Total 7.762ns (2.089ns logic, 5.673ns route)
(26.9% logic, 73.1% route)
--------------------------------------------------------------------------------
Hold Paths: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMA (SLICE_X84Y89.D3), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.321ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_InterruptManager/int_pointer_w_2 (FF)
Destination: i_Core/i_InterruptManager/Mram_int_fifo1_RAMA (RAM)
Requirement: 0.000ns
Data Path Delay: 0.325ns (Levels of Logic = 0)
Clock Path Skew: 0.004ns (0.069 - 0.065)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_2 to i_Core/i_InterruptManager/Mram_int_fifo1_RAMA
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X83Y89.BQ Tcko 0.198 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_InterruptManager/int_pointer_w_2
SLICE_X84Y89.D3 net (fanout=8) 0.299 i_Core/i_InterruptManager/int_pointer_w<2>
SLICE_X84Y89.CLK Tah (-Th) 0.172 i_Core/i_InterruptManager/_n0165<5>
i_Core/i_InterruptManager/Mram_int_fifo1_RAMA
------------------------------------------------- ---------------------------
Total 0.325ns (0.026ns logic, 0.299ns route)
(8.0% logic, 92.0% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1 (SLICE_X84Y89.D3), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.321ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_InterruptManager/int_pointer_w_2 (FF)
Destination: i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1 (RAM)
Requirement: 0.000ns
Data Path Delay: 0.325ns (Levels of Logic = 0)
Clock Path Skew: 0.004ns (0.069 - 0.065)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_2 to i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X83Y89.BQ Tcko 0.198 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_InterruptManager/int_pointer_w_2
SLICE_X84Y89.D3 net (fanout=8) 0.299 i_Core/i_InterruptManager/int_pointer_w<2>
SLICE_X84Y89.CLK Tah (-Th) 0.172 i_Core/i_InterruptManager/_n0165<5>
i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1
------------------------------------------------- ---------------------------
Total 0.325ns (0.026ns logic, 0.299ns route)
(8.0% logic, 92.0% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMB (SLICE_X84Y89.D3), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.321ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_InterruptManager/int_pointer_w_2 (FF)
Destination: i_Core/i_InterruptManager/Mram_int_fifo1_RAMB (RAM)
Requirement: 0.000ns
Data Path Delay: 0.325ns (Levels of Logic = 0)
Clock Path Skew: 0.004ns (0.069 - 0.065)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_2 to i_Core/i_InterruptManager/Mram_int_fifo1_RAMB
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X83Y89.BQ Tcko 0.198 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_InterruptManager/int_pointer_w_2
SLICE_X84Y89.D3 net (fanout=8) 0.299 i_Core/i_InterruptManager/int_pointer_w<2>
SLICE_X84Y89.CLK Tah (-Th) 0.172 i_Core/i_InterruptManager/_n0165<5>
i_Core/i_InterruptManager/Mram_int_fifo1_RAMB
------------------------------------------------- ---------------------------
Total 0.325ns (0.026ns logic, 0.299ns route)
(8.0% logic, 92.0% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 5.833ns (period - min period limit)
Period: 8.333ns
Min period limit: 2.500ns (400.000MHz) (Tbcper_I)
Physical resource: Si57x_BUFG/I0
Logical resource: Si57x_BUFG/I0
Location pin: BUFGMUX_X2Y4.I0
Clock network: Si57x
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
Period: 8.333ns
Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/i_Debouncer/BouncingSignal_x<2>/CLK
Logical resource: i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2/CLK
Location pin: SLICE_X22Y33.CLK
Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
Period: 8.333ns
Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/VmeSysReset_dx<1>/CLK
Logical resource: i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0/CLK
Location pin: SLICE_X72Y108.CLK
Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock Si57x_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 8.144| | | |
Si57x_ikn | 8.144| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock Si57x_ikn
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 8.144| | | |
Si57x_ikn | 8.144| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 44725 paths, 0 nets, and 4167 connections
Design statistics:
Minimum period: 8.144ns{1} (Maximum frequency: 122.790MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Thu Dec 16 18:44:35 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 273 MB
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx 0 → 100644
View file @ 23b1b4b5
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<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 12.3 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
</twCmdLine><twDesign>SFpga.ncd</twDesign><twDesignPath>SFpga.ncd</twDesignPath><twPCF>SFpga.pcf</twPCF><twPcfPath>SFpga.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg676"><twDevName>xc6slx150t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.12c 2010-09-15</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="4" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="TIMESPEC TS_Si57x_ik = PERIOD &quot;Si57x_ik&quot; 120 MHz HIGH 50 %;" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%;</twConstName><twItemCnt>44725</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>2977</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>8.144</twMinPer></twConstHead><twPathRptBanner iPaths="310" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (SLICE_X63Y77.C4), 310 paths
</twPathRptBanner><twPathRpt anchorID="5"><twConstPath anchorID="6" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.189</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_11</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twDest><twTotPathDel>8.211</twTotPathDel><twClkSkew dest = "0.993" src = "0.891">-0.102</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_11</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X86Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X86Y101.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;11&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.116</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y77.C4</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.621</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y77.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;16&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twBEL></twPathDel><twLogDel>2.135</twLogDel><twRouteDel>6.076</twRouteDel><twTotDel>8.211</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.0</twPctLog><twPctRoute>74.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="7"><twConstPath anchorID="8" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.392</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_9</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twDest><twTotPathDel>8.008</twTotPathDel><twClkSkew dest = "0.993" src = "0.891">-0.102</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_9</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X87Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X87Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;15&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.959</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y77.C4</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.621</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y77.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;16&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twBEL></twPathDel><twLogDel>2.089</twLogDel><twRouteDel>5.919</twRouteDel><twTotDel>8.008</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.1</twPctLog><twPctRoute>73.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="9"><twConstPath anchorID="10" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.626</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_6</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twDest><twTotPathDel>7.774</twTotPathDel><twClkSkew dest = "0.993" src = "0.891">-0.102</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_6</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X87Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X87Y101.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;15&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.725</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y77.C4</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.621</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y77.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;16&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_16</twBEL></twPathDel><twLogDel>2.089</twLogDel><twRouteDel>5.685</twRouteDel><twTotDel>7.774</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.9</twPctLog><twPctRoute>73.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="310" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_21 (SLICE_X67Y77.C6), 310 paths
</twPathRptBanner><twPathRpt anchorID="11"><twConstPath anchorID="12" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.194</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_11</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twDest><twTotPathDel>8.206</twTotPathDel><twClkSkew dest = "0.993" src = "0.891">-0.102</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_11</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X86Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X86Y101.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;11&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.116</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X67Y77.C6</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.616</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X67Y77.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;9&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_21_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twBEL></twPathDel><twLogDel>2.135</twLogDel><twRouteDel>6.071</twRouteDel><twTotDel>8.206</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.0</twPctLog><twPctRoute>74.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="13"><twConstPath anchorID="14" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.397</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_9</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twDest><twTotPathDel>8.003</twTotPathDel><twClkSkew dest = "0.993" src = "0.891">-0.102</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_9</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X87Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X87Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;15&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.959</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X67Y77.C6</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.616</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X67Y77.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;9&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_21_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twBEL></twPathDel><twLogDel>2.089</twLogDel><twRouteDel>5.914</twRouteDel><twTotDel>8.003</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.1</twPctLog><twPctRoute>73.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="15"><twConstPath anchorID="16" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.631</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_6</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twDest><twTotPathDel>7.769</twTotPathDel><twClkSkew dest = "0.993" src = "0.891">-0.102</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_6</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X87Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X87Y101.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;15&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.725</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X67Y77.C6</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.616</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X67Y77.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;9&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_21_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_21</twBEL></twPathDel><twLogDel>2.089</twLogDel><twRouteDel>5.680</twRouteDel><twTotDel>7.769</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.9</twPctLog><twPctRoute>73.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="310" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_30 (SLICE_X67Y75.C6), 310 paths
</twPathRptBanner><twPathRpt anchorID="17"><twConstPath anchorID="18" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.197</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_11</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twDest><twTotPathDel>8.199</twTotPathDel><twClkSkew dest = "0.989" src = "0.891">-0.098</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_11</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X86Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X86Y101.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;11&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.116</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X67Y75.C6</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.609</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X67Y75.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;30&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_30_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twBEL></twPathDel><twLogDel>2.135</twLogDel><twRouteDel>6.064</twRouteDel><twTotDel>8.199</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.0</twPctLog><twPctRoute>74.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="19"><twConstPath anchorID="20" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.400</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_9</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twDest><twTotPathDel>7.996</twTotPathDel><twClkSkew dest = "0.989" src = "0.891">-0.098</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_9</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X87Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X87Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;15&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.959</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X67Y75.C6</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.609</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X67Y75.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;30&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_30_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twBEL></twPathDel><twLogDel>2.089</twLogDel><twRouteDel>5.907</twRouteDel><twTotDel>7.996</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.1</twPctLog><twPctRoute>73.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="21"><twConstPath anchorID="22" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.634</twSlack><twSrc BELType="FF">i_Core/i_VmeInterface/adr_o_6</twSrc><twDest BELType="FF">i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twDest><twTotPathDel>7.762</twTotPathDel><twClkSkew dest = "0.989" src = "0.891">-0.098</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_VmeInterface/adr_o_6</twSrc><twDest BELType='FF'>i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X87Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X87Y101.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;15&gt;</twComp><twBEL>i_Core/i_VmeInterface/adr_o_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.725</twDelInfo><twComp>i_Core/i_VmeInterface/adr_o&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00432</twBEL></twPathDel><twPathDel><twSite>SLICE_X87Y100.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00432</twComp></twPathDel><twPathDel><twSite>SLICE_X87Y100.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1</twComp><twBEL>i_Core/i_AddressDecoderWB/_n00434_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y90.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.395</twDelInfo><twComp>i_Core/i_AddressDecoderWB/_n00434</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y90.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_VmeInterface/ack_d</twComp><twBEL>i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.C6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">2.102</twDelInfo><twComp>i_Core/StbSpiMaster</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0649_inv11_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y76.B4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.301</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0649_inv11</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y76.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;31&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/_n0817_inv</twBEL></twPathDel><twPathDel><twSite>SLICE_X67Y75.C6</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">0.609</twDelInfo><twComp>i_Core/i_SpiMasterWB/_n0817_inv</twComp></twPathDel><twPathDel><twSite>SLICE_X67Y75.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>i_Core/i_SpiMasterWB/ShiftIn_qb32&lt;30&gt;</twComp><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_30_rstpot</twBEL><twBEL>i_Core/i_SpiMasterWB/ShiftIn_qb32_30</twBEL></twPathDel><twLogDel>2.089</twLogDel><twRouteDel>5.673</twRouteDel><twTotDel>7.762</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>26.9</twPctLog><twPctRoute>73.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMA (SLICE_X84Y89.D3), 1 path
</twPathRptBanner><twPathRpt anchorID="23"><twConstPath anchorID="24" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.321</twSlack><twSrc BELType="FF">i_Core/i_InterruptManager/int_pointer_w_2</twSrc><twDest BELType="RAM">i_Core/i_InterruptManager/Mram_int_fifo1_RAMA</twDest><twTotPathDel>0.325</twTotPathDel><twClkSkew dest = "0.069" src = "0.065">-0.004</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_InterruptManager/int_pointer_w_2</twSrc><twDest BELType='RAM'>i_Core/i_InterruptManager/Mram_int_fifo1_RAMA</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X83Y89.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X83Y89.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>i_Core/i_InterruptManager/int_pointer_w&lt;2&gt;</twComp><twBEL>i_Core/i_InterruptManager/int_pointer_w_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X84Y89.D3</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twFalling">0.299</twDelInfo><twComp>i_Core/i_InterruptManager/int_pointer_w&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X84Y89.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.172</twDelInfo><twComp>i_Core/i_InterruptManager/_n0165&lt;5&gt;</twComp><twBEL>i_Core/i_InterruptManager/Mram_int_fifo1_RAMA</twBEL></twPathDel><twLogDel>0.026</twLogDel><twRouteDel>0.299</twRouteDel><twTotDel>0.325</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>8.0</twPctLog><twPctRoute>92.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1 (SLICE_X84Y89.D3), 1 path
</twPathRptBanner><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.321</twSlack><twSrc BELType="FF">i_Core/i_InterruptManager/int_pointer_w_2</twSrc><twDest BELType="RAM">i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1</twDest><twTotPathDel>0.325</twTotPathDel><twClkSkew dest = "0.069" src = "0.065">-0.004</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_InterruptManager/int_pointer_w_2</twSrc><twDest BELType='RAM'>i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X83Y89.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X83Y89.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>i_Core/i_InterruptManager/int_pointer_w&lt;2&gt;</twComp><twBEL>i_Core/i_InterruptManager/int_pointer_w_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X84Y89.D3</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twFalling">0.299</twDelInfo><twComp>i_Core/i_InterruptManager/int_pointer_w&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X84Y89.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.172</twDelInfo><twComp>i_Core/i_InterruptManager/_n0165&lt;5&gt;</twComp><twBEL>i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1</twBEL></twPathDel><twLogDel>0.026</twLogDel><twRouteDel>0.299</twRouteDel><twTotDel>0.325</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>8.0</twPctLog><twPctRoute>92.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMB (SLICE_X84Y89.D3), 1 path
</twPathRptBanner><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.321</twSlack><twSrc BELType="FF">i_Core/i_InterruptManager/int_pointer_w_2</twSrc><twDest BELType="RAM">i_Core/i_InterruptManager/Mram_int_fifo1_RAMB</twDest><twTotPathDel>0.325</twTotPathDel><twClkSkew dest = "0.069" src = "0.065">-0.004</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_InterruptManager/int_pointer_w_2</twSrc><twDest BELType='RAM'>i_Core/i_InterruptManager/Mram_int_fifo1_RAMB</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X83Y89.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X83Y89.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>i_Core/i_InterruptManager/int_pointer_w&lt;2&gt;</twComp><twBEL>i_Core/i_InterruptManager/int_pointer_w_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X84Y89.D3</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twFalling">0.299</twDelInfo><twComp>i_Core/i_InterruptManager/int_pointer_w&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X84Y89.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.172</twDelInfo><twComp>i_Core/i_InterruptManager/_n0165&lt;5&gt;</twComp><twBEL>i_Core/i_InterruptManager/Mram_int_fifo1_RAMB</twBEL></twPathDel><twLogDel>0.026</twLogDel><twRouteDel>0.299</twRouteDel><twTotDel>0.325</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>8.0</twPctLog><twPctRoute>92.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="29"><twPinLimitBanner>Component Switching Limit Checks: TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="30" type="MINPERIOD" name="Tbcper_I" slack="5.833" period="8.333" constraintValue="8.333" deviceLimit="2.500" freqLimit="400.000" physResource="Si57x_BUFG/I0" logResource="Si57x_BUFG/I0" locationPin="BUFGMUX_X2Y4.I0" clockNet="Si57x"/><twPinLimit anchorID="31" type="MINPERIOD" name="Tcp" slack="6.934" period="8.333" constraintValue="8.333" deviceLimit="1.399" freqLimit="714.796" physResource="i_Core/i_Debouncer/BouncingSignal_x&lt;2&gt;/CLK" logResource="i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2/CLK" locationPin="SLICE_X22Y33.CLK" clockNet="Si57x_BUFG"/><twPinLimit anchorID="32" type="MINPERIOD" name="Tcp" slack="6.934" period="8.333" constraintValue="8.333" deviceLimit="1.399" freqLimit="714.796" physResource="i_Core/VmeSysReset_dx&lt;1&gt;/CLK" logResource="i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0/CLK" locationPin="SLICE_X72Y108.CLK" clockNet="Si57x_BUFG"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="33">0</twUnmetConstCnt><twDataSheet anchorID="34" twNameLen="15"><twClk2SUList anchorID="35" twDestWidth="9"><twDest>Si57x_ik</twDest><twClk2SU><twSrc>Si57x_ik</twSrc><twRiseRise>8.144</twRiseRise></twClk2SU><twClk2SU><twSrc>Si57x_ikn</twSrc><twRiseRise>8.144</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="36" twDestWidth="9"><twDest>Si57x_ikn</twDest><twClk2SU><twSrc>Si57x_ik</twSrc><twRiseRise>8.144</twRiseRise></twClk2SU><twClk2SU><twSrc>Si57x_ikn</twSrc><twRiseRise>8.144</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="37"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>44725</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>4167</twConnCnt></twConstCov><twStats anchorID="38"><twMinPer>8.144</twMinPer><twFootnote number="1" /><twMaxFreq>122.790</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Thu Dec 16 18:44:35 2010 </twTimestamp></twFoot><twClientInfo anchorID="39"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 273 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.ucf 0 → 100644
View file @ 23b1b4b5
NET "DdrA_ob14[0]" LOC = P24;
NET "DdrA_ob14[1]" LOC = P26;
NET "DdrA_ob14[2]" LOC = P22;
NET "DdrA_ob14[4]" LOC = N24;
NET "DdrA_ob14[7]" LOC = P21;
NET "DdrA_ob14[8]" LOC = P17;
NET "DdrA_ob14[9]" LOC = P19;
NET "DdrA_ob14[10]" LOC = N23;
NET "DdrA_ob14[11]" LOC = N20;
NET "DdrA_ob14[12]" LOC = N22;
NET "DdrA_ob14[13]" LOC = L23;
NET "DdrBA_ob3[0]" LOC = R20;
NET "DdrBA_ob3[1]" LOC = R21;
NET "DdrBA_ob3[2]" LOC = R19;
NET "DdrCkE_o" LOC = N21;
NET "DdrCk_ok" LOC = R23;
NET "DdrReset_or" LOC = N19;
NET "DdrWe_o" LOC = R18;
NET "DdsD_ob16[0]" LOC = F10;
NET "DdsD_ob16[1]" LOC = F9;
NET "DdsD_ob16[2]" LOC = G9;
NET "DdsD_ob16[3]" LOC = E8;
NET "DdsD_ob16[4]" LOC = F7;
NET "DdsD_ob16[5]" LOC = G7;
NET "DdsD_ob16[6]" LOC = E6;
NET "DdsD_ob16[7]" LOC = F6;
NET "DdsD_ob16[8]" LOC = E10;
NET "DdsD_ob16[9]" LOC = C5;
NET "DdsD_ob16[10]" LOC = D5;
NET "DdsD_ob16[11]" LOC = E5;
NET "DdsD_ob16[12]" LOC = F5;
NET "DdsD_ob16[13]" LOC = G6;
NET "DdsD_ob16[14]" LOC = C3;
NET "DdsD_ob16[15]" LOC = K12;
NET "DdsDrCtl_o" LOC = H12;
NET "DdsDrHold_o" LOC = G12;
NET "DdsDrOver_i" LOC = G13;
NET "DdsF_ob2[0]" LOC = B3;
NET "DdsF_ob2[1]" LOC = A2;
NET "DdsIOUpdate_io" LOC = B5;
NET "DdsIoReset_or" LOC = G11;
NET "DdsMasterRst_or" LOC = H9;
NET "DdsOsk_o" LOC = A5;
NET "DdsPdClk_ik" LOC = D13;
NET "DdsPllLock_i" LOC = G10;
NET "DdsPowerDown_o" LOC = H10;
NET "DdsProfile_ob3[0]" LOC = A4;
NET "DdsProfile_ob3[1]" LOC = B4;
NET "DdsProfile_ob3[2]" LOC = A3;
NET "DdsRamSwpOvr_i" LOC = J11;
NET "DdsSClk_o" LOC = F11;
NET "DdsSDio_io" LOC = E12;
NET "DdsSDo_i" LOC = F12;
NET "DdsSyncClk_ik" LOC = E13;
NET "DdsSyncIn_ok" LOC = B14;
NET "DdsSyncIn_okn" LOC = A14;
NET "DdsSyncOut_ik" LOC = C13;
NET "DdsSyncOut_ikn" LOC = A13;
NET "DdsSyncSmpErr_i" LOC = H8;
NET "DdsTxEnable_o" LOC = G8;
NET "Si57xOe_o" LOC = E18;
NET "Si57xSCl_ok" LOC = F14;
NET "Si57xSDa_io" LOC = E14;
NET "Si57x_ik" LOC = B12;
NET "Si57x_ikn" LOC = A12;
NET "VmeADirVfcToVme_o" LOC = F20;
NET "VmeAOeN_oen" LOC = F19;
NET "VmeAm_ib6[0]" LOC = G19;
NET "VmeAm_ib6[1]" LOC = G16;
NET "VmeAm_ib6[2]" LOC = H19;
NET "VmeAm_ib6[3]" LOC = H18;
NET "VmeAm_ib6[4]" LOC = H17;
NET "VmeAm_ib6[5]" LOC = J17;
NET "VmeD_iob32[0]" LOC = A22;
NET "VmeD_iob32[1]" LOC = B22;
NET "VmeD_iob32[2]" LOC = A23;
NET "VmeD_iob32[3]" LOC = B23;
NET "VmeD_iob32[16]" LOC = H13;
NET "VmeD_iob32[17]" LOC = H15;
NET "VmeD_iob32[18]" LOC = J15;
NET "VmeIack_in" LOC = F18;
NET "VmeP0BunchSelectDir_o" LOC = G15;
NET "VmeP0BunchSelectOe_o" LOC = F15;
NET "VmeP0BuslineDir_o" LOC = J12;
NET "VmeP0BuslineOe_o" LOC = J13;
NET "VmeP0HwHighByteDir_o" LOC = H14;
NET "VmeP0HwHighByteOe_o" LOC = K14;
NET "VmeP0HwLowByteDir_o" LOC = F16;
NET "VmeP0HwLowByteOe_o" LOC = E16;
NET "VmeRetryOe_oe" LOC = F17;
NET "VmeRetry_on" LOC = G17;
NET "VmeSysReset_in" LOC = J16;
NET "VmeTck_i" LOC = D22;
NET "VmeTdi_i" LOC = C21;
NET "VmeTdo_o" LOC = B21;
NET "VmeTms_i" LOC = D21;
NET "VmeWrite_in" LOC = E20;
NET "DdrA_ob14[3]" LOC = T22;
NET "DdrA_ob14[5]" LOC = U23;
NET "DdrA_ob14[6]" LOC = U24;
NET "DdrCAS_o" LOC = R26;
NET "DdrCk_okn" LOC = R24;
NET "DdrDQ_iob16[4]" LOC = U25;
NET "DdrDQ_iob16[5]" LOC = U26;
NET "DdrDQ_iob16[6]" LOC = T24;
NET "DdrDQ_iob16[7]" LOC = T26;
NET "DdrLDM_o" LOC = W24;
NET "DdrODT_o" LOC = T23;
NET "DdrRAS_o" LOC = R25;
NET "DdrUDM_o" LOC = V23;
NET "AFpgaProgCsi_io" LOC = AB4;
NET "AFpgaProgD_iob8[0]" LOC = AB5;
NET "AFpgaProgD_iob8[2]" LOC = AA3;
NET "AFpgaProgM_iob2[1]" LOC = AA4;
NET "AFpgaProgRdWr_io" LOC = Y5;
NET "DdrDQ_iob16[0]" LOC = AA25;
NET "DdrDQ_iob16[1]" LOC = AA26;
NET "DdrDQ_iob16[2]" LOC = W25;
NET "DdrDQ_iob16[3]" LOC = W26;
NET "DdrDQ_iob16[8]" LOC = AD24;
NET "DdrDQ_iob16[9]" LOC = AD26;
NET "DdrDQ_iob16[10]" LOC = AB24;
NET "DdrDQ_iob16[11]" LOC = AB26;
NET "DdrDQ_iob16[12]" LOC = Y24;
NET "DdrDQ_iob16[13]" LOC = Y26;
NET "DdrDQ_iob16[14]" LOC = AE25;
NET "DdrDQ_iob16[15]" LOC = AE26;
NET "DdrLDQS_io" LOC = V24;
NET "DdrLDQS_ion" LOC = V26;
NET "DdrUDQS_io" LOC = AC25;
NET "DdrUDQS_ion" LOC = AC26;
NET "SysAppSlow_iob2[1]" LOC = AC4;
NET "DdrA_ob14[0]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[1]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[2]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[3]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[4]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[5]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[6]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[7]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[8]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[9]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[10]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[11]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[12]" IOSTANDARD = SSTL15_II;
NET "DdrA_ob14[13]" IOSTANDARD = SSTL15_II;
NET "DdrBA_ob3[0]" IOSTANDARD = SSTL15_II;
NET "DdrBA_ob3[1]" IOSTANDARD = SSTL15_II;
NET "DdrBA_ob3[2]" IOSTANDARD = SSTL15_II;
NET "DdrCAS_o" IOSTANDARD = SSTL15_II;
NET "DdrCkE_o" IOSTANDARD = SSTL15_II;
NET "DdrCk_ok" IOSTANDARD = DIFF_SSTL15_II;
NET "DdrCk_okn" IOSTANDARD = DIFF_SSTL15_II;
NET "DdrDQ_iob16[0]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[1]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[2]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[3]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[4]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[5]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[6]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[7]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[8]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[9]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[10]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[11]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[12]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[13]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[14]" IOSTANDARD = SSTL15_II;
NET "DdrDQ_iob16[15]" IOSTANDARD = SSTL15_II;
NET "DdrLDM_o" IOSTANDARD = SSTL15_II;
NET "DdrLDQS_io" IOSTANDARD = DIFF_SSTL15_II;
NET "DdrLDQS_ion" IOSTANDARD = DIFF_SSTL15_II;
NET "DdrODT_o" IOSTANDARD = SSTL15_II;
NET "DdrRAS_o" IOSTANDARD = SSTL15_II;
NET "DdrReset_or" IOSTANDARD = SSTL15_II;
NET "DdrUDM_o" IOSTANDARD = SSTL15_II;
NET "DdrUDQS_io" IOSTANDARD = DIFF_SSTL15_II;
NET "DdrUDQS_ion" IOSTANDARD = DIFF_SSTL15_II;
NET "DdrWe_o" IOSTANDARD = SSTL15_II;
NET "DdsD_ob16[0]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[1]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[2]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[3]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[4]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[5]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[6]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[7]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[8]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[9]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[10]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[11]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[12]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[13]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[14]" IOSTANDARD = LVCMOS33;
NET "DdsD_ob16[15]" IOSTANDARD = LVCMOS33;
NET "DdsDrCtl_o" IOSTANDARD = LVCMOS33;
NET "DdsDrHold_o" IOSTANDARD = LVCMOS33;
NET "DdsDrOver_i" IOSTANDARD = LVCMOS33;
NET "DdsF_ob2[0]" IOSTANDARD = LVCMOS33;
NET "DdsF_ob2[1]" IOSTANDARD = LVCMOS33;
NET "DdsIOUpdate_io" IOSTANDARD = LVCMOS33;
NET "DdsIoReset_or" IOSTANDARD = LVCMOS33;
NET "DdsMasterRst_or" IOSTANDARD = LVCMOS33;
NET "DdsOsk_o" IOSTANDARD = LVCMOS33;
NET "DdsPdClk_ik" IOSTANDARD = LVCMOS33;
NET "DdsPllLock_i" IOSTANDARD = LVCMOS33;
NET "DdsPowerDown_o" IOSTANDARD = LVCMOS33;
NET "DdsProfile_ob3[0]" IOSTANDARD = LVCMOS33;
NET "DdsProfile_ob3[1]" IOSTANDARD = LVCMOS33;
NET "DdsProfile_ob3[2]" IOSTANDARD = LVCMOS33;
NET "DdsRamSwpOvr_i" IOSTANDARD = LVCMOS33;
NET "DdsSClk_o" IOSTANDARD = LVCMOS33;
NET "DdsSDio_io" IOSTANDARD = LVCMOS33;
NET "DdsSDo_i" IOSTANDARD = LVCMOS33;
NET "DdsSyncClk_ik" IOSTANDARD = LVCMOS33;
NET "DdsSyncIn_ok" IOSTANDARD = LVDS_33;
NET "DdsSyncIn_okn" IOSTANDARD = LVDS_33;
NET "DdsSyncOut_ik" IOSTANDARD = LVDS_33;
NET "DdsSyncOut_ikn" IOSTANDARD = LVDS_33;
NET "DdsSyncSmpErr_i" IOSTANDARD = LVCMOS33;
NET "DdsTxEnable_o" IOSTANDARD = LVCMOS33;
NET "Si57xOe_o" IOSTANDARD = LVCMOS33;
NET "Si57xSCl_ok" IOSTANDARD = LVCMOS33;
NET "Si57xSDa_io" IOSTANDARD = LVCMOS33;
NET "Si57x_ik" IOSTANDARD = LVDS_33;
NET "Si57x_ikn" IOSTANDARD = LVDS_33;
NET "VmeADirVfcToVme_o" IOSTANDARD = LVCMOS33;
NET "VmeAOeN_oen" IOSTANDARD = LVCMOS33;
NET "VmeAm_ib6[0]" IOSTANDARD = LVCMOS33;
NET "VmeAm_ib6[1]" IOSTANDARD = LVCMOS33;
NET "VmeAm_ib6[2]" IOSTANDARD = LVCMOS33;
NET "VmeAm_ib6[3]" IOSTANDARD = LVCMOS33;
NET "VmeAm_ib6[4]" IOSTANDARD = LVCMOS33;
NET "VmeAm_ib6[5]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[0]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[1]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[2]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[3]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[4]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[5]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[6]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[7]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[8]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[9]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[10]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[11]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[12]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[13]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[14]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[15]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[16]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[17]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[18]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[19]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[20]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[21]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[22]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[23]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[24]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[25]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[26]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[27]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[28]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[29]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[30]" IOSTANDARD = LVCMOS33;
NET "VmeD_iob32[31]" IOSTANDARD = LVCMOS33;
NET "VmeIack_in" IOSTANDARD = LVCMOS33;
NET "VmeP0BunchSelectDir_o" IOSTANDARD = LVCMOS33;
NET "VmeP0BunchSelectOe_o" IOSTANDARD = LVCMOS33;
NET "VmeP0BuslineDir_o" IOSTANDARD = LVCMOS33;
NET "VmeP0BuslineOe_o" IOSTANDARD = LVCMOS33;
NET "VmeP0HwHighByteDir_o" IOSTANDARD = LVCMOS33;
NET "VmeP0HwHighByteOe_o" IOSTANDARD = LVCMOS33;
NET "VmeP0HwLowByteDir_o" IOSTANDARD = LVCMOS33;
NET "VmeP0HwLowByteOe_o" IOSTANDARD = LVCMOS33;
NET "VmeRetryOe_oe" IOSTANDARD = LVCMOS33;
NET "VmeRetry_on" IOSTANDARD = LVCMOS33;
NET "VmeSysReset_in" IOSTANDARD = LVCMOS33;
NET "VmeTck_i" IOSTANDARD = LVCMOS33;
NET "VmeTdi_i" IOSTANDARD = LVCMOS33;
NET "VmeTdo_o" IOSTANDARD = LVCMOS33;
NET "VmeTms_i" IOSTANDARD = LVCMOS33;
NET "VmeWrite_in" IOSTANDARD = LVCMOS33;
NET "AFpgaProgClk_io" LOC = AB3;
NET "AFpgaProgD_iob8[1]" LOC = Y3;
NET "AFpgaProgD_iob8[3]" LOC = V3;
NET "AFpgaProgD_iob8[5]" LOC = W2;
NET "AFpgaProgD_iob8[6]" LOC = V5;
NET "AFpgaProgD_iob8[7]" LOC = W5;
NET "AFpgaProgDone_io" LOC = AC3;
NET "AFpgaProgInit_io" LOC = U8;
NET "AFpgaProgM_iob2[0]" LOC = AD3;
NET "Fmc1PGC2M_in" LOC = W1;
NET "Fmc1PrsntM2C_in" LOC = V1;
NET "Fmc2PGC2M_in" LOC = U2;
NET "Fmc2PrsntM2C_in" LOC = U1;
NET "FpLed_onb8[5]" LOC = U3;
NET "FpLed_onb8[6]" LOC = U4;
NET "PcbRev_ib8[0]" LOC = AA1;
NET "PcbRev_ib8[1]" LOC = AA2;
NET "PcbRev_ib8[2]" LOC = AB1;
NET "PcbRev_ib8[3]" LOC = AC1;
NET "PcbRev_ib8[4]" LOC = AC2;
NET "PcbRev_ib8[5]" LOC = AD1;
NET "PcbRev_ib8[6]" LOC = AE1;
NET "PcbRev_ib8[7]" LOC = AE2;
NET "PllFmc12SFpga_ik" LOC = V4;
NET "PllFmc12SFpga_ikn" LOC = W3;
NET "PllFmc22SFpga_ik" LOC = T3;
NET "PllFmc22SFpga_ikn" LOC = T1;
NET "Switch_ib2[0]" LOC = V6;
NET "Switch_ib2[1]" LOC = V7;
NET "SysAppClk_ok" LOC = R7;
NET "SysAppClk_ik" LOC = R6;
NET "SysAppSlow_iob2[2]" LOC = T6;
NET "AFpgaProgD_iob8[4]" LOC = U5;
NET "AFpgaProgProgram_o" LOC = U7;
NET "FlashAFpgaClk_ok" LOC = AC22;
NET "FlashAFpgaCs_on" LOC = AB17;
NET "FlashAFpgaD_o" LOC = AF22;
NET "FlashAFpgaQ_i" LOC = AA18;
NET "FlashSFpgaClk_ok" LOC = AE24;
NET "FlashSFpgaCs_on" LOC = AF3;
NET "FlashSFpgaD_o" LOC = AF23;
NET "FlashSFpgaQ_i" LOC = AD23;
NET "Fmc1SCl_ok" LOC = N1;
NET "Fmc1SDa_io" LOC = N2;
NET "Fmc2SCl_ok" LOC = M1;
NET "Fmc2SDa_io" LOC = L1;
NET "FpLed_onb8[0]" LOC = P5;
NET "FpLed_onb8[1]" LOC = R4;
NET "FpLed_onb8[2]" LOC = R3;
NET "FpLed_onb8[3]" LOC = P6;
NET "FpLed_onb8[4]" LOC = R5;
NET "FpLed_onb8[7]" LOC = T4;
NET "ManualAddress_ib5[0]" LOC = R8;
NET "ManualAddress_ib5[1]" LOC = T8;
NET "ManualAddress_ib5[2]" LOC = R9;
NET "ManualAddress_ib5[3]" LOC = T9;
NET "ManualAddress_ib5[4]" LOC = P10;
NET "PllDacClrn_orn" LOC = Y21;
NET "PllDacDin_o" LOC = AB21;
NET "PllDacDout_i" LOC = Y20;
NET "PllDacLDac_on" LOC = AA22;
NET "PllDacSClk_ok" LOC = AA21;
NET "PllDacSynch_on" LOC = AB22;
NET "PllDds2SFpga_ik" LOC = R2;
NET "PllDds2SFpga_ikn" LOC = R1;
NET "PllDdsCs_on" LOC = D1;
NET "PllDdsLd_i" LOC = G2;
NET "PllDdsPd_on" LOC = F3;
NET "PllDdsRefMon_i" LOC = G1;
NET "PllDdsSClk_ok" LOC = E2;
NET "PllDdsSdo_i" LOC = D3;
NET "PllDdsStatus_i" LOC = F1;
NET "PllDdsSynch_on" LOC = E1;
NET "PllFmc1Cs_on" LOC = AD6;
NET "PllFmc1Ld_i" LOC = AA9;
NET "PllFmc1Pd_on" LOC = AD4;
NET "PllFmc1Ref1_ok" LOC = AA11;
NET "PllFmc1RefMon_i" LOC = AA10;
NET "PllFmc1RefSel_o" LOC = AA8;
NET "PllFmc1Reset_orn" LOC = AC5;
NET "PllFmc1SClk_ok" LOC = AA6;
NET "PllFmc1SDio_io" LOC = AD5;
NET "PllFmc1Sdo_i" LOC = AC6;
NET "PllFmc1Status_i" LOC = AB9;
NET "PllFmc1Synch_on" LOC = AB7;
NET "PllFmc2Cs_on" LOC = U13;
NET "PllFmc2Ld_i" LOC = Y13;
NET "PllFmc2Pd_on" LOC = V16;
NET "PllFmc2Ref1_ok" LOC = Y12;
NET "PllFmc2RefMon_i" LOC = Y11;
NET "PllFmc2RefSel_o" LOC = V13;
NET "PllFmc2Reset_orn" LOC = U15;
NET "PllFmc2SClk_ok" LOC = V11;
NET "PllFmc2SDio_io" LOC = V15;
NET "PllFmc2Sdo_i" LOC = V14;
NET "PllFmc2Status_i" LOC = W12;
NET "PllFmc2Synch_on" LOC = V12;
NET "PllSys2SFpga_ik" LOC = AE13;
NET "PllSys2SFpga_ikn" LOC = AF13;
NET "PllSysCs_on" LOC = AB11;
NET "PllSysLd_i" LOC = AC14;
NET "PllSysPd_on" LOC = AF4;
NET "PllSysRef12_ok" LOC = AA15;
NET "PllSysRef12_okn" LOC = AB15;
NET "PllSysRefMon_i" LOC = AD14;
NET "PllSysRefSel_o" LOC = AB13;
NET "PllSysReset_orn" LOC = AE5;
NET "PllSysSClk_ok" LOC = AA12;
NET "PllSysSDio_io" LOC = AF5;
NET "PllSysSdo_i" LOC = AF6;
NET "PllSysStatus_i" LOC = AB14;
NET "PllSysSynch_on" LOC = AA13;
NET "PushButton_ion" LOC = AA7;
NET "Sfp2LoS_i" LOC = J3;
NET "Sfp2ModeDef0_i" LOC = H3;
NET "Sfp2RateSelect" LOC = J4;
NET "UseGa_i" LOC = R10;
NET "VAdcCs_on" LOC = W7;
NET "VAdcDin_o" LOC = Y9;
NET "VAdcDout_i" LOC = W9;
NET "VAdcSClk_ok" LOC = W8;
NET "VAdjCs_on" LOC = H1;
NET "VAdjDin_o" LOC = J1;
NET "VAdjInhibit_ozn" LOC = L2;
NET "VAdjSClk_ok" LOC = J2;
NET "VAdjSpi_o" LOC = K1;
NET "VcTcXo_ik" LOC = AF14;
NET "VmeAs_in" LOC = M8;
NET "VmeBerr_o" LOC = V18;
NET "VmeDDirVfcToVme_o" LOC = L9;
NET "VmeD_iob32[19]" LOC = W20;
NET "VmeD_iob32[20]" LOC = W19;
NET "VmeD_iob32[21]" LOC = AB19;
NET "VmeD_iob32[22]" LOC = AA19;
NET "VmeD_iob32[23]" LOC = W18;
NET "VmeD_iob32[24]" LOC = Y17;
NET "VmeD_iob32[25]" LOC = AA17;
NET "VmeD_iob32[26]" LOC = W17;
NET "VmeD_iob32[27]" LOC = W16;
NET "VmeD_iob32[28]" LOC = AA16;
NET "VmeD_iob32[29]" LOC = Y16;
NET "VmeD_iob32[30]" LOC = Y15;
NET "VmeD_iob32[31]" LOC = W14;
NET "VmeIackIn_in" LOC = W10;
NET "VmeIackOut_on" LOC = V10;
NET "VmeIrq_ob7[1]" LOC = L7;
NET "VmeIrq_ob7[4]" LOC = M3;
NET "VmeIrq_ob7[5]" LOC = M4;
NET "VmeIrq_ob7[6]" LOC = N3;
NET "VmeIrq_ob7[7]" LOC = M6;
NET "VmeP0LvdsBunchClkIn_i" LOC = AE15;
NET "VmeP0LvdsBunchClkOut_o" LOC = AF15;
NET "VmeSysClk_ik" LOC = L8;
NET "WRLoS_i" LOC = L6;
NET "WRModeDef0_i" LOC = L3;
NET "WRModeDef2_io" LOC = K3;
NET "WRRateSelect_o" LOC = L4;
NET "WRTxDisable_o" LOC = K5;
NET "WRTxFault_i" LOC = J5;
NET "FlashAFpgaClk_ok" IOSTANDARD = LVCMOS33;
NET "FlashAFpgaCs_on" IOSTANDARD = LVCMOS33;
NET "FlashAFpgaD_o" IOSTANDARD = LVCMOS33;
NET "FlashAFpgaQ_i" IOSTANDARD = LVCMOS33;
NET "FlashSFpgaClk_ok" IOSTANDARD = LVCMOS33;
NET "FlashSFpgaCs_on" IOSTANDARD = LVCMOS33;
NET "FlashSFpgaD_o" IOSTANDARD = LVCMOS33;
NET "FlashSFpgaQ_i" IOSTANDARD = LVCMOS33;
NET "PllDacClrn_orn" IOSTANDARD = LVCMOS33;
NET "PllDacDin_o" IOSTANDARD = LVCMOS33;
NET "PllDacDout_i" IOSTANDARD = LVCMOS33;
NET "PllDacLDac_on" IOSTANDARD = LVCMOS33;
NET "PllDacSClk_ok" IOSTANDARD = LVCMOS33;
NET "PllDacSynch_on" IOSTANDARD = LVCMOS33;
NET "PllFmc1Cs_on" IOSTANDARD = LVCMOS33;
NET "PllFmc1Ld_i" IOSTANDARD = LVCMOS33;
NET "PllFmc1Pd_on" IOSTANDARD = LVCMOS33;
NET "PllFmc1Ref1_ok" IOSTANDARD = LVCMOS33;
NET "PllFmc1RefMon_i" IOSTANDARD = LVCMOS33;
NET "PllFmc1RefSel_o" IOSTANDARD = LVCMOS33;
NET "PllFmc1Reset_orn" IOSTANDARD = LVCMOS33;
NET "PllFmc1SClk_ok" IOSTANDARD = LVCMOS33;
NET "PllFmc1SDio_io" IOSTANDARD = LVCMOS33;
NET "PllFmc1Sdo_i" IOSTANDARD = LVCMOS33;
NET "PllFmc1Status_i" IOSTANDARD = LVCMOS33;
NET "PllFmc1Synch_on" IOSTANDARD = LVCMOS33;
NET "PllFmc2Cs_on" IOSTANDARD = LVCMOS33;
NET "PllFmc2Ld_i" IOSTANDARD = LVCMOS33;
NET "PllFmc2Pd_on" IOSTANDARD = LVCMOS33;
NET "PllFmc2Ref1_ok" IOSTANDARD = LVCMOS33;
NET "PllFmc2RefMon_i" IOSTANDARD = LVCMOS33;
NET "PllFmc2RefSel_o" IOSTANDARD = LVCMOS33;
NET "PllFmc2Reset_orn" IOSTANDARD = LVCMOS33;
NET "PllFmc2SClk_ok" IOSTANDARD = LVCMOS33;
NET "PllFmc2SDio_io" IOSTANDARD = LVCMOS33;
NET "PllFmc2Sdo_i" IOSTANDARD = LVCMOS33;
NET "PllFmc2Status_i" IOSTANDARD = LVCMOS33;
NET "PllFmc2Synch_on" IOSTANDARD = LVCMOS33;
NET "PllSys2SFpga_ik" IOSTANDARD = LVDS_33;
NET "PllSys2SFpga_ikn" IOSTANDARD = LVDS_33;
NET "PllSysCs_on" IOSTANDARD = LVCMOS33;
NET "PllSysLd_i" IOSTANDARD = LVCMOS33;
NET "PllSysPd_on" IOSTANDARD = LVCMOS33;
NET "PllSysRef12_ok" IOSTANDARD = LVDS_33;
NET "PllSysRef12_okn" IOSTANDARD = LVDS_33;
NET "PllSysRefMon_i" IOSTANDARD = LVCMOS33;
NET "PllSysRefSel_o" IOSTANDARD = LVCMOS33;
NET "PllSysReset_orn" IOSTANDARD = LVCMOS33;
NET "PllSysSClk_ok" IOSTANDARD = LVCMOS33;
NET "PllSysSDio_io" IOSTANDARD = LVCMOS33;
NET "PllSysSdo_i" IOSTANDARD = LVCMOS33;
NET "PllSysStatus_i" IOSTANDARD = LVCMOS33;
NET "PllSysSynch_on" IOSTANDARD = LVCMOS33;
NET "PushButton_ion" IOSTANDARD = LVCMOS33;
NET "VAdcCs_on" IOSTANDARD = LVCMOS33;
NET "VAdcDin_o" IOSTANDARD = LVCMOS33;
NET "VAdcDout_i" IOSTANDARD = LVCMOS33;
NET "VAdcSClk_ok" IOSTANDARD = LVCMOS33;
NET "VcTcXo_ik" IOSTANDARD = LVCMOS33;
NET "VmeBerr_o" IOSTANDARD = LVCMOS33;
NET "VmeIackIn_in" IOSTANDARD = LVCMOS33;
NET "VmeIackOut_on" IOSTANDARD = LVCMOS33;
NET "VmeP0LvdsBunchClkIn_i" IOSTANDARD = LVCMOS33;
NET "VmeP0LvdsBunchClkOut_o" IOSTANDARD = LVCMOS33;
NET "FpGpIo1OutputMode_o" LOC = C1;
NET "FpGpIo2OutputMode_o" LOC = C2;
NET "FpGpIo34OutputMode_o" LOC = B1;
NET "PllDdsReset_orn" LOC = E3;
NET "PllDdsSDio_io" LOC = E4;
NET "Sfp2ModeDef1_i" LOC = H5;
NET "Sfp2ModeDef2_io" LOC = H6;
NET "Sfp2TxDisable_o" LOC = G3;
NET "Sfp2TxFault_i" LOC = G4;
NET "TempIdDQ_io" LOC = B2;
NET "VmeA_iob31[1]" LOC = M24;
NET "VmeA_iob31[2]" LOC = M21;
NET "VmeA_iob31[3]" LOC = L21;
NET "VmeA_iob31[4]" LOC = K22;
NET "VmeA_iob31[5]" LOC = K24;
NET "VmeA_iob31[6]" LOC = K21;
NET "VmeA_iob31[7]" LOC = J22;
NET "VmeA_iob31[8]" LOC = J24;
NET "VmeA_iob31[9]" LOC = J23;
NET "VmeA_iob31[10]" LOC = H21;
NET "VmeA_iob31[11]" LOC = H24;
NET "VmeA_iob31[12]" LOC = H22;
NET "VmeA_iob31[13]" LOC = G24;
NET "VmeA_iob31[14]" LOC = G23;
NET "VmeA_iob31[15]" LOC = F23;
NET "VmeA_iob31[16]" LOC = F24;
NET "VmeA_iob31[17]" LOC = F22;
NET "VmeA_iob31[18]" LOC = E24;
NET "VmeA_iob31[19]" LOC = E23;
NET "VmeA_iob31[20]" LOC = C24;
NET "VmeA_iob31[21]" LOC = D23;
NET "VmeA_iob31[22]" LOC = D24;
NET "VmeA_iob31[23]" LOC = N26;
NET "VmeA_iob31[24]" LOC = K18;
NET "VmeA_iob31[25]" LOC = J20;
NET "VmeA_iob31[26]" LOC = K19;
NET "VmeA_iob31[27]" LOC = K20;
NET "VmeA_iob31[28]" LOC = L19;
NET "VmeA_iob31[29]" LOC = L20;
NET "VmeA_iob31[30]" LOC = M18;
NET "VmeA_iob31[31]" LOC = M19;
NET "VmeDOeN_oen" LOC = K9;
NET "VmeD_iob32[4]" LOC = B24;
NET "VmeD_iob32[5]" LOC = A25;
NET "VmeD_iob32[6]" LOC = B25;
NET "VmeD_iob32[7]" LOC = B26;
NET "VmeD_iob32[8]" LOC = C25;
NET "VmeD_iob32[9]" LOC = C26;
NET "VmeD_iob32[10]" LOC = D26;
NET "VmeD_iob32[11]" LOC = E25;
NET "VmeD_iob32[12]" LOC = E26;
NET "VmeD_iob32[13]" LOC = F26;
NET "VmeD_iob32[14]" LOC = G25;
NET "VmeD_iob32[15]" LOC = G26;
NET "VmeDs_inb2[1]" LOC = G20;
NET "VmeDs_inb2[2]" LOC = H20;
NET "VmeDtAckOe_oe" LOC = J9;
NET "VmeDtAck_on" LOC = N25;
NET "VmeGaP_in" LOC = J25;
NET "VmeGa_ib5n[0]" LOC = J26;
NET "VmeGa_ib5n[1]" LOC = K26;
NET "VmeGa_ib5n[2]" LOC = L25;
NET "VmeGa_ib5n[3]" LOC = L26;
NET "VmeGa_ib5n[4]" LOC = M26;
NET "VmeIrq_ob7[2]" LOC = J7;
NET "VmeIrq_ob7[3]" LOC = K7;
NET "VmeLword_io" LOC = M23;
NET "VmeP0LvdsTClkIn_i" LOC = L10;
NET "VmeP0LvdsTClkOut_o" LOC = K10;
NET "VmeTdoOe_oe" LOC = K8;
NET "VmeTrst_i" LOC = H26;
NET "WRModeDef1_i" LOC = K6;
NET "Fmc1SCl_ok" IOSTANDARD = LVCMOS33;
NET "Fmc1SDa_io" IOSTANDARD = LVCMOS33;
NET "Fmc2SCl_ok" IOSTANDARD = LVCMOS33;
NET "Fmc2SDa_io" IOSTANDARD = LVCMOS33;
NET "FpGpIo1OutputMode_o" IOSTANDARD = LVCMOS33;
NET "FpGpIo2OutputMode_o" IOSTANDARD = LVCMOS33;
NET "FpGpIo34OutputMode_o" IOSTANDARD = LVCMOS33;
NET "PllDdsCs_on" IOSTANDARD = LVCMOS33;
NET "PllDdsLd_i" IOSTANDARD = LVCMOS33;
NET "PllDdsPd_on" IOSTANDARD = LVCMOS33;
NET "PllDdsRefMon_i" IOSTANDARD = LVCMOS33;
NET "PllDdsReset_orn" IOSTANDARD = LVCMOS33;
NET "PllDdsSClk_ok" IOSTANDARD = LVCMOS33;
NET "PllDdsSDio_io" IOSTANDARD = LVCMOS33;
NET "PllDdsSdo_i" IOSTANDARD = LVCMOS33;
NET "PllDdsStatus_i" IOSTANDARD = LVCMOS33;
NET "PllDdsSynch_on" IOSTANDARD = LVCMOS33;
NET "Sfp2LoS_i" IOSTANDARD = LVCMOS33;
NET "Sfp2ModeDef0_i" IOSTANDARD = LVCMOS33;
NET "Sfp2ModeDef1_i" IOSTANDARD = LVCMOS33;
NET "Sfp2ModeDef2_io" IOSTANDARD = LVCMOS33;
NET "Sfp2RateSelect" IOSTANDARD = LVCMOS33;
NET "Sfp2TxDisable_o" IOSTANDARD = LVCMOS33;
NET "Sfp2TxFault_i" IOSTANDARD = LVCMOS33;
NET "TempIdDQ_io" IOSTANDARD = LVCMOS33;
NET "VAdjCs_on" IOSTANDARD = LVCMOS33;
NET "VAdjDin_o" IOSTANDARD = LVCMOS33;
NET "VAdjInhibit_ozn" IOSTANDARD = LVCMOS33;
NET "VAdjSClk_ok" IOSTANDARD = LVCMOS33;
NET "VAdjSpi_o" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[1]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[2]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[3]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[4]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[5]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[6]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[7]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[8]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[9]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[10]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[11]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[12]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[13]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[14]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[15]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[16]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[17]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[18]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[19]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[20]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[21]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[22]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[23]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[24]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[25]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[26]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[27]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[28]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[29]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[30]" IOSTANDARD = LVCMOS33;
NET "VmeA_iob31[31]" IOSTANDARD = LVCMOS33;
NET "VmeAs_in" IOSTANDARD = LVCMOS33;
NET "VmeDDirVfcToVme_o" IOSTANDARD = LVCMOS33;
NET "VmeDOeN_oen" IOSTANDARD = LVCMOS33;
NET "VmeDs_inb2[1]" IOSTANDARD = LVCMOS33;
NET "VmeDs_inb2[2]" IOSTANDARD = LVCMOS33;
NET "VmeDtAckOe_oe" IOSTANDARD = LVCMOS33;
NET "VmeDtAck_on" IOSTANDARD = LVCMOS33;
NET "VmeGaP_in" IOSTANDARD = LVCMOS33;
NET "VmeGa_ib5n[0]" IOSTANDARD = LVCMOS33;
NET "VmeGa_ib5n[1]" IOSTANDARD = LVCMOS33;
NET "VmeGa_ib5n[2]" IOSTANDARD = LVCMOS33;
NET "VmeGa_ib5n[3]" IOSTANDARD = LVCMOS33;
NET "VmeGa_ib5n[4]" IOSTANDARD = LVCMOS33;
NET "VmeIrq_ob7[1]" IOSTANDARD = LVCMOS33;
NET "VmeIrq_ob7[2]" IOSTANDARD = LVCMOS33;
NET "VmeIrq_ob7[3]" IOSTANDARD = LVCMOS33;
NET "VmeIrq_ob7[4]" IOSTANDARD = LVCMOS33;
NET "VmeIrq_ob7[5]" IOSTANDARD = LVCMOS33;
NET "VmeIrq_ob7[6]" IOSTANDARD = LVCMOS33;
NET "VmeIrq_ob7[7]" IOSTANDARD = LVCMOS33;
NET "VmeLword_io" IOSTANDARD = LVCMOS33;
NET "VmeP0LvdsTClkIn_i" IOSTANDARD = LVCMOS33;
NET "VmeP0LvdsTClkOut_o" IOSTANDARD = LVCMOS33;
NET "VmeSysClk_ik" IOSTANDARD = LVCMOS33;
NET "VmeTdoOe_oe" IOSTANDARD = LVCMOS33;
NET "VmeTrst_i" IOSTANDARD = LVCMOS33;
NET "WRLoS_i" IOSTANDARD = LVCMOS33;
NET "WRModeDef0_i" IOSTANDARD = LVCMOS33;
NET "WRModeDef1_i" IOSTANDARD = LVCMOS33;
NET "WRModeDef2_io" IOSTANDARD = LVCMOS33;
NET "WRRateSelect_o" IOSTANDARD = LVCMOS33;
NET "WRTxDisable_o" IOSTANDARD = LVCMOS33;
NET "WRTxFault_i" IOSTANDARD = LVCMOS33;
NET "VmeSysClk_ik" CLOCK_DEDICATED_ROUTE = "FALSE";
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/16
NET "Si57x_ik" TNM_NET = "Si57x_ik";
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 120 MHz HIGH 50 %;
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes 0 → 100644
View file @ 23b1b4b5
Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:10 2010
All signals are completely routed.
WARNING:ParHelpers:361 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
AFpgaProgClk_io_IBUF
AFpgaProgCsi_io_IBUF
AFpgaProgD_iob8<0>_IBUF
AFpgaProgD_iob8<1>_IBUF
AFpgaProgD_iob8<2>_IBUF
AFpgaProgD_iob8<3>_IBUF
AFpgaProgD_iob8<6>_IBUF
AFpgaProgInit_io_IBUF
AFpgaProgM_iob2<0>_IBUF
AFpgaProgM_iob2<1>_IBUF
AFpgaProgRdWr_io_IBUF
DdsDrOver_i_IBUF
DdsPdClk_ik_IBUF
DdsPllLock_i_IBUF
DdsRamSwpOvr_i_IBUF
DdsSDo_i_IBUF
DdsSyncClk_ik_IBUF
DdsSyncSmpErr_i_IBUF
Fmc1PrsntM2C_in_IBUF
Fmc2PrsntM2C_in_IBUF
PcbRev_ib8<0>_IBUF
PcbRev_ib8<1>_IBUF
PcbRev_ib8<2>_IBUF
PcbRev_ib8<3>_IBUF
PcbRev_ib8<4>_IBUF
PcbRev_ib8<5>_IBUF
PcbRev_ib8<6>_IBUF
PcbRev_ib8<7>_IBUF
PllDacDout_i_IBUF
Sfp2LoS_i_IBUF
Sfp2ModeDef0_i_IBUF
Sfp2TxFault_i_IBUF
TempIdDQ_io_IBUF
VmeAm_ib6<1>_IBUF
VmeAm_ib6<2>_IBUF
VmeDs_inb2<1>_IBUF
VmeDs_inb2<2>_IBUF
VmeP0LvdsBunchClkIn_i_IBUF
VmeP0LvdsTClkIn_i_IBUF
VmeTck_i_IBUF
VmeTdi_i_IBUF
VmeTms_i_IBUF
VmeTrst_i_IBUF
WRLoS_i_IBUF
WRModeDef0_i_IBUF
WRTxFault_i_IBUF
i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
trunk/firmware/XilinxISE/SystemFpga/SFpga.ut 0 → 100644
View file @ 23b1b4b5
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4
trunk/firmware/XilinxISE/SystemFpga/SFpga.xpi 0 → 100644
View file @ 23b1b4b5
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=YES
trunk/firmware/XilinxISE/SystemFpga/SFpga.xst 0 → 100644
View file @ 23b1b4b5
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn SFpga.prj
-ifmt mixed
-ofn SFpga
-ofmt NGC
-p xc6slx150t-3-fgg676
-top SFpga
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
trunk/firmware/XilinxISE/SystemFpga/SFpga_2010-12-16-17-18-34.twx 0 → 100644
View file @ 23b1b4b5
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_bitgen.xwbt 0 → 100644
View file @ 23b1b4b5
INTSTYLE=ise
INFILE=C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ncd
OUTFILE=C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.bit
FAMILY=Spartan6
PART=xc6slx150t-3fgg676
WORKINGDIR=C:\VFC_SVN\firmware\XilinxISE\SystemFpga
LICENSE=ISE
USER_INFO=174122088_179509804_641
trunk/firmware/XilinxISE/SystemFpga/SFpga_envsettings.html 0 → 100644
View file @ 23b1b4b5
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
</tr>
<tr>
<td>XILINX</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>C:\Xilinx\12.3\ISE_DS\EDK</td>
<td>C:\Xilinx\12.3\ISE_DS\EDK</td>
<td>C:\Xilinx\12.3\ISE_DS\EDK</td>
<td>C:\Xilinx\12.3\ISE_DS\EDK</td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>C:\Xilinx\12.3\ISE_DS\PlanAhead</td>
<td>C:\Xilinx\12.3\ISE_DS\PlanAhead</td>
<td>C:\Xilinx\12.3\ISE_DS\PlanAhead</td>
<td>C:\Xilinx\12.3\ISE_DS\PlanAhead</td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>SFpga.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ifmt</td>
<td>&nbsp;</td>
<td>mixed</td>
<td>Mixed</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>SFpga</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx150t-3-fgg676</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>SFpga</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Speed</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-power</td>
<td>Power Reduction</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>As_Optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>No</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>AllClockNets</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-dsp_utilization_ratio</td>
<td>DSP Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-reduce_control_sets</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_dsp48</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>100000</td>
<td>100000</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>16</td>
<td>16</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-dd</td>
<td>&nbsp;</td>
<td>_ngo</td>
<td>None</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx150t-fgg676-3</td>
<td>None</td>
</tr>
<tr>
<td>-uc</td>
<td>&nbsp;</td>
<td>SFpga.ucf</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Map Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>high</td>
</tr>
<tr>
<td>-xt</td>
<td>Extra Cost Tables</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>-ir</td>
<td>Use RLOC Constraints</td>
<td>OFF</td>
<td>OFF</td>
</tr>
<tr>
<td>-t</td>
<td>Starting Placer Cost Table (1-100) Map</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-lc</td>
<td>LUT Combining</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-o</td>
<td>&nbsp;</td>
<td>SFpga_map.ncd</td>
<td>None</td>
</tr>
<tr>
<td>-w</td>
<td>&nbsp;</td>
<td>true</td>
<td>false</td>
</tr>
<tr>
<td>-pr</td>
<td>Pack I/O Registers/Latches into IOBs</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx150t-fgg676-3</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Place and Route Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-mt</td>
<td>Enable Multi-Threading</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>std</td>
</tr>
<tr>
<td>-w</td>
<td>&nbsp;</td>
<td>true</td>
<td>false</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
</tr>
</TABLE>
</BODY> </HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_guide.ncd 0 → 100644
View file @ 23b1b4b5
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map 0 → 100644
View file @ 23b1b4b5
Release 12.3 Map M.70d (nt)
Xilinx Map Application Log File for Design 'SFpga'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr
off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Thu Dec 16 18:41:28 2010
Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
PllFmc12SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllFmc12SFpga_ikn connected to top level port
PllFmc12SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllFmc22SFpga_ik connected to top level port
PllFmc22SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllFmc22SFpga_ikn connected to top level port
PllFmc22SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllSys2SFpga_ik connected to top level port
PllSys2SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllSys2SFpga_ikn connected to top level port
PllSys2SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllDds2SFpga_ik connected to top level port
PllDds2SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllDds2SFpga_ikn connected to top level port
PllDds2SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal DdsSyncOut_ik connected to top level port
DdsSyncOut_ik has been removed.
WARNING:MapLib:701 - Signal DdsSyncOut_ikn connected to top level port
DdsSyncOut_ikn has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<15> connected to top level port
DdrDQ_iob16<15> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<14> connected to top level port
DdrDQ_iob16<14> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<13> connected to top level port
DdrDQ_iob16<13> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<12> connected to top level port
DdrDQ_iob16<12> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<11> connected to top level port
DdrDQ_iob16<11> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<10> connected to top level port
DdrDQ_iob16<10> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<9> connected to top level port
DdrDQ_iob16<9> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<8> connected to top level port
DdrDQ_iob16<8> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<7> connected to top level port
DdrDQ_iob16<7> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<6> connected to top level port
DdrDQ_iob16<6> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<5> connected to top level port
DdrDQ_iob16<5> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<4> connected to top level port
DdrDQ_iob16<4> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<3> connected to top level port
DdrDQ_iob16<3> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<2> connected to top level port
DdrDQ_iob16<2> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<1> connected to top level port
DdrDQ_iob16<1> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<0> connected to top level port
DdrDQ_iob16<0> has been removed.
WARNING:MapLib:701 - Signal Si57xSDa_io connected to top level port Si57xSDa_io
has been removed.
WARNING:MapLib:701 - Signal AFpgaProgDone_io connected to top level port
AFpgaProgDone_io has been removed.
WARNING:MapLib:701 - Signal DdsIOUpdate_io connected to top level port
DdsIOUpdate_io has been removed.
WARNING:MapLib:701 - Signal WRModeDef2_io connected to top level port
WRModeDef2_io has been removed.
WARNING:MapLib:701 - Signal Sfp2ModeDef2_io connected to top level port
Sfp2ModeDef2_io has been removed.
WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
VAdjInhibit_ozn has been removed.
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 28 secs
Total CPU time at the beginning of Placer: 26 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:fbd9bf1c) REAL time: 36 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:fbd9bf1c) REAL time: 36 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:fbd9bf1c) REAL time: 36 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
.......
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <VmeSysClk_ik> is placed at site <PAD550>. The corresponding
BUFG component <VmeSysClk_ik_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y9>.
There is only a select set of IOBs that can use the fast path to the Clocker
buffer, and they are not being used. You may want to analyze why this problem
exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <VmeSysClk_ik.PAD>
allowing your design to continue. This constraint disables all clock placer
rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:b9a90c54) REAL time: 50 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:b9a90c54) REAL time: 50 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:b9a90c54) REAL time: 50 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:5a4374ed) REAL time: 52 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b9b9c566) REAL time: 52 secs
Phase 9.8 Global Placement
...........
................
..............................
.....
Phase 9.8 Global Placement (Checksum:1b243f66) REAL time: 1 mins 3 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:1b243f66) REAL time: 1 mins 3 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:3389a4d6) REAL time: 1 mins 18 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:3389a4d6) REAL time: 1 mins 18 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:bed3755b) REAL time: 1 mins 19 secs
Total REAL time to Placer completion: 1 mins 28 secs
Total CPU time to Placer completion: 1 mins 24 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<3>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<4>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<5>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<6>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<7>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRModeDef0_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTrst_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSDo_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PllDacDout_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsTClkIn_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPllLock_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2ModeDef0_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2LoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRTxFault_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsBunchClkIn_i_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TempIdDQ_io_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsDrOver_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTdi_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTck_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc1PrsntM2C_in_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTms_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc2PrsntM2C_in_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 83
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 4
Number used as Single Port RAM: 0
Number used as Shift Register: 3
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 15
Number with same-slice register load: 6
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113
Number with an unused Flip Flop: 382 out of 1,113 34%
Number with an unused LUT: 196 out of 1,113 17%
Number of fully used LUT-FF pairs: 535 out of 1,113 48%
Number of unique control sets: 32
Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2
IOB Slave Pads: 2
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 268 0%
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 0 out of 586 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02
Peak Memory Usage: 406 MB
Total REAL time to MAP completion: 1 mins 31 secs
Total CPU time to MAP completion: 1 mins 28 secs
Mapping completed.
See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp 0 → 100644
View file @ 23b1b4b5
Release 12.3 Map M.70d (nt)
Xilinx Mapping Report File for Design 'SFpga'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr
off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Thu Dec 16 18:41:28 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 83
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 4
Number used as Single Port RAM: 0
Number used as Shift Register: 3
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 15
Number with same-slice register load: 6
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113
Number with an unused Flip Flop: 382 out of 1,113 34%
Number with an unused LUT: 196 out of 1,113 17%
Number of fully used LUT-FF pairs: 535 out of 1,113 48%
Number of unique control sets: 32
Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2
IOB Slave Pads: 2
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 268 0%
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 0 out of 586 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02
Peak Memory Usage: 406 MB
Total REAL time to MAP completion: 1 mins 31 secs
Total CPU time to MAP completion: 1 mins 28 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
PllFmc12SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllFmc12SFpga_ikn connected to top level port
PllFmc12SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllFmc22SFpga_ik connected to top level port
PllFmc22SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllFmc22SFpga_ikn connected to top level port
PllFmc22SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllSys2SFpga_ik connected to top level port
PllSys2SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllSys2SFpga_ikn connected to top level port
PllSys2SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal PllDds2SFpga_ik connected to top level port
PllDds2SFpga_ik has been removed.
WARNING:MapLib:701 - Signal PllDds2SFpga_ikn connected to top level port
PllDds2SFpga_ikn has been removed.
WARNING:MapLib:701 - Signal DdsSyncOut_ik connected to top level port
DdsSyncOut_ik has been removed.
WARNING:MapLib:701 - Signal DdsSyncOut_ikn connected to top level port
DdsSyncOut_ikn has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<15> connected to top level port
DdrDQ_iob16<15> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<14> connected to top level port
DdrDQ_iob16<14> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<13> connected to top level port
DdrDQ_iob16<13> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<12> connected to top level port
DdrDQ_iob16<12> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<11> connected to top level port
DdrDQ_iob16<11> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<10> connected to top level port
DdrDQ_iob16<10> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<9> connected to top level port
DdrDQ_iob16<9> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<8> connected to top level port
DdrDQ_iob16<8> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<7> connected to top level port
DdrDQ_iob16<7> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<6> connected to top level port
DdrDQ_iob16<6> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<5> connected to top level port
DdrDQ_iob16<5> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<4> connected to top level port
DdrDQ_iob16<4> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<3> connected to top level port
DdrDQ_iob16<3> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<2> connected to top level port
DdrDQ_iob16<2> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<1> connected to top level port
DdrDQ_iob16<1> has been removed.
WARNING:MapLib:701 - Signal DdrDQ_iob16<0> connected to top level port
DdrDQ_iob16<0> has been removed.
WARNING:MapLib:701 - Signal Si57xSDa_io connected to top level port Si57xSDa_io
has been removed.
WARNING:MapLib:701 - Signal AFpgaProgDone_io connected to top level port
AFpgaProgDone_io has been removed.
WARNING:MapLib:701 - Signal DdsIOUpdate_io connected to top level port
DdsIOUpdate_io has been removed.
WARNING:MapLib:701 - Signal WRModeDef2_io connected to top level port
WRModeDef2_io has been removed.
WARNING:MapLib:701 - Signal Sfp2ModeDef2_io connected to top level port
Sfp2ModeDef2_io has been removed.
WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
VAdjInhibit_ozn has been removed.
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <VmeSysClk_ik> is placed at site <PAD550>. The corresponding
BUFG component <VmeSysClk_ik_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y9>.
There is only a select set of IOBs that can use the fast path to the Clocker
buffer, and they are not being used. You may want to analyze why this problem
exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <VmeSysClk_ik.PAD>
allowing your design to continue. This constraint disables all clock placer
rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<3>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<4>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<5>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<6>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<7>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRModeDef0_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTrst_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSDo_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PllDacDout_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsTClkIn_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPllLock_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2ModeDef0_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2LoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRTxFault_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsBunchClkIn_i_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TempIdDQ_io_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsDrOver_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTdi_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTck_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc1PrsntM2C_in_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTms_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc2PrsntM2C_in_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network N450 has no load.
INFO:LIT:395 - The above info message is repeated 51 more times for the
following (max. 5 shown):
N452,
VmeAm_ib6<2>_IBUF,
VmeAm_ib6<1>_IBUF,
VmeDs_inb2<2>_IBUF,
VmeDs_inb2<1>_IBUF
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
67 block(s) removed
2 block(s) optimized away
37 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block "i_DdsSyncOut_ik" (IBUFGDS) removed.
The signal "DdsSyncOut_ik" is loadless and has been removed.
Loadless block "DdsSyncOut_ik" (PAD) removed.
The signal "DdsSyncOut_ikn" is loadless and has been removed.
Loadless block "DdsSyncOut_ikn" (PAD) removed.
Loadless block "i_PllDds2SFpga_ik" (IBUFGDS) removed.
The signal "PllDds2SFpga_ik" is loadless and has been removed.
Loadless block "PllDds2SFpga_ik" (PAD) removed.
The signal "PllDds2SFpga_ikn" is loadless and has been removed.
Loadless block "PllDds2SFpga_ikn" (PAD) removed.
Loadless block "i_PllFmc12SFpga_ik" (IBUFGDS) removed.
The signal "PllFmc12SFpga_ik" is loadless and has been removed.
Loadless block "PllFmc12SFpga_ik" (PAD) removed.
The signal "PllFmc12SFpga_ikn" is loadless and has been removed.
Loadless block "PllFmc12SFpga_ikn" (PAD) removed.
Loadless block "i_PllFmc22SFpga_ik" (IBUFGDS) removed.
The signal "PllFmc22SFpga_ik" is loadless and has been removed.
Loadless block "PllFmc22SFpga_ik" (PAD) removed.
The signal "PllFmc22SFpga_ikn" is loadless and has been removed.
Loadless block "PllFmc22SFpga_ikn" (PAD) removed.
Loadless block "i_PllSys2SFpga_ik" (IBUFGDS) removed.
The signal "PllSys2SFpga_ik" is loadless and has been removed.
Loadless block "PllSys2SFpga_ik" (PAD) removed.
The signal "PllSys2SFpga_ikn" is loadless and has been removed.
Loadless block "PllSys2SFpga_ikn" (PAD) removed.
The signal "i_DdrLDQS_io/O" is sourceless and has been removed.
The signal "i_DdrUDQS_io/O" is sourceless and has been removed.
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "DdrDQ_iob16<15>" is unused and has been removed.
Unused block "DdrDQ_iob16_15_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<14>" is unused and has been removed.
Unused block "DdrDQ_iob16_14_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<13>" is unused and has been removed.
Unused block "DdrDQ_iob16_13_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<12>" is unused and has been removed.
Unused block "DdrDQ_iob16_12_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<11>" is unused and has been removed.
Unused block "DdrDQ_iob16_11_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<10>" is unused and has been removed.
Unused block "DdrDQ_iob16_10_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<9>" is unused and has been removed.
Unused block "DdrDQ_iob16_9_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<8>" is unused and has been removed.
Unused block "DdrDQ_iob16_8_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<7>" is unused and has been removed.
Unused block "DdrDQ_iob16_7_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<6>" is unused and has been removed.
Unused block "DdrDQ_iob16_6_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<5>" is unused and has been removed.
Unused block "DdrDQ_iob16_5_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<4>" is unused and has been removed.
Unused block "DdrDQ_iob16_4_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<3>" is unused and has been removed.
Unused block "DdrDQ_iob16_3_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<2>" is unused and has been removed.
Unused block "DdrDQ_iob16_2_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<1>" is unused and has been removed.
Unused block "DdrDQ_iob16_1_OBUFT" (TRI) removed.
The signal "DdrDQ_iob16<0>" is unused and has been removed.
Unused block "DdrDQ_iob16_0_OBUFT" (TRI) removed.
The signal "Si57xSDa_io" is unused and has been removed.
Unused block "Si57xSDa_io_OBUFT" (TRI) removed.
The signal "AFpgaProgDone_io" is unused and has been removed.
Unused block "AFpgaProgDone_io_OBUFT" (TRI) removed.
The signal "AFpgaProgProgram_o" is unused and has been removed.
Unused block "AFpgaProgProgram_o_OBUFT" (TRI) removed.
The signal "VAdjInhibit_ozn" is unused and has been removed.
Unused block "VAdjInhibit_ozn_OBUFT" (TRI) removed.
The signal "DdsIOUpdate_io" is unused and has been removed.
Unused block "DdsIOUpdate_io_OBUFT" (TRI) removed.
The signal "WRModeDef2_io" is unused and has been removed.
Unused block "WRModeDef2_io_OBUFT" (TRI) removed.
The signal "Sfp2ModeDef2_io" is unused and has been removed.
Unused block "Sfp2ModeDef2_io_OBUFT" (TRI) removed.
The signal "Fmc1SDa_io" is unused and has been removed.
Unused block "Fmc1SDa_io_OBUFT" (TRI) removed.
The signal "Fmc2SDa_io" is unused and has been removed.
Unused block "Fmc2SDa_io_OBUFT" (TRI) removed.
Unused block "AFpgaProgDone_io" (PAD) removed.
Unused block "AFpgaProgProgram_o" (PAD) removed.
Unused block "DdrDQ_iob16<0>" (PAD) removed.
Unused block "DdrDQ_iob16<10>" (PAD) removed.
Unused block "DdrDQ_iob16<11>" (PAD) removed.
Unused block "DdrDQ_iob16<12>" (PAD) removed.
Unused block "DdrDQ_iob16<13>" (PAD) removed.
Unused block "DdrDQ_iob16<14>" (PAD) removed.
Unused block "DdrDQ_iob16<15>" (PAD) removed.
Unused block "DdrDQ_iob16<1>" (PAD) removed.
Unused block "DdrDQ_iob16<2>" (PAD) removed.
Unused block "DdrDQ_iob16<3>" (PAD) removed.
Unused block "DdrDQ_iob16<4>" (PAD) removed.
Unused block "DdrDQ_iob16<5>" (PAD) removed.
Unused block "DdrDQ_iob16<6>" (PAD) removed.
Unused block "DdrDQ_iob16<7>" (PAD) removed.
Unused block "DdrDQ_iob16<8>" (PAD) removed.
Unused block "DdrDQ_iob16<9>" (PAD) removed.
Unused block "DdsIOUpdate_io" (PAD) removed.
Unused block "Fmc1SDa_io" (PAD) removed.
Unused block "Fmc2SDa_io" (PAD) removed.
Unused block "Sfp2ModeDef2_io" (PAD) removed.
Unused block "Si57xSDa_io" (PAD) removed.
Unused block "VAdjInhibit_ozn" (PAD) removed.
Unused block "WRModeDef2_io" (PAD) removed.
Unused block "i_DdrLDQS_io/IBUFDS" (IBUFDS) removed.
Unused block "i_DdrUDQS_io/IBUFDS" (IBUFDS) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| AFpgaProgClk_io | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgCsi_io | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| AFpgaProgInit_io | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgM_iob2<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgM_iob2<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgRdWr_io | IOB | INPUT | LVCMOS25 | | | | | | |
| DdrA_ob14<0> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<1> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<2> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<3> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<4> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<5> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<6> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<7> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<8> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<9> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<10> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<11> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<12> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrA_ob14<13> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrBA_ob3<0> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrBA_ob3<1> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrBA_ob3<2> | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrCAS_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrCkE_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrCk_ok | IOB | OUTPUT | DIFF_SSTL15_II | | | | | | |
| DdrCk_okn | IOB | OUTPUT | DIFF_SSTL15_II | | | | | | |
| DdrLDM_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrLDQS_io | IOB | OUTPUT | DIFF_SSTL15_II | | | | | | |
| DdrLDQS_ion | IOB | OUTPUT | DIFF_SSTL15_II | | | | | | |
| DdrODT_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrRAS_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrReset_or | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrUDM_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdrUDQS_io | IOB | OUTPUT | DIFF_SSTL15_II | | | | | | |
| DdrUDQS_ion | IOB | OUTPUT | DIFF_SSTL15_II | | | | | | |
| DdrWe_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| DdsD_ob16<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<7> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<8> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<9> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<10> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<11> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<12> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<13> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<14> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsD_ob16<15> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsDrCtl_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsDrHold_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsDrOver_i | IOB | INPUT | LVCMOS33 | | | | | | |
| DdsF_ob2<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsF_ob2<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsIoReset_or | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsMasterRst_or | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsOsk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsPdClk_ik | IOB | INPUT | LVCMOS33 | | | | | | |
| DdsPllLock_i | IOB | INPUT | LVCMOS33 | | | | | | |
| DdsPowerDown_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsProfile_ob3<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsProfile_ob3<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsProfile_ob3<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsRamSwpOvr_i | IOB | INPUT | LVCMOS33 | | | | | | |
| DdsSClk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsSDio_io | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| DdsSDo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| DdsSyncClk_ik | IOB | INPUT | LVCMOS33 | | | | | | |
| DdsSyncIn_ok | IOBM | OUTPUT | LVDS_33 | | | | | | |
| DdsSyncIn_okn | IOBS | OUTPUT | LVDS_33 | | | | | | |
| DdsSyncSmpErr_i | IOB | INPUT | LVCMOS33 | | | | | | |
| DdsTxEnable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FlashAFpgaClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FlashAFpgaCs_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FlashAFpgaD_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FlashAFpgaQ_i | IOB | INPUT | LVCMOS33 | | | | | | |
| FlashSFpgaClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FlashSFpgaCs_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FlashSFpgaD_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FlashSFpgaQ_i | IOB | INPUT | LVCMOS33 | | | | | | |
| Fmc1PGC2M_in | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| Fmc1PrsntM2C_in | IOB | INPUT | LVCMOS25 | | | | | | |
| Fmc1SCl_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Fmc2PGC2M_in | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| Fmc2PrsntM2C_in | IOB | INPUT | LVCMOS25 | | | | | | |
| Fmc2SCl_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FpGpIo1OutputMode_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FpGpIo2OutputMode_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FpGpIo34OutputMode_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| FpLed_onb8<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| FpLed_onb8<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| FpLed_onb8<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| FpLed_onb8<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| FpLed_onb8<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| FpLed_onb8<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| FpLed_onb8<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| FpLed_onb8<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ManualAddress_ib5<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| ManualAddress_ib5<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| ManualAddress_ib5<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| ManualAddress_ib5<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| ManualAddress_ib5<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| PcbRev_ib8<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| PcbRev_ib8<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| PcbRev_ib8<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| PcbRev_ib8<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| PcbRev_ib8<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| PcbRev_ib8<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| PcbRev_ib8<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| PcbRev_ib8<7> | IOB | INPUT | LVCMOS25 | | | | | | |
| PllDacClrn_orn | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDacDin_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDacDout_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllDacLDac_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDacSClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDacSynch_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDdsClk_ok | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| PllDdsCs_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDdsLd_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllDdsPd_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDdsRefMon_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllDdsRefSel_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| PllDdsReset_orn | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDdsSClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDdsSDio_io | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllDdsSdo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllDdsStatus_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllDdsSynch_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc1Cs_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc1Ld_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllFmc1Pd_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc1Ref1_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc1RefMon_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllFmc1RefSel_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc1Reset_orn | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc1SClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc1SDio_io | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc1Sdo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllFmc1Status_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllFmc1Synch_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc2Cs_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc2Ld_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllFmc2Pd_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc2Ref1_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc2RefMon_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllFmc2RefSel_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc2Reset_orn | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc2SClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc2SDio_io | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllFmc2Sdo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllFmc2Status_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllFmc2Synch_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllSysCs_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllSysLd_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllSysPd_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllSysRef12_ok | IOBM | OUTPUT | LVDS_33 | | | | | | |
| PllSysRef12_okn | IOBS | OUTPUT | LVDS_33 | | | | | | |
| PllSysRefMon_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllSysRefSel_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllSysReset_orn | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllSysSClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllSysSDio_io | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PllSysSdo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllSysStatus_i | IOB | INPUT | LVCMOS33 | | | | | | |
| PllSysSynch_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| PushButton_ion | IOB | INPUT | LVCMOS33 | | | | | | |
| Sfp2LoS_i | IOB | INPUT | LVCMOS33 | | | | | | |
| Sfp2ModeDef0_i | IOB | INPUT | LVCMOS33 | | | | | | |
| Sfp2ModeDef1_i | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2RateSelect | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2TxDisable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2TxFault_i | IOB | INPUT | LVCMOS33 | | | | | | |
| Si57xOe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Si57xSCl_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Si57x_ik | IOB | INPUT | LVDS_33 | TRUE | | | | | |
| Si57x_ikn | IOB | INPUT | LVDS_33 | TRUE | | | | | |
| Switch_ib2<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| Switch_ib2<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| SysAppClk_ik | IOB | INPUT | LVCMOS25 | | | | | | |
| SysAppClk_ok | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| SysAppSlow_iob2<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| SysAppSlow_iob2<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| TempIdDQ_io | IOB | INPUT | LVCMOS33 | | | | | | |
| UseGa_i | IOB | INPUT | LVCMOS25 | | | | | | |
| VAdcCs_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VAdcDin_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VAdcDout_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VAdcSClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VAdjCs_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VAdjDin_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VAdjSClk_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VAdjSpi_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VcTcXo_ik | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeADirVfcToVme_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeAOeN_oen | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeA_iob31<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<6> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<7> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<8> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<9> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<10> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<11> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<12> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<13> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<14> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<15> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<16> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<17> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<18> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<19> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<20> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<21> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<22> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<23> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<24> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<25> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<26> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<27> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<28> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<29> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<30> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeA_iob31<31> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeAm_ib6<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeAm_ib6<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeAm_ib6<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeAm_ib6<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeAm_ib6<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeAm_ib6<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeAs_in | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeBerr_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeDDirVfcToVme_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeDOeN_oen | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeD_iob32<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| VmeDs_inb2<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeDs_inb2<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeDtAckOe_oe | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeDtAck_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeGaP_in | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeGa_ib5n<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeGa_ib5n<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeGa_ib5n<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeGa_ib5n<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeGa_ib5n<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeIackIn_in | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeIackOut_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeIack_in | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeIrq_ob7<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeIrq_ob7<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeIrq_ob7<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeIrq_ob7<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeIrq_ob7<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeIrq_ob7<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeIrq_ob7<7> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeLword_io | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeP0BunchSelectDir_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0BunchSelectOe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0BuslineDir_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0BuslineOe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0HwHighByteDir_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0HwHighByteOe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0HwLowByteDir_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0HwLowByteOe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0LvdsBunchClkIn_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeP0LvdsBunchClkOut_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeP0LvdsTClkIn_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeP0LvdsTClkOut_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeRetryOe_oe | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeRetry_on | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeSysClk_ik | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeSysReset_in | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeTck_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeTdi_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeTdoOe_oe | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeTdo_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VmeTms_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeTrst_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VmeWrite_in | IOB | INPUT | LVCMOS33 | | | | | | |
| WRLoS_i | IOB | INPUT | LVCMOS33 | | | | | | |
| WRModeDef0_i | IOB | INPUT | LVCMOS33 | | | | | | |
| WRModeDef1_i | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| WRRateSelect_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| WRTxDisable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| WRTxFault_i | IOB | INPUT | LVCMOS33 | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ncd 0 → 100644
View file @ 23b1b4b5
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trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ngm 0 → 100644
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trunk/firmware/XilinxISE/SystemFpga/SFpga_map.xrpt 0 → 100644
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trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Thu Dec 16 18:41:24 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
</row>
</table>
</section>
<task stringID="NGDBUILD_OPTION_SUMMARY">
<section stringID="NGDBUILD_OPTION_SUMMARY">
<item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
<item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx150t-fgg676-3"/>
<item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="SFpga.ucf"/>
</section>
</task>
<task stringID="NGDBUILD_REPORT">
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="14"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="189"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="99"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="313"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="77"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="163"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="163"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="121"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="112"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="181"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="189"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="99"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="313"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="155"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="163"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="163"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="121"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="112"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="181"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
</section>
</task>
</application>
</document>
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv 0 → 100644
View file @ 23b1b4b5
#Release 12.3 - par M.70d (nt)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Thu Dec 16 18:44:09 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
#INPUT FILE: SFpga_map.ncd
#OUTPUT FILE: SFpga_pad.csv
#PART TYPE: xc6slx150t
#SPEED GRADE: -3
#PACKAGE: fgg676
#
# Pinout by Pin Number:
#
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
A1,,,GND,,,,,,,,,,,,
A2,DdsF_ob2<1>,IOB,IO_L14N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
A3,DdsProfile_ob3<2>,IOB,IO_L14P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
A4,DdsProfile_ob3<0>,IOB,IO_L22N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
A5,DdsOsk_o,IOB,IO_L24N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
A6,,OPAD,MGTTXN0_101,UNUSED,,,,,,,,,,,
A7,,,MGTAVTTTX_101,,,,,,,,,,,,
A8,,OPAD,MGTTXN1_101,UNUSED,,,,,,,,,,,
A9,,,GND,,,,,,,,,,,,
A10,,IPAD,MGTREFCLK0N_101,UNUSED,,,,,,,,,,,
A11,,,GND,,,,,,,,,,,,
A12,Si57x_ikn,IOB,IO_L36N_GCLK14_0,,LVDS_33,0,,,,,,LOCATED,NO,DIFF_TERM,
A13,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
A14,DdsSyncIn_okn,IOBS,IO_L37N_GCLK12_0,,LVDS_33,0,,,,,,LOCATED,NO,,
A15,,,GND,,,,,,,,,,,,
A16,,IPAD,MGTREFCLK1N_123,UNUSED,,,,,,,,,,,
A17,,,GND,,,,,,,,,,,,
A18,,OPAD,MGTTXN0_123,UNUSED,,,,,,,,,,,
A19,,,MGTAVTTTX_123,,,,,,,,,,,,
A20,,OPAD,MGTTXN1_123,UNUSED,,,,,,,,,,,
A21,,,GND,,,,,,,,,,,,
A22,VmeD_iob32<0>,IOB,IO_L63N_SCP6_0,BIDIR,LVCMOS33,0,12,,,NONE,,LOCATED,NO,NONE,
A23,VmeD_iob32<2>,IOB,IO_L65N_SCP2_0,BIDIR,LVCMOS33,0,12,,,NONE,,LOCATED,NO,NONE,
A24,,,TCK,,,,,,,,,,,,
A25,VmeD_iob32<5>,IOB,IO_L2N_M5A14_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
A26,,,GND,,,,,,,,,,,,
AA1,PcbRev_ib8<0>,IOB,IO_L36N_M3DQ9_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AA2,PcbRev_ib8<1>,IOB,IO_L36P_M3DQ8_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AA3,AFpgaProgD_iob8<2>,IOB,IO_L2N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AA4,AFpgaProgM_iob2<1>,IOB,IO_L2P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AA5,,,VCCAUX,,,,,,,,2.5,,,,
AA6,PllFmc1SClk_ok,IOB,IO_L64N_D9_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AA7,PushButton_ion,IOB,IO_L64P_D8_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AA8,PllFmc1RefSel_o,IOB,IO_L52N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AA9,PllFmc1Ld_i,IOB,IO_L47P_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AA10,PllFmc1RefMon_i,IOB,IO_L48P_D7_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AA11,PllFmc1Ref1_ok,IOB,IO_L41N_VREF_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AA12,PllSysSClk_ok,IOB,IO_L33N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AA13,PllSysSynch_on,IOB,IO_L36N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AA14,,,VCCO_2,,,2,,,,,3.30,,,,
AA15,PllSysRef12_ok,IOBM,IO_L28P_2,OUTPUT,LVDS_33,2,,,,,,LOCATED,NO,NONE,
AA16,VmeD_iob32<28>,IOB,IO_L24N_VREF_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
AA17,VmeD_iob32<25>,IOB,IO_L16N_VREF_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
AA18,FlashAFpgaQ_i,IOB,IO_L20P_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AA19,VmeD_iob32<22>,IOB,IO_L18P_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
AA20,,,VCCO_2,,,2,,,,,3.30,,,,
AA21,PllDacSClk_ok,IOB,IO_L15P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AA22,PllDacLDac_on,IOB,IO_L2N_CMPMOSI_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AA23,,IOBM,IO_L67P_1,UNUSED,,1,,,,,,,,,
AA24,,IOBS,IO_L67N_1,UNUSED,,1,,,,,,,,,
AA25,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,,
AA26,,IOBS,IO_L47N_LDC_M1DQ1_1,UNUSED,,1,,,,,,,,,
AB1,PcbRev_ib8<2>,IOB,IO_L32N_M3DQ15_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AB2,,,GND,,,,,,,,,,,,
AB3,AFpgaProgClk_io,IOB,IO_L32P_M3DQ14_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AB4,AFpgaProgCsi_io,IOB,IO_L8P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AB5,AFpgaProgD_iob8<0>,IOB,IO_L1P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AB6,,,VCCO_2,,,2,,,,,3.30,,,,
AB7,PllFmc1Synch_on,IOB,IO_L53P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AB8,,,VCCAUX,,,,,,,,2.5,,,,
AB9,PllFmc1Status_i,IOB,IO_L47N_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AB10,,,MGTRREF_245,,,,,,,,,,,,
AB11,PllSysCs_on,IOB,IO_L48N_RDWR_B_VREF_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AB12,,,MGTAVTTRCAL_245,,,,,,,,,,,,
AB13,PllSysRefSel_o,IOB,IO_L36P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AB14,PllSysStatus_i,IOB,IO_L30P_GCLK1_D13_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AB15,PllSysRef12_okn,IOBS,IO_L28N_2,,LVDS_33,2,,,,,,LOCATED,NO,,
AB16,,,GND,,,,,,,,,,,,
AB17,FlashAFpgaCs_on,IOB,IO_L20N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AB18,,,VCCAUX,,,,,,,,2.5,,,,
AB19,VmeD_iob32<21>,IOB,IO_L18N_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
AB20,,,GND,,,,,,,,,,,,
AB21,PllDacDin_o,IOB,IO_L15N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AB22,PllDacSynch_on,IOB,IO_L5P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AB23,,,VCCO_1,,,1,,,,,1.50,,,,
AB24,,IOBM,IO_L49P_M1DQ10_1,UNUSED,,1,,,,,,,,,
AB25,,,GND,,,,,,,,,,,,
AB26,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,,
AC1,PcbRev_ib8<3>,IOB,IO_L34N_M3UDQSN_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AC2,PcbRev_ib8<4>,IOB,IO_L34P_M3UDQS_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AC3,PllDdsRefSel_o,IOB,IO_L8N_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE,
AC4,SysAppSlow_iob2<1>,IOB,IO_L1N_VREF_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
AC5,PllFmc1Reset_orn,IOB,IO_L61P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AC6,PllFmc1Sdo_i,IOB,IO_L53N_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AC7,,,VCCAUX,,,,,,,,2.5,,,,
AC8,,IPAD,MGTRXP0_245,UNUSED,,,,,,,,,,,
AC9,,,MGTAVTTRX_245,,,,,,,,,,,,
AC10,,IPAD,MGTRXP1_245,UNUSED,,,,,,,,,,,
AC11,,,GND,,,,,,,,,,,,
AC12,,IPAD,MGTREFCLK1P_245,UNUSED,,,,,,,,,,,
AC13,,,GND,,,,,,,,,,,,
AC14,PllSysLd_i,IOB,IO_L30N_GCLK0_USERCCLK_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AC15,,,GND,,,,,,,,,,,,
AC16,,IPAD,MGTREFCLK0P_267,UNUSED,,,,,,,,,,,
AC17,,,GND,,,,,,,,,,,,
AC18,,IPAD,MGTRXP0_267,UNUSED,,,,,,,,,,,
AC19,,,MGTAVTTRX_267,,,,,,,,,,,,
AC20,,IPAD,MGTRXP1_267,UNUSED,,,,,,,,,,,
AC21,,,VCCAUX,,,,,,,,2.5,,,,
AC22,FlashAFpgaClk_ok,IOB,IO_L5N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AC23,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
AC24,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
AC25,DdrUDQS_io,IOB,IO_L50P_M1UDQS_1,TRISTATE,DIFF_SSTL15_II,1,,,,,,LOCATED,NO,NONE,
AC26,DdrUDQS_ion,IOB,IO_L50N_M1UDQSN_1,TRISTATE,DIFF_SSTL15_II,1,,,,,,LOCATED,NO,NONE,
AD1,PcbRev_ib8<5>,IOB,IO_L33N_M3DQ13_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AD2,,,VCCO_3,,,3,,,,,2.50,,,,
AD3,AFpgaProgM_iob2<0>,IOB,IO_L33P_M3DQ12_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AD4,PllFmc1Pd_on,IOB,IO_L63P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AD5,PllFmc1SDio_io,IOB,IO_L61N_VREF_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AD6,PllFmc1Cs_on,IOB,IO_L49P_D3_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AD7,,,GND,,,,,,,,,,,,
AD8,,IPAD,MGTRXN0_245,UNUSED,,,,,,,,,,,
AD9,,,GND,,,,,,,,,,,,
AD10,,IPAD,MGTRXN1_245,UNUSED,,,,,,,,,,,
AD11,,,MGTAVCC_245,,,,,,,,,,,,
AD12,,IPAD,MGTREFCLK1N_245,UNUSED,,,,,,,,,,,
AD13,,,MGTAVCCPLL1_245,,,,,,,,,,,,
AD14,PllSysRefMon_i,IOB,IO_L32P_GCLK29_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AD15,,,MGTAVCCPLL0_267,,,,,,,,,,,,
AD16,,IPAD,MGTREFCLK0N_267,UNUSED,,,,,,,,,,,
AD17,,,MGTAVCC_267,,,,,,,,,,,,
AD18,,IPAD,MGTRXN0_267,UNUSED,,,,,,,,,,,
AD19,,,GND,,,,,,,,,,,,
AD20,,IPAD,MGTRXN1_267,UNUSED,,,,,,,,,,,
AD21,,,GND,,,,,,,,,,,,
AD22,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,,
AD23,FlashSFpgaQ_i,IOB,IO_L3P_D0_DIN_MISO_MISO1_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AD24,,IOBM,IO_L48P_HDC_M1DQ8_1,UNUSED,,1,,,,,,,,,
AD25,,,VCCO_1,,,1,,,,,1.50,,,,
AD26,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,,
AE1,PcbRev_ib8<6>,IOB,IO_L35N_M3DQ11_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AE2,PcbRev_ib8<7>,IOB,IO_L35P_M3DQ10_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AE3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
AE4,,,VCCO_2,,,2,,,,,3.30,,,,
AE5,PllSysReset_orn,IOB,IO_L51P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AE6,,,GND,,,,,,,,,,,,
AE7,,OPAD,MGTTXP0_245,UNUSED,,,,,,,,,,,
AE8,,,GND,,,,,,,,,,,,
AE9,,OPAD,MGTTXP1_245,UNUSED,,,,,,,,,,,
AE10,,,GND,,,,,,,,,,,,
AE11,,IPAD,MGTREFCLK0P_245,UNUSED,,,,,,,,,,,
AE12,,,MGTAVCCPLL0_245,,,,,,,,,,,,
AE13,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,,
AE14,,,VCCO_2,,,2,,,,,3.30,,,,
AE15,VmeP0LvdsBunchClkIn_i,IOB,IO_L29P_GCLK3_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AE16,,,MGTAVCCPLL1_267,,,,,,,,,,,,
AE17,,IPAD,MGTREFCLK1P_267,UNUSED,,,,,,,,,,,
AE18,,,GND,,,,,,,,,,,,
AE19,,OPAD,MGTTXP0_267,UNUSED,,,,,,,,,,,
AE20,,,GND,,,,,,,,,,,,
AE21,,OPAD,MGTTXP1_267,UNUSED,,,,,,,,,,,
AE22,,,GND,,,,,,,,,,,,
AE23,,,VCCO_2,,,2,,,,,3.30,,,,
AE24,FlashSFpgaClk_ok,IOB,IO_L1P_CCLK_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AE25,,IOBM,IO_L52P_M1DQ14_1,UNUSED,,1,,,,,,,,,
AE26,,IOBS,IO_L52N_M1DQ15_1,UNUSED,,1,,,,,,,,,
AF1,,,GND,,,,,,,,,,,,
AF2,,,PROGRAM_B_2,,,,,,,,,,,,
AF3,FlashSFpgaCs_on,IOB,IO_L65N_CSO_B_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AF4,PllSysPd_on,IOB,IO_L63N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AF5,PllSysSDio_io,IOB,IO_L51N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AF6,PllSysSdo_i,IOB,IO_L49N_D4_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AF7,,OPAD,MGTTXN0_245,UNUSED,,,,,,,,,,,
AF8,,,MGTAVTTTX_245,,,,,,,,,,,,
AF9,,OPAD,MGTTXN1_245,UNUSED,,,,,,,,,,,
AF10,,,GND,,,,,,,,,,,,
AF11,,IPAD,MGTREFCLK0N_245,UNUSED,,,,,,,,,,,
AF12,,,GND,,,,,,,,,,,,
AF13,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
AF14,VcTcXo_ik,IOB,IO_L32N_GCLK28_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
AF15,VmeP0LvdsBunchClkOut_o,IOB,IO_L29N_GCLK2_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AF16,,,GND,,,,,,,,,,,,
AF17,,IPAD,MGTREFCLK1N_267,UNUSED,,,,,,,,,,,
AF18,,,GND,,,,,,,,,,,,
AF19,,OPAD,MGTTXN0_267,UNUSED,,,,,,,,,,,
AF20,,,MGTAVTTTX_267,,,,,,,,,,,,
AF21,,OPAD,MGTTXN1_267,UNUSED,,,,,,,,,,,
AF22,FlashAFpgaD_o,IOB,IO_L13N_D10_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AF23,FlashSFpgaD_o,IOB,IO_L3N_MOSI_CSI_B_MISO0_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AF24,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,,
AF25,,,DONE_2,,,,,,,,,,,,
AF26,,,GND,,,,,,,,,,,,
B1,FpGpIo34OutputMode_o,IOB,IO_L75N_M4BA1_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
B2,TempIdDQ_io,IOB,IO_L75P_M4BA0_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
B3,DdsF_ob2<0>,IOB,IO_L4N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
B4,DdsProfile_ob3<1>,IOB,IO_L22P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
B5,,IOBM,IO_L24P_0,UNUSED,,0,,,,,,,,,
B6,,OPAD,MGTTXP0_101,UNUSED,,,,,,,,,,,
B7,,,GND,,,,,,,,,,,,
B8,,OPAD,MGTTXP1_101,UNUSED,,,,,,,,,,,
B9,,,GND,,,,,,,,,,,,
B10,,IPAD,MGTREFCLK0P_101,UNUSED,,,,,,,,,,,
B11,,,MGTAVCCPLL0_101,,,,,,,,,,,,
B12,Si57x_ik,IOB,IO_L36P_GCLK15_0,INPUT,LVDS_33,0,,,,NONE,,LOCATED,NO,DIFF_TERM,
B13,,,VCCO_0,,,0,,,,,3.30,,,,
B14,DdsSyncIn_ok,IOBM,IO_L37P_GCLK13_0,OUTPUT,LVDS_33,0,,,,,,LOCATED,NO,NONE,
B15,,,MGTAVCCPLL1_123,,,,,,,,,,,,
B16,,IPAD,MGTREFCLK1P_123,UNUSED,,,,,,,,,,,
B17,,,GND,,,,,,,,,,,,
B18,,OPAD,MGTTXP0_123,UNUSED,,,,,,,,,,,
B19,,,GND,,,,,,,,,,,,
B20,,OPAD,MGTTXP1_123,UNUSED,,,,,,,,,,,
B21,VmeTdo_o,IOB,IO_L59N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
B22,VmeD_iob32<1>,IOB,IO_L63P_SCP7_0,BIDIR,LVCMOS33,0,12,,,NONE,,LOCATED,NO,NONE,
B23,VmeD_iob32<3>,IOB,IO_L65P_SCP3_0,BIDIR,LVCMOS33,0,12,,,NONE,,LOCATED,NO,NONE,
B24,VmeD_iob32<4>,IOB,IO_L2P_M5A13_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
B25,VmeD_iob32<6>,IOB,IO_L11P_M5CLK_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
B26,VmeD_iob32<7>,IOB,IO_L11N_M5CLKN_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
C1,FpGpIo1OutputMode_o,IOB,IO_L79N_M4A9_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
C2,FpGpIo2OutputMode_o,IOB,IO_L79P_M4A8_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
C3,DdsD_ob16<14>,IOB,IO_L4P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
C4,,,VCCO_0,,,0,,,,,3.30,,,,
C5,DdsD_ob16<9>,IOB,IO_L16N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
C6,,,GND,,,,,,,,,,,,
C7,,IPAD,MGTRXN0_101,UNUSED,,,,,,,,,,,
C8,,,GND,,,,,,,,,,,,
C9,,IPAD,MGTRXN1_101,UNUSED,,,,,,,,,,,
C10,,,MGTAVCC_101,,,,,,,,,,,,
C11,,IPAD,MGTREFCLK1N_101,UNUSED,,,,,,,,,,,
C12,,,MGTAVCCPLL1_101,,,,,,,,,,,,
C13,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,,
C14,,,MGTAVCCPLL0_123,,,,,,,,,,,,
C15,,IPAD,MGTREFCLK0N_123,UNUSED,,,,,,,,,,,
C16,,,MGTAVCC_123,,,,,,,,,,,,
C17,,IPAD,MGTRXN0_123,UNUSED,,,,,,,,,,,
C18,,,GND,,,,,,,,,,,,
C19,,IPAD,MGTRXN1_123,UNUSED,,,,,,,,,,,
C20,,,GND,,,,,,,,,,,,
C21,VmeTdi_i,IOB,IO_L59P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
C22,,,VCCO_0,,,0,,,,,3.30,,,,
C23,,,TDI,,,,,,,,,,,,
C24,VmeA_iob31<20>,IOB,IO_L4N_M5A12_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
C25,VmeD_iob32<8>,IOB,IO_L10P_M5A0_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
C26,VmeD_iob32<9>,IOB,IO_L10N_M5A1_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
D1,PllDdsCs_on,IOB,IO_L68N_M4DQ5_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
D2,,,VCCO_4,,,4,,,,,3.30,,,,
D3,PllDdsSdo_i,IOB,IO_L68P_M4DQ4_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
D4,,,GND,,,,,,,,,,,,
D5,DdsD_ob16<10>,IOB,IO_L16P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
D6,,,VCCAUX,,,,,,,,2.5,,,,
D7,,IPAD,MGTRXP0_101,UNUSED,,,,,,,,,,,
D8,,,MGTAVTTRX_101,,,,,,,,,,,,
D9,,IPAD,MGTRXP1_101,UNUSED,,,,,,,,,,,
D10,,,GND,,,,,,,,,,,,
D11,,IPAD,MGTREFCLK1P_101,UNUSED,,,,,,,,,,,
D12,,,GND,,,,,,,,,,,,
D13,DdsPdClk_ik,IOB,IO_L34N_GCLK18_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
D14,,,GND,,,,,,,,,,,,
D15,,IPAD,MGTREFCLK0P_123,UNUSED,,,,,,,,,,,
D16,,,GND,,,,,,,,,,,,
D17,,IPAD,MGTRXP0_123,UNUSED,,,,,,,,,,,
D18,,,MGTAVTTRX_123,,,,,,,,,,,,
D19,,IPAD,MGTRXP1_123,UNUSED,,,,,,,,,,,
D20,,,VCCAUX,,,,,,,,2.5,,,,
D21,VmeTms_i,IOB,IO_L66P_SCP1_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
D22,VmeTck_i,IOB,IO_L66N_SCP0_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
D23,VmeA_iob31<21>,IOB,IO_L4P_M5CKE_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
D24,VmeA_iob31<22>,IOB,IO_L17P_M5DQ6_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
D25,,,VCCO_5,,,5,,,,,3.30,,,,
D26,VmeD_iob32<10>,IOB,IO_L17N_M5DQ7_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
E1,PllDdsSynch_on,IOB,IO_L67N_M4DQ7_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
E2,PllDdsSClk_ok,IOB,IO_L67P_M4DQ6_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
E3,PllDdsReset_orn,IOB,IO_L81N_M4A11_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
E4,PllDdsSDio_io,IOB,IO_L81P_M4RESET_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
E5,DdsD_ob16<11>,IOB,IO_L8N_VREF_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E6,DdsD_ob16<6>,IOB,IO_L8P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E7,,,GND,,,,,,,,,,,,
E8,DdsD_ob16<3>,IOB,IO_L15N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E9,,,MGTRREF_101,,,,,,,,,,,,
E10,DdsD_ob16<8>,IOB,IO_L23N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E11,,,MGTAVTTRCAL_101,,,,,,,,,,,,
E12,DdsSDio_io,IOB,IO_L31N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E13,DdsSyncClk_ik,IOB,IO_L34P_GCLK19_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
E14,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
E15,,,GND,,,,,,,,,,,,
E16,VmeP0HwLowByteOe_o,IOB,IO_L49N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E17,,,VCCAUX,,,,,,,,2.5,,,,
E18,Si57xOe_o,IOB,IO_L51N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E19,,,GND,,,,,,,,,,,,
E20,VmeWrite_in,IOB,IO_L57N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
E21,,,VCCO_0,,,0,,,,,3.30,,,,
E22,,,GND,,,,,,,,,,,,
E23,VmeA_iob31<19>,IOB,IO_L8P_M5A7_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
E24,VmeA_iob31<18>,IOB,IO_L8N_M5A2_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
E25,VmeD_iob32<11>,IOB,IO_L16P_M5DQ4_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
E26,VmeD_iob32<12>,IOB,IO_L16N_M5DQ5_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
F1,PllDdsStatus_i,IOB,IO_L66N_M4LDQSN_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
F2,,,GND,,,,,,,,,,,,
F3,PllDdsPd_on,IOB,IO_L66P_M4LDQS_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
F4,,,VCCO_4,,,4,,,,,3.30,,,,
F5,DdsD_ob16<12>,IOB,IO_L5N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F6,DdsD_ob16<7>,IOB,IO_L3N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F7,DdsD_ob16<4>,IOB,IO_L3P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F8,,,VCCO_0,,,0,,,,,3.30,,,,
F9,DdsD_ob16<1>,IOB,IO_L15P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F10,DdsD_ob16<0>,IOB,IO_L23P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F11,DdsSClk_o,IOB,IO_L30N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F12,DdsSDo_i,IOB,IO_L31P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
F13,,,VCCO_0,,,0,,,,,3.30,,,,
F14,Si57xSCl_ok,IOB,IO_L40P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F15,VmeP0BunchSelectOe_o,IOB,IO_L50N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F16,VmeP0HwLowByteDir_o,IOB,IO_L49P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F17,VmeRetryOe_oe,IOB,IO_L56N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F18,VmeIack_in,IOB,IO_L51P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
F19,VmeAOeN_oen,IOB,IO_L64N_SCP4_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F20,VmeADirVfcToVme_o,IOB,IO_L57P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
F21,,,TMS,,,,,,,,,,,,
F22,VmeA_iob31<17>,IOB,IO_L6P_M5A10_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
F23,VmeA_iob31<15>,IOB,IO_L14P_M5RASN_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
F24,VmeA_iob31<16>,IOB,IO_L18P_M5LDQS_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
F25,,,GND,,,,,,,,,,,,
F26,VmeD_iob32<13>,IOB,IO_L18N_M5LDQSN_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
G1,PllDdsRefMon_i,IOB,IO_L65N_M4DQ3_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
G2,PllDdsLd_i,IOB,IO_L65P_M4DQ2_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
G3,Sfp2TxDisable_o,IOB,IO_L77N_M4BA2_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
G4,Sfp2TxFault_i,IOB,IO_L77P_M4WE_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
G5,,,VCCAUX,,,,,,,,2.5,,,,
G6,DdsD_ob16<13>,IOB,IO_L5P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
G7,DdsD_ob16<5>,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
G8,DdsTxEnable_o,IOB,IO_L2N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
G9,DdsD_ob16<2>,IOB,IO_L13N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
G10,DdsPllLock_i,IOB,IO_L21N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
G11,DdsIoReset_or,IOB,IO_L32N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
G12,DdsDrHold_o,IOB,IO_L30P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
G13,DdsDrOver_i,IOB,IO_L33N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
G14,,,GND,,,,,,,,,,,,
G15,VmeP0BunchSelectDir_o,IOB,IO_L50P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
G16,VmeAm_ib6<1>,IOB,IO_L56P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
G17,VmeRetry_on,IOB,IO_L58N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
G18,,,VCCO_0,,,0,,,,,3.30,,,,
G19,VmeAm_ib6<0>,IOB,IO_L64P_SCP5_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
G20,VmeDs_inb2<1>,IOB,IO_L1N_A24_VREF_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
G21,,,TDO,,,,,,,,,,,,
G22,,,VCCO_5,,,5,,,,,3.30,,,,
G23,VmeA_iob31<14>,IOB,IO_L6N_M5A4_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
G24,VmeA_iob31<13>,IOB,IO_L14N_M5CASN_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
G25,VmeD_iob32<14>,IOB,IO_L20P_M5DQ0_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
G26,VmeD_iob32<15>,IOB,IO_L20N_M5DQ1_5,BIDIR,LVCMOS33,5,12,,,NONE,,LOCATED,NO,NONE,
H1,VAdjCs_on,IOB,IO_L64N_M4DQ1_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
H2,,,VCCO_4,,,4,,,,,3.30,,,,
H3,Sfp2ModeDef0_i,IOB,IO_L64P_M4DQ0_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
H4,,,GND,,,,,,,,,,,,
H5,Sfp2ModeDef1_i,IOB,IO_L83N_VREF_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
H6,,IOBM,IO_L83P_4,UNUSED,,4,,,,,,,,,
H7,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,,
H8,DdsSyncSmpErr_i,IOB,IO_L2P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
H9,DdsMasterRst_or,IOB,IO_L13P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
H10,DdsPowerDown_o,IOB,IO_L21P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
H11,,,VCCO_0,,,0,,,,,3.30,,,,
H12,DdsDrCtl_o,IOB,IO_L33P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
H13,VmeD_iob32<16>,IOB,IO_L39N_0,BIDIR,LVCMOS33,0,12,,,NONE,,LOCATED,NO,NONE,
H14,VmeP0HwHighByteDir_o,IOB,IO_L41N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
H15,VmeD_iob32<17>,IOB,IO_L43N_0,BIDIR,LVCMOS33,0,12,,,NONE,,LOCATED,NO,NONE,
H16,,,VCCO_0,,,0,,,,,3.30,,,,
H17,VmeAm_ib6<4>,IOB,IO_L58P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
H18,VmeAm_ib6<3>,IOB,IO_L62P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
H19,VmeAm_ib6<2>,IOB,IO_L62N_VREF_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
H20,VmeDs_inb2<2>,IOB,IO_L1P_A25_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
H21,VmeA_iob31<10>,IOB,IO_L5P_M5A8_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
H22,VmeA_iob31<12>,IOB,IO_L5N_M5A9_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
H23,,,GND,,,,,,,,,,,,
H24,VmeA_iob31<11>,IOB,IO_L19P_M5DQ2_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
H25,,,VCCO_5,,,5,,,,,3.30,,,,
H26,VmeTrst_i,IOB,IO_L19N_M5DQ3_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
J1,VAdjDin_o,IOB,IO_L63N_M4DQ9_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
J2,VAdjSClk_ok,IOB,IO_L63P_M4DQ8_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
J3,Sfp2LoS_i,IOB,IO_L69N_M4LDM_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
J4,Sfp2RateSelect,IOB,IO_L69P_M4UDM_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
J5,WRTxFault_i,IOB,IO_L73N_M4CLKN_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
J6,,,VCCO_4,,,4,,,,,3.30,,,,
J7,VmeIrq_ob7<2>,IOB,IO_L78N_M4A4_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
J8,,,GND,,,,,,,,,,,,
J9,VmeDtAckOe_oe,IOB,IO_L78P_M4A10_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
J10,,,VCCAUX,,,,,,,,2.5,,,,
J11,DdsRamSwpOvr_i,IOB,IO_L32P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
J12,VmeP0BuslineDir_o,IOB,IO_L38N_VREF_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
J13,VmeP0BuslineOe_o,IOB,IO_L39P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
J14,,,VCCO_0,,,0,,,,,3.30,,,,
J15,VmeD_iob32<18>,IOB,IO_L43P_0,BIDIR,LVCMOS33,0,12,,,NONE,,LOCATED,NO,NONE,
J16,VmeSysReset_in,IOB,IO_L48P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
J17,VmeAm_ib6<5>,IOB,IO_L48N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
J18,,,VCCAUX,,,,,,,,2.5,,,,
J19,,,GND,,,,,,,,,,,,
J20,VmeA_iob31<25>,IOB,IO_L7P_M5WE_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
J21,,,VCCO_5,,,5,,,,,3.30,,,,
J22,VmeA_iob31<7>,IOB,IO_L7N_M5BA2_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
J23,VmeA_iob31<9>,IOB,IO_L15P_M5UDM_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
J24,VmeA_iob31<8>,IOB,IO_L15N_M5LDM_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
J25,VmeGaP_in,IOB,IO_L22P_M5DQ10_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
J26,VmeGa_ib5n<0>,IOB,IO_L22N_M5DQ11_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
K1,VAdjSpi_o,IOB,IO_L62N_M4DQ11_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
K2,,,GND,,,,,,,,,,,,
K3,,IOBM,IO_L62P_M4DQ10_4,UNUSED,,4,,,,,,,,,
K4,,,VCCO_4,,,4,,,,,3.30,,,,
K5,WRTxDisable_o,IOB,IO_L73P_M4CLK_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
K6,WRModeDef1_i,IOB,IO_L82N_M4A14_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
K7,VmeIrq_ob7<3>,IOB,IO_L82P_M4A13_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
K8,VmeTdoOe_oe,IOB,IO_L80N_M4A12_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
K9,VmeDOeN_oen,IOB,IO_L80P_M4CKE_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
K10,VmeP0LvdsTClkOut_o,IOB,IO_L76N_M4A2_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
K11,,,VCCINT,,,,,,,,1.2,,,,
K12,DdsD_ob16<15>,IOB,IO_L38P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
K13,,,VCCAUX,,,,,,,,2.5,,,,
K14,VmeP0HwHighByteOe_o,IOB,IO_L41P_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
K15,,,VCCAUX,,,,,,,,2.5,,,,
K16,,,GND,,,,,,,,,,,,
K17,,,VCCINT,,,,,,,,1.2,,,,
K18,VmeA_iob31<24>,IOB,IO_L3P_M5RESET_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
K19,VmeA_iob31<26>,IOB,IO_L3N_M5A11_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
K20,VmeA_iob31<27>,IOB,IO_L9N_M5BA1_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
K21,VmeA_iob31<6>,IOB,IO_L12P_M5A3_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
K22,VmeA_iob31<4>,IOB,IO_L12N_M5ODT_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
K23,,,VCCO_5,,,5,,,,,3.30,,,,
K24,VmeA_iob31<5>,IOB,IO_L21P_M5DQ8_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
K25,,,GND,,,,,,,,,,,,
K26,VmeGa_ib5n<1>,IOB,IO_L21N_M5DQ9_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
L1,,IOBS,IO_L61N_M4UDQSN_4,UNUSED,,4,,,,,,,,,
L2,,IOBM,IO_L61P_M4UDQS_4,UNUSED,,4,,,,,,,,,
L3,WRModeDef0_i,IOB,IO_L71N_M4A6_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
L4,WRRateSelect_o,IOB,IO_L71P_M4A5_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
L5,,,VCCAUX,,,,,,,,2.5,,,,
L6,WRLoS_i,IOB,IO_L74N_M4A1_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
L7,VmeIrq_ob7<1>,IOB,IO_L74P_M4A0_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
L8,VmeSysClk_ik,IOB,IO_L70N_M4CASN_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
L9,VmeDDirVfcToVme_o,IOB,IO_L70P_M4RASN_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
L10,VmeP0LvdsTClkIn_i,IOB,IO_L76P_M4A7_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
L11,,,GND,,,,,,,,,,,,
L12,,,VCCINT,,,,,,,,1.2,,,,
L13,,,GND,,,,,,,,,,,,
L14,,,VCCINT,,,,,,,,1.2,,,,
L15,,,GND,,,,,,,,,,,,
L16,,,VCCINT,,,,,,,,1.2,,,,
L17,,,GND,,,,,,,,,,,,
L18,,,VCCAUX,,,,,,,,2.5,,,,
L19,VmeA_iob31<28>,IOB,IO_L9P_M5BA0_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
L20,VmeA_iob31<29>,IOB,IO_L27P_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
L21,VmeA_iob31<3>,IOB,IO_L27N_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
L22,,,VCCAUX,,,,,,,,2.5,,,,
L23,DdrA_ob14<13>,IOB,IO_L29P_A23_M1A13_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
L24,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,,
L25,VmeGa_ib5n<2>,IOB,IO_L24P_M5DQ12_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
L26,VmeGa_ib5n<3>,IOB,IO_L24N_M5DQ13_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
M1,Fmc2SCl_ok,IOB,IO_L60N_M4DQ13_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
M2,,,VCCO_4,,,4,,,,,3.30,,,,
M3,VmeIrq_ob7<4>,IOB,IO_L60P_M4DQ12_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
M4,VmeIrq_ob7<5>,IOB,IO_L58P_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
M5,,,GND,,,,,,,,,,,,
M6,VmeIrq_ob7<7>,IOB,IO_L72N_M4ODT_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
M7,,,VCCO_4,,,4,,,,,3.30,,,,
M8,VmeAs_in,IOB,IO_L72P_M4A3_4,INPUT,LVCMOS33,4,,,,NONE,,LOCATED,NO,NONE,
M9,,IOBS,IO_L57N_VREF_3,UNUSED,,3,,,,,,,,,
M10,,IOBM,IO_L57P_3,UNUSED,,3,,,,,,,,,
M11,,,VCCINT,,,,,,,,1.2,,,,
M12,,,VCCINT,,,,,,,,1.2,,,,
M13,,,VCCINT,,,,,,,,1.2,,,,
M14,,,VCCINT,,,,,,,,1.2,,,,
M15,,,VCCINT,,,,,,,,1.2,,,,
M16,,,VCCINT,,,,,,,,1.2,,,,
M17,,,VCCAUX,,,,,,,,2.5,,,,
M18,VmeA_iob31<30>,IOB,IO_L13P_M5A5_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
M19,VmeA_iob31<31>,IOB,IO_L13N_M5A6_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
M20,,,VCCO_5,,,5,,,,,3.30,,,,
M21,VmeA_iob31<2>,IOB,IO_L26P_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
M22,,,GND,,,,,,,,,,,,
M23,VmeLword_io,IOB,IO_L26N_VREF_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
M24,VmeA_iob31<1>,IOB,IO_L23P_M5UDQS_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
M25,,,VCCO_5,,,5,,,,,3.30,,,,
M26,VmeGa_ib5n<4>,IOB,IO_L23N_M5UDQSN_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
N1,Fmc1SCl_ok,IOB,IO_L59N_M4DQ15_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
N2,,IOBM,IO_L59P_M4DQ14_4,UNUSED,,4,,,,,,,,,
N3,VmeIrq_ob7<6>,IOB,IO_L58N_VREF_4,OUTPUT,LVCMOS33,4,12,,,,,LOCATED,NO,NONE,
N4,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,,
N5,,IOBM,IO_L54P_M3RESET_3,UNUSED,,3,,,,,,,,,
N6,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,,
N7,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,,
N8,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,,
N9,,IOBS,IO_L55N_M3A14_3,UNUSED,,3,,,,,,,,,
N10,,,VCCAUX,,,,,,,,2.5,,,,
N11,,,GND,,,,,,,,,,,,
N12,,,VCCINT,,,,,,,,1.2,,,,
N13,,,VCCINT,,,,,,,,1.2,,,,
N14,,,GND,,,,,,,,,,,,
N15,,,VCCINT,,,,,,,,1.2,,,,
N16,,,VCCINT,,,,,,,,1.2,,,,
N17,,IOBM,IO_L28P_1,UNUSED,,1,,,,,,,,,
N18,,IOBS,IO_L28N_VREF_1,UNUSED,,1,,,,,,,,,
N19,DdrReset_or,IOB,IO_L30P_A21_M1RESET_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
N20,DdrA_ob14<11>,IOB,IO_L30N_A20_M1A11_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
N21,DdrCkE_o,IOB,IO_L31P_A19_M1CKE_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
N22,DdrA_ob14<12>,IOB,IO_L31N_A18_M1A12_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
N23,DdrA_ob14<10>,IOB,IO_L33P_A15_M1A10_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
N24,DdrA_ob14<4>,IOB,IO_L33N_A14_M1A4_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
N25,VmeDtAck_on,IOB,IO_L25P_M5DQ14_5,OUTPUT,LVCMOS33,5,12,,,,,LOCATED,NO,NONE,
N26,VmeA_iob31<23>,IOB,IO_L25N_M5DQ15_5,INPUT,LVCMOS33,5,,,,NONE,,LOCATED,NO,NONE,
P1,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,,
P2,,,GND,,,,,,,,,,,,
P3,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,,
P4,,,VCCO_3,,,3,,,,,2.50,,,,
P5,FpLed_onb8<0>,IOB,IO_L50P_M3WE_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
P6,FpLed_onb8<3>,IOB,IO_L49N_M3A2_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
P7,,,GND,,,,,,,,,,,,
P8,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,,
P9,,,VCCO_3,,,3,,,,,2.50,,,,
P10,ManualAddress_ib5<4>,IOB,IO_L55P_M3A13_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
P11,,,VCCINT,,,,,,,,1.2,,,,
P12,,,VCCINT,,,,,,,,1.2,,,,
P13,,,GND,,,,,,,,,,,,
P14,,,VCCINT,,,,,,,,1.2,,,,
P15,,,VCCINT,,,,,,,,1.2,,,,
P16,,,GND,,,,,,,,,,,,
P17,DdrA_ob14<8>,IOB,IO_L32P_A17_M1A8_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
P18,,,VCCO_1,,,1,,,,,1.50,,,,
P19,DdrA_ob14<9>,IOB,IO_L32N_A16_M1A9_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
P20,,,GND,,,,,,,,,,,,
P21,DdrA_ob14<7>,IOB,IO_L35P_A11_M1A7_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
P22,DdrA_ob14<2>,IOB,IO_L35N_A10_M1A2_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
P23,,,VCCO_1,,,1,,,,,1.50,,,,
P24,DdrA_ob14<0>,IOB,IO_L37P_A7_M1A0_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
P25,,,GND,,,,,,,,,,,,
P26,DdrA_ob14<1>,IOB,IO_L37N_A6_M1A1_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
R1,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,,
R2,,IOBM,IO_L44P_GCLK21_M3A5_3,UNUSED,,3,,,,,,,,,
R3,FpLed_onb8<2>,IOB,IO_L52N_M3A9_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R4,FpLed_onb8<1>,IOB,IO_L52P_M3A8_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R5,FpLed_onb8<4>,IOB,IO_L50N_M3BA2_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R6,SysAppClk_ik,IOB,IO_L43N_GCLK22_IRDY2_M3CASN_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
R7,SysAppClk_ok,IOB,IO_L43P_GCLK23_M3RASN_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R8,ManualAddress_ib5<0>,IOB,IO_L45P_M3A3_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
R9,ManualAddress_ib5<2>,IOB,IO_L53P_M3CKE_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
R10,UseGa_i,IOB,IO_L47P_M3A0_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
R11,,,VCCINT,,,,,,,,1.2,,,,
R12,,,VCCINT,,,,,,,,1.2,,,,
R13,,,VCCINT,,,,,,,,1.2,,,,
R14,,,VCCINT,,,,,,,,1.2,,,,
R15,,,VCCINT,,,,,,,,1.2,,,,
R16,,,VCCINT,,,,,,,,1.2,,,,
R17,,,VCCINT,,,,,,,,1.2,,,,
R18,DdrWe_o,IOB,IO_L34P_A13_M1WE_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
R19,DdrBA_ob3<2>,IOB,IO_L34N_A12_M1BA2_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
R20,DdrBA_ob3<0>,IOB,IO_L36P_A9_M1BA0_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
R21,DdrBA_ob3<1>,IOB,IO_L36N_A8_M1BA1_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
R22,,,VCCAUX,,,,,,,,2.5,,,,
R23,DdrCk_ok,IOB,IO_L38P_A5_M1CLK_1,OUTPUT,DIFF_SSTL15_II,1,,,,,,LOCATED,NO,NONE,
R24,DdrCk_okn,IOB,IO_L38N_A4_M1CLKN_1,OUTPUT,DIFF_SSTL15_II,1,,,,,,LOCATED,NO,NONE,
R25,DdrRAS_o,IOB,IO_L41P_GCLK9_IRDY1_M1RASN_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
R26,DdrCAS_o,IOB,IO_L41N_GCLK8_M1CASN_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
T1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,,
T2,,,VCCO_3,,,3,,,,,2.50,,,,
T3,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,,
T4,FpLed_onb8<7>,IOB,IO_L46N_M3CLKN_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
T5,,,GND,,,,,,,,,,,,
T6,SysAppSlow_iob2<2>,IOB,IO_L31N_VREF_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
T7,,,VCCO_3,,,3,,,,,2.50,,,,
T8,ManualAddress_ib5<1>,IOB,IO_L45N_M3ODT_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
T9,ManualAddress_ib5<3>,IOB,IO_L47N_M3A1_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
T10,,,GND,,,,,,,,,,,,
T11,,,VCCINT,,,,,,,,1.2,,,,
T12,,,GND,,,,,,,,,,,,
T13,,,VCCINT,,,,,,,,1.2,,,,
T14,,,GND,,,,,,,,,,,,
T15,,,VCCINT,,,,,,,,1.2,,,,
T16,,,GND,,,,,,,,,,,,
T17,,,VCCINT,,,,,,,,1.2,,,,
T18,,,GND,,,,,,,,,,,,
T19,,IOBM,IO_L66P_1,UNUSED,,1,,,,,,,,,
T20,,IOBS,IO_L66N_1,UNUSED,,1,,,,,,,,,
T21,,,GND,,,,,,,,,,,,
T22,DdrA_ob14<3>,IOB,IO_L39P_M1A3_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
T23,DdrODT_o,IOB,IO_L39N_M1ODT_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
T24,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,,
T25,,,VCCO_1,,,1,,,,,1.50,,,,
T26,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
U1,Fmc2PrsntM2C_in,IOB,IO_L40N_M3DQ7_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U2,Fmc2PGC2M_in,IOB,IO_L40P_M3DQ6_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U3,FpLed_onb8<5>,IOB,IO_L10N_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U4,FpLed_onb8<6>,IOB,IO_L10P_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U5,AFpgaProgD_iob8<4>,IOB,IO_L46P_M3CLK_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U6,,,VCCAUX,,,,,,,,2.5,,,,
U7,,IOBM,IO_L31P_3,UNUSED,,3,,,,,,,,,
U8,AFpgaProgInit_io,IOB,IO_L18N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U9,,IOBM,IO_L18P_3,UNUSED,,3,,,,,,,,,
U10,,,VCCINT,,,,,,,,1.2,,,,
U11,,,GND,,,,,,,,,,,,
U12,,,VCCAUX,,,,,,,,2.5,,,,
U13,PllFmc2Cs_on,IOB,IO_L27P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
U14,,,VCCAUX,,,,,,,,2.5,,,,
U15,PllFmc2Reset_orn,IOB,IO_L17P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
U16,,,VCCINT,,,,,,,,1.2,,,,
U17,,,GND,,,,,,,,,,,,
U18,,,VCCAUX,,,,,,,,2.5,,,,
U19,,IOBM,IO_L68P_1,UNUSED,,1,,,,,,,,,
U20,,IOBS,IO_L68N_1,UNUSED,,1,,,,,,,,,
U21,,IOBM,IO_L53P_1,UNUSED,,1,,,,,,,,,
U22,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,,
U23,DdrA_ob14<5>,IOB,IO_L40P_GCLK11_M1A5_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
U24,DdrA_ob14<6>,IOB,IO_L40N_GCLK10_M1A6_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
U25,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,,
U26,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,,
V1,Fmc1PrsntM2C_in,IOB,IO_L39N_M3LDQSN_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
V2,,,GND,,,,,,,,,,,,
V3,AFpgaProgD_iob8<3>,IOB,IO_L39P_M3LDQS_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
V4,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,,
V5,AFpgaProgD_iob8<6>,IOB,IO_L17P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
V6,Switch_ib2<0>,IOB,IO_L9N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
V7,Switch_ib2<1>,IOB,IO_L9P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
V8,,,GND,,,,,,,,,,,,
V9,,,VCCAUX,,,,,,,,2.5,,,,
V10,VmeIackOut_on,IOB,IO_L46N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
V11,PllFmc2SClk_ok,IOB,IO_L46P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
V12,PllFmc2Synch_on,IOB,IO_L35P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
V13,PllFmc2RefSel_o,IOB,IO_L27N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
V14,PllFmc2Sdo_i,IOB,IO_L26P_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
V15,PllFmc2SDio_io,IOB,IO_L26N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
V16,PllFmc2Pd_on,IOB,IO_L17N_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
V17,,,VCCAUX,,,,,,,,2.5,,,,
V18,VmeBerr_o,IOB,IO_L12P_D1_MISO2_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
V19,,,RFUSE,,,,,,,,,,,,
V20,,IOBM,IO_L69P_1,UNUSED,,1,,,,,,,,,
V21,,IOBS,IO_L69N_VREF_1,UNUSED,,1,,,,,,,,,
V22,,,VBATT,,,,,,,,,,,,
V23,DdrUDM_o,IOB,IO_L42P_GCLK7_M1UDM_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
V24,DdrLDQS_io,IOB,IO_L45P_A1_M1LDQS_1,TRISTATE,DIFF_SSTL15_II,1,,,,,,LOCATED,NO,NONE,
V25,,,GND,,,,,,,,,,,,
V26,DdrLDQS_ion,IOB,IO_L45N_A0_M1LDQSN_1,TRISTATE,DIFF_SSTL15_II,1,,,,,,LOCATED,NO,NONE,
W1,Fmc1PGC2M_in,IOB,IO_L38N_M3DQ3_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
W2,AFpgaProgD_iob8<5>,IOB,IO_L38P_M3DQ2_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
W3,,IOBS,IO_L42N_GCLK24_M3LDM_3,UNUSED,,3,,,,,,,,,
W4,,,VCCO_3,,,3,,,,,2.50,,,,
W5,AFpgaProgD_iob8<7>,IOB,IO_L17N_VREF_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
W6,,,VCCO_3,,,3,,,,,2.50,,,,
W7,VAdcCs_on,IOB,IO_L62N_D6_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
W8,VAdcSClk_ok,IOB,IO_L62P_D5_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
W9,VAdcDout_i,IOB,IO_L50N_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
W10,VmeIackIn_in,IOB,IO_L50P_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
W11,,,VCCO_2,,,2,,,,,3.30,,,,
W12,PllFmc2Status_i,IOB,IO_L35N_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
W13,,,VCCAUX,,,,,,,,2.5,,,,
W14,VmeD_iob32<31>,IOB,IO_L34P_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
W15,,,VCCO_2,,,2,,,,,3.30,,,,
W16,VmeD_iob32<27>,IOB,IO_L19P_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
W17,VmeD_iob32<26>,IOB,IO_L14P_D11_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
W18,VmeD_iob32<23>,IOB,IO_L14N_D12_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
W19,VmeD_iob32<20>,IOB,IO_L12N_D2_MISO3_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
W20,VmeD_iob32<19>,IOB,IO_L4P_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
W21,,,VCCO_1,,,1,,,,,1.50,,,,
W22,,,VFS,,,,,,,,,,,,
W23,,,VCCO_1,,,1,,,,,1.50,,,,
W24,DdrLDM_o,IOB,IO_L42N_GCLK6_TRDY1_M1LDM_1,OUTPUT,SSTL15_II,1,,,,,,LOCATED,NO,NONE,
W25,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,,
W26,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,,
Y1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,,
Y2,,,VCCO_3,,,3,,,,,2.50,,,,
Y3,AFpgaProgD_iob8<1>,IOB,IO_L37P_M3DQ0_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
Y4,,,GND,,,,,,,,,,,,
Y5,AFpgaProgRdWr_io,IOB,IO_L7N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
Y6,PllDdsClk_ok,IOB,IO_L7P_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE,
Y7,,,GND,,,,,,,,,,,,
Y8,,,VCCO_2,,,2,,,,,3.30,,,,
Y9,VAdcDin_o,IOB,IO_L52P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
Y10,,,GND,,,,,,,,,,,,
Y11,PllFmc2RefMon_i,IOB,IO_L41P_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
Y12,PllFmc2Ref1_ok,IOB,IO_L33P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
Y13,PllFmc2Ld_i,IOB,IO_L34N_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
Y14,,,GND,,,,,,,,,,,,
Y15,VmeD_iob32<30>,IOB,IO_L24P_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
Y16,VmeD_iob32<29>,IOB,IO_L19N_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
Y17,VmeD_iob32<24>,IOB,IO_L16P_2,BIDIR,LVCMOS33,2,12,,,NONE,,LOCATED,NO,NONE,
Y18,,,VCCO_2,,,2,,,,,3.30,,,,
Y19,,,CMPCS_B_2,,,,,,,,,,,,
Y20,PllDacDout_i,IOB,IO_L4N_VREF_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
Y21,PllDacClrn_orn,IOB,IO_L2P_CMPCLK_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
Y22,,,SUSPEND,,,,,,,,,,,,
Y23,,,GND,,,,,,,,,,,,
Y24,,IOBM,IO_L51P_M1DQ12_1,UNUSED,,1,,,,,,,,,
Y25,,,VCCO_1,,,1,,,,,1.50,,,,
Y26,,IOBS,IO_L51N_M1DQ13_1,UNUSED,,1,,,,,,,,,
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
#
#* Default value.
#** This default Pullup/Pulldown value can be overridden in Bitgen.
#****** Special VCCO requirements may apply. Please consult the device
# family datasheet for specific guideline on VCCO requirements.
#
#
#
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt 0 → 100644
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This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_par.xrpt 0 → 100644
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trunk/firmware/XilinxISE/SystemFpga/SFpga_preroute.twr 0 → 100644
View file @ 23b1b4b5
--------------------------------------------------------------------------------
Release 12.3 Trace (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml SFpga_preroute.twx SFpga_map.ncd -o SFpga_preroute.twr
SFpga.pcf -ucf SFpga.ucf
Design file: SFpga_map.ncd
Physical constraint file: SFpga.pcf
Device,package,speed: xc6slx150t,fgg676,C,-3 (PRODUCTION 1.12c 2010-09-15)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock Si57x_ik
--------------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
--------------------+------------+------------+------------+------------+------------------+--------+
FlashAFpgaQ_i | 6.563(R)| SLOW | -5.755(R)| FAST |Si57x_BUFG | 0.000|
FlashSFpgaQ_i | 7.666(R)| SLOW | -6.848(R)| FAST |Si57x_BUFG | 0.000|
ManualAddress_ib5<0>| 8.463(R)| SLOW | -6.491(R)| SLOW |Si57x_BUFG | 0.000|
ManualAddress_ib5<1>| 7.243(R)| SLOW | -5.284(R)| SLOW |Si57x_BUFG | 0.000|
ManualAddress_ib5<2>| 8.628(R)| SLOW | -6.656(R)| SLOW |Si57x_BUFG | 0.000|
ManualAddress_ib5<3>| 9.304(R)| SLOW | -7.321(R)| FAST |Si57x_BUFG | 0.000|
ManualAddress_ib5<4>| 8.702(R)| SLOW | -6.739(R)| SLOW |Si57x_BUFG | 0.000|
PllDdsLd_i | 9.369(R)| SLOW | -8.850(R)| FAST |Si57x_BUFG | 0.000|
PllDdsRefMon_i | 8.621(R)| SLOW | -7.995(R)| SLOW |Si57x_BUFG | 0.000|
PllDdsSdo_i | 11.484(R)| SLOW | -10.676(R)| FAST |Si57x_BUFG | 0.000|
PllDdsStatus_i | 9.665(R)| SLOW | -9.131(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Ld_i | 8.142(R)| SLOW | -7.613(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1RefMon_i | 8.857(R)| SLOW | -8.236(R)| SLOW |Si57x_BUFG | 0.000|
PllFmc1Sdo_i | 8.949(R)| SLOW | -8.141(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Status_i | 9.158(R)| SLOW | -8.639(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Ld_i | 6.907(R)| SLOW | -6.286(R)| SLOW |Si57x_BUFG | 0.000|
PllFmc2RefMon_i | 8.905(R)| SLOW | -8.386(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Sdo_i | 6.184(R)| SLOW | -5.376(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Status_i | 7.665(R)| SLOW | -7.039(R)| SLOW |Si57x_BUFG | 0.000|
PllSysLd_i | 7.168(R)| SLOW | -6.633(R)| FAST |Si57x_BUFG | 0.000|
PllSysRefMon_i | 7.388(R)| SLOW | -6.832(R)| FAST |Si57x_BUFG | 0.000|
PllSysSdo_i | 8.442(R)| SLOW | -7.634(R)| FAST |Si57x_BUFG | 0.000|
PllSysStatus_i | 6.792(R)| SLOW | -6.289(R)| FAST |Si57x_BUFG | 0.000|
PushButton_ion | 1.974(R)| FAST | -1.516(R)| SLOW |Si57x_BUFG | 0.000|
UseGa_i | 9.072(R)| SLOW | -6.304(R)| SLOW |Si57x_BUFG | 0.000|
VAdcDout_i | 8.523(R)| SLOW | -7.715(R)| FAST |Si57x_BUFG | 0.000|
VmeA_iob31<1> | 8.455(R)| SLOW | -7.157(R)| FAST |Si57x_BUFG | 0.000|
VmeA_iob31<2> | 7.575(R)| SLOW | -2.719(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<3> | 7.459(R)| SLOW | -2.522(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<4> | 5.217(R)| SLOW | -4.619(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<5> | 4.363(R)| SLOW | -3.178(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<6> | 3.992(R)| SLOW | -3.394(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<7> | 4.968(R)| SLOW | -4.370(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<8> | 3.512(R)| SLOW | -2.914(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<9> | 3.527(R)| SLOW | -2.929(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<10> | 4.973(R)| SLOW | -4.375(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<11> | 3.302(R)| SLOW | -2.841(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<12> | 4.947(R)| SLOW | -4.349(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<13> | 3.747(R)| SLOW | -3.149(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<14> | 5.248(R)| SLOW | -4.650(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<15> | 3.767(R)| SLOW | -3.169(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<16> | 3.272(R)| SLOW | -2.674(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<17> | 4.976(R)| SLOW | -4.515(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<18> | 4.772(R)| SLOW | -4.311(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<19> | 4.727(R)| SLOW | -4.129(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<20> | 5.207(R)| SLOW | -4.609(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<21> | 5.213(R)| SLOW | -4.615(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<22> | 3.527(R)| SLOW | -2.929(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<23> | 2.937(R)| SLOW | -2.083(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<24> | 5.411(R)| FAST | -4.918(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<25> | 5.170(R)| FAST | -4.677(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<26> | 5.584(R)| FAST | -5.091(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<27> | 3.986(R)| FAST | -3.493(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<28> | 3.620(R)| FAST | -3.151(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<29> | 1.221(R)| FAST | -0.752(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<30> | 3.420(R)| FAST | -2.787(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<31> | 3.229(R)| FAST | -2.760(R)| SLOW |Si57x_BUFG | 0.000|
VmeAm_ib6<0> | 10.693(R)| SLOW | -7.862(R)| SLOW |Si57x_BUFG | 0.000|
VmeAm_ib6<3> | 10.453(R)| SLOW | -7.635(R)| SLOW |Si57x_BUFG | 0.000|
VmeAm_ib6<4> | 10.238(R)| SLOW | -7.445(R)| SLOW |Si57x_BUFG | 0.000|
VmeAm_ib6<5> | 9.056(R)| SLOW | -7.019(R)| SLOW |Si57x_BUFG | 0.000|
VmeAs_in | 5.553(R)| FAST | -5.060(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<0> | 8.259(R)| SLOW | -7.772(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<1> | 8.763(R)| SLOW | -8.275(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<2> | 8.517(R)| SLOW | -8.034(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<3> | 8.547(R)| SLOW | -8.069(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<4> | 8.228(R)| SLOW | -7.752(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<5> | 8.489(R)| SLOW | -8.009(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<6> | 7.052(R)| SLOW | -6.578(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<7> | 7.155(R)| SLOW | -6.677(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<8> | 6.287(R)| SLOW | -5.804(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<9> | 6.751(R)| SLOW | -6.133(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<10> | 6.252(R)| SLOW | -5.776(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<11> | 6.078(R)| SLOW | -5.602(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<12> | 6.108(R)| SLOW | -5.490(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<13> | 5.864(R)| SLOW | -5.390(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<14> | 5.632(R)| SLOW | -5.154(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<15> | 5.256(R)| SLOW | -4.643(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<16> | 7.419(R)| SLOW | -6.939(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<17> | 6.302(R)| SLOW | -5.826(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<18> | 6.743(R)| SLOW | -6.262(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<19> | 6.572(R)| SLOW | -6.089(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<20> | 6.759(R)| SLOW | -6.283(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<21> | 6.761(R)| SLOW | -6.281(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<22> | 5.920(R)| SLOW | -5.439(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<23> | 6.098(R)| SLOW | -5.613(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<24> | 5.844(R)| SLOW | -5.368(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<25> | 6.142(R)| SLOW | -5.654(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<26> | 5.789(R)| SLOW | -5.306(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<27> | 5.983(R)| SLOW | -5.495(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<28> | 6.457(R)| SLOW | -5.983(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<29> | 6.687(R)| SLOW | -6.209(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<30> | 6.812(R)| SLOW | -6.324(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<31> | 7.735(R)| SLOW | -7.124(R)| SLOW |Si57x_BUFG | 0.000|
VmeGaP_in | 9.887(R)| SLOW | -6.243(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<0> | 9.856(R)| SLOW | -5.418(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<1> | 9.955(R)| SLOW | -5.021(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<2> | 9.562(R)| SLOW | -5.284(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<3> | 9.445(R)| SLOW | -5.801(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<4> | 9.248(R)| SLOW | -5.604(R)| SLOW |Si57x_BUFG | 0.000|
VmeIackIn_in | 10.242(R)| SLOW | -8.858(R)| SLOW |Si57x_BUFG | 0.000|
VmeIack_in | 9.352(R)| SLOW | -7.087(R)| SLOW |Si57x_BUFG | 0.000|
VmeLword_io | 9.023(R)| SLOW | -4.222(R)| SLOW |Si57x_BUFG | 0.000|
VmeSysReset_in | 6.382(R)| FAST | -5.924(R)| SLOW |Si57x_BUFG | 0.000|
VmeWrite_in | 6.812(R)| SLOW | -6.119(R)| SLOW |Si57x_BUFG | 0.000|
--------------------+------------+------------+------------+------------+------------------+--------+
Setup/Hold to clock Si57x_ikn
--------------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
--------------------+------------+------------+------------+------------+------------------+--------+
FlashAFpgaQ_i | 6.562(R)| SLOW | -5.754(R)| FAST |Si57x_BUFG | 0.000|
FlashSFpgaQ_i | 7.665(R)| SLOW | -6.847(R)| FAST |Si57x_BUFG | 0.000|
ManualAddress_ib5<0>| 8.462(R)| SLOW | -6.490(R)| SLOW |Si57x_BUFG | 0.000|
ManualAddress_ib5<1>| 7.242(R)| SLOW | -5.283(R)| SLOW |Si57x_BUFG | 0.000|
ManualAddress_ib5<2>| 8.627(R)| SLOW | -6.655(R)| SLOW |Si57x_BUFG | 0.000|
ManualAddress_ib5<3>| 9.303(R)| SLOW | -7.320(R)| FAST |Si57x_BUFG | 0.000|
ManualAddress_ib5<4>| 8.701(R)| SLOW | -6.738(R)| SLOW |Si57x_BUFG | 0.000|
PllDdsLd_i | 9.368(R)| SLOW | -8.849(R)| FAST |Si57x_BUFG | 0.000|
PllDdsRefMon_i | 8.620(R)| SLOW | -7.994(R)| SLOW |Si57x_BUFG | 0.000|
PllDdsSdo_i | 11.483(R)| SLOW | -10.675(R)| FAST |Si57x_BUFG | 0.000|
PllDdsStatus_i | 9.664(R)| SLOW | -9.130(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Ld_i | 8.141(R)| SLOW | -7.612(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1RefMon_i | 8.856(R)| SLOW | -8.235(R)| SLOW |Si57x_BUFG | 0.000|
PllFmc1Sdo_i | 8.948(R)| SLOW | -8.140(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Status_i | 9.157(R)| SLOW | -8.638(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Ld_i | 6.906(R)| SLOW | -6.285(R)| SLOW |Si57x_BUFG | 0.000|
PllFmc2RefMon_i | 8.904(R)| SLOW | -8.385(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Sdo_i | 6.183(R)| SLOW | -5.375(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Status_i | 7.664(R)| SLOW | -7.038(R)| SLOW |Si57x_BUFG | 0.000|
PllSysLd_i | 7.167(R)| SLOW | -6.632(R)| FAST |Si57x_BUFG | 0.000|
PllSysRefMon_i | 7.387(R)| SLOW | -6.831(R)| FAST |Si57x_BUFG | 0.000|
PllSysSdo_i | 8.441(R)| SLOW | -7.633(R)| FAST |Si57x_BUFG | 0.000|
PllSysStatus_i | 6.791(R)| SLOW | -6.288(R)| FAST |Si57x_BUFG | 0.000|
PushButton_ion | 1.973(R)| FAST | -1.515(R)| SLOW |Si57x_BUFG | 0.000|
UseGa_i | 9.071(R)| SLOW | -6.303(R)| SLOW |Si57x_BUFG | 0.000|
VAdcDout_i | 8.522(R)| SLOW | -7.714(R)| FAST |Si57x_BUFG | 0.000|
VmeA_iob31<1> | 8.454(R)| SLOW | -7.156(R)| FAST |Si57x_BUFG | 0.000|
VmeA_iob31<2> | 7.574(R)| SLOW | -2.718(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<3> | 7.458(R)| SLOW | -2.521(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<4> | 5.216(R)| SLOW | -4.618(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<5> | 4.362(R)| SLOW | -3.177(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<6> | 3.991(R)| SLOW | -3.393(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<7> | 4.967(R)| SLOW | -4.369(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<8> | 3.511(R)| SLOW | -2.913(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<9> | 3.526(R)| SLOW | -2.928(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<10> | 4.972(R)| SLOW | -4.374(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<11> | 3.301(R)| SLOW | -2.840(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<12> | 4.946(R)| SLOW | -4.348(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<13> | 3.746(R)| SLOW | -3.148(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<14> | 5.247(R)| SLOW | -4.649(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<15> | 3.766(R)| SLOW | -3.168(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<16> | 3.271(R)| SLOW | -2.673(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<17> | 4.975(R)| SLOW | -4.514(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<18> | 4.771(R)| SLOW | -4.310(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<19> | 4.726(R)| SLOW | -4.128(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<20> | 5.206(R)| SLOW | -4.608(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<21> | 5.212(R)| SLOW | -4.614(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<22> | 3.526(R)| SLOW | -2.928(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<23> | 2.936(R)| SLOW | -2.082(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<24> | 5.410(R)| FAST | -4.917(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<25> | 5.169(R)| FAST | -4.676(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<26> | 5.583(R)| FAST | -5.090(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<27> | 3.985(R)| FAST | -3.492(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<28> | 3.619(R)| FAST | -3.150(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<29> | 1.220(R)| FAST | -0.751(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<30> | 3.419(R)| FAST | -2.786(R)| SLOW |Si57x_BUFG | 0.000|
VmeA_iob31<31> | 3.228(R)| FAST | -2.759(R)| SLOW |Si57x_BUFG | 0.000|
VmeAm_ib6<0> | 10.692(R)| SLOW | -7.861(R)| SLOW |Si57x_BUFG | 0.000|
VmeAm_ib6<3> | 10.452(R)| SLOW | -7.634(R)| SLOW |Si57x_BUFG | 0.000|
VmeAm_ib6<4> | 10.237(R)| SLOW | -7.444(R)| SLOW |Si57x_BUFG | 0.000|
VmeAm_ib6<5> | 9.055(R)| SLOW | -7.018(R)| SLOW |Si57x_BUFG | 0.000|
VmeAs_in | 5.552(R)| FAST | -5.059(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<0> | 8.258(R)| SLOW | -7.771(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<1> | 8.762(R)| SLOW | -8.274(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<2> | 8.516(R)| SLOW | -8.033(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<3> | 8.546(R)| SLOW | -8.068(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<4> | 8.227(R)| SLOW | -7.751(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<5> | 8.488(R)| SLOW | -8.008(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<6> | 7.051(R)| SLOW | -6.577(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<7> | 7.154(R)| SLOW | -6.676(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<8> | 6.286(R)| SLOW | -5.803(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<9> | 6.750(R)| SLOW | -6.132(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<10> | 6.251(R)| SLOW | -5.775(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<11> | 6.077(R)| SLOW | -5.601(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<12> | 6.107(R)| SLOW | -5.489(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<13> | 5.863(R)| SLOW | -5.389(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<14> | 5.631(R)| SLOW | -5.153(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<15> | 5.255(R)| SLOW | -4.642(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<16> | 7.418(R)| SLOW | -6.938(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<17> | 6.301(R)| SLOW | -5.825(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<18> | 6.742(R)| SLOW | -6.261(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<19> | 6.571(R)| SLOW | -6.088(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<20> | 6.758(R)| SLOW | -6.282(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<21> | 6.760(R)| SLOW | -6.280(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<22> | 5.919(R)| SLOW | -5.438(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<23> | 6.097(R)| SLOW | -5.612(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<24> | 5.843(R)| SLOW | -5.367(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<25> | 6.141(R)| SLOW | -5.653(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<26> | 5.788(R)| SLOW | -5.305(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<27> | 5.982(R)| SLOW | -5.494(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<28> | 6.456(R)| SLOW | -5.982(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<29> | 6.686(R)| SLOW | -6.208(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<30> | 6.811(R)| SLOW | -6.323(R)| SLOW |Si57x_BUFG | 0.000|
VmeD_iob32<31> | 7.734(R)| SLOW | -7.123(R)| SLOW |Si57x_BUFG | 0.000|
VmeGaP_in | 9.886(R)| SLOW | -6.242(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<0> | 9.855(R)| SLOW | -5.417(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<1> | 9.954(R)| SLOW | -5.020(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<2> | 9.561(R)| SLOW | -5.283(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<3> | 9.444(R)| SLOW | -5.800(R)| SLOW |Si57x_BUFG | 0.000|
VmeGa_ib5n<4> | 9.247(R)| SLOW | -5.603(R)| SLOW |Si57x_BUFG | 0.000|
VmeIackIn_in | 10.241(R)| SLOW | -8.857(R)| SLOW |Si57x_BUFG | 0.000|
VmeIack_in | 9.351(R)| SLOW | -7.086(R)| SLOW |Si57x_BUFG | 0.000|
VmeLword_io | 9.022(R)| SLOW | -4.221(R)| SLOW |Si57x_BUFG | 0.000|
VmeSysReset_in | 6.381(R)| FAST | -5.923(R)| SLOW |Si57x_BUFG | 0.000|
VmeWrite_in | 6.811(R)| SLOW | -6.118(R)| SLOW |Si57x_BUFG | 0.000|
--------------------+------------+------------+------------+------------+------------------+--------+
Setup/Hold to clock SysAppClk_ik
------------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------------+------------+------------+------------+------------+------------------+--------+
AFpgaProgD_iob8<4>| 1.884(R)| FAST | -1.499(R)| SLOW |SysAppClk_ik_BUFGP| 0.000|
AFpgaProgD_iob8<5>| 2.401(R)| FAST | -2.063(R)| SLOW |SysAppClk_ik_BUFGP| 0.000|
------------------+------------+------------+------------+------------+------------------+--------+
Clock Si57x_ik to Pad
------------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------------+-----------------+------------+-----------------+------------+------------------+--------+
AFpgaProgD_iob8<7>| 10.827(R)| SLOW | 8.702(R)| FAST |Si57x_BUFG | 0.000|
FlashAFpgaClk_ok | 15.012(R)| SLOW | 12.821(R)| FAST |Si57x_BUFG | 0.000|
FlashAFpgaCs_on | 13.800(R)| SLOW | 11.653(R)| FAST |Si57x_BUFG | 0.000|
FlashAFpgaD_o | 16.039(R)| SLOW | 13.666(R)| FAST |Si57x_BUFG | 0.000|
FlashSFpgaClk_ok | 15.546(R)| SLOW | 13.355(R)| FAST |Si57x_BUFG | 0.000|
FlashSFpgaCs_on | 15.584(R)| SLOW | 13.437(R)| FAST |Si57x_BUFG | 0.000|
FlashSFpgaD_o | 16.715(R)| SLOW | 14.342(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<0> | 9.978(R)| SLOW | 7.760(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<1> | 15.506(R)| SLOW | 12.800(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<3> | 11.564(R)| SLOW | 9.336(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<4> | 10.438(R)| SLOW | 8.269(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<7> | 13.630(R)| SLOW | 11.358(R)| FAST |Si57x_BUFG | 0.000|
PllDacDin_o | 15.984(R)| SLOW | 13.611(R)| FAST |Si57x_BUFG | 0.000|
PllDacSClk_ok | 14.443(R)| SLOW | 12.252(R)| FAST |Si57x_BUFG | 0.000|
PllDacSynch_on | 14.796(R)| SLOW | 12.649(R)| FAST |Si57x_BUFG | 0.000|
PllDdsCs_on | 18.866(R)| SLOW | 16.719(R)| FAST |Si57x_BUFG | 0.000|
PllDdsPd_on | 18.477(R)| SLOW | 16.286(R)| FAST |Si57x_BUFG | 0.000|
PllDdsRefSel_o | 16.653(R)| SLOW | 14.463(R)| FAST |Si57x_BUFG | 0.000|
PllDdsReset_orn | 20.312(R)| SLOW | 18.121(R)| FAST |Si57x_BUFG | 0.000|
PllDdsSClk_ok | 18.929(R)| SLOW | 16.738(R)| FAST |Si57x_BUFG | 0.000|
PllDdsSDio_io | 21.968(R)| SLOW | 19.595(R)| FAST |Si57x_BUFG | 0.000|
PllDdsSynch_on | 18.561(R)| SLOW | 16.372(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Cs_on | 13.632(R)| SLOW | 11.426(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Pd_on | 17.515(R)| SLOW | 15.326(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1RefSel_o | 17.130(R)| SLOW | 14.983(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Reset_orn | 17.584(R)| SLOW | 15.395(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1SClk_ok | 17.448(R)| SLOW | 15.257(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1SDio_io | 17.832(R)| SLOW | 15.459(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Synch_on | 16.962(R)| SLOW | 14.815(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Cs_on | 12.688(R)| SLOW | 10.541(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Pd_on | 14.632(R)| SLOW | 12.420(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2RefSel_o | 14.374(R)| SLOW | 12.227(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Reset_orn | 14.553(R)| SLOW | 12.406(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2SClk_ok | 16.653(R)| SLOW | 14.462(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2SDio_io | 14.822(R)| SLOW | 12.449(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Synch_on | 14.953(R)| SLOW | 12.764(R)| FAST |Si57x_BUFG | 0.000|
PllSysCs_on | 13.887(R)| SLOW | 11.740(R)| FAST |Si57x_BUFG | 0.000|
PllSysPd_on | 17.874(R)| SLOW | 15.683(R)| FAST |Si57x_BUFG | 0.000|
PllSysRefSel_o | 14.835(R)| SLOW | 12.623(R)| FAST |Si57x_BUFG | 0.000|
PllSysReset_orn | 16.939(R)| SLOW | 14.792(R)| FAST |Si57x_BUFG | 0.000|
PllSysSClk_ok | 14.409(R)| SLOW | 12.218(R)| FAST |Si57x_BUFG | 0.000|
PllSysSDio_io | 17.426(R)| SLOW | 15.053(R)| FAST |Si57x_BUFG | 0.000|
PllSysSynch_on | 14.788(R)| SLOW | 12.599(R)| FAST |Si57x_BUFG | 0.000|
SysAppSlow_iob2<1>| 18.161(R)| SLOW | 16.036(R)| FAST |Si57x_BUFG | 0.000|
SysAppSlow_iob2<2>| 14.147(R)| SLOW | 12.022(R)| FAST |Si57x_BUFG | 0.000|
VAdcCs_on | 15.573(R)| SLOW | 13.426(R)| FAST |Si57x_BUFG | 0.000|
VAdcDin_o | 17.731(R)| SLOW | 15.358(R)| FAST |Si57x_BUFG | 0.000|
VAdcSClk_ok | 17.423(R)| SLOW | 15.232(R)| FAST |Si57x_BUFG | 0.000|
VAdjCs_on | 18.249(R)| SLOW | 16.102(R)| FAST |Si57x_BUFG | 0.000|
VAdjDin_o | 19.508(R)| SLOW | 17.135(R)| FAST |Si57x_BUFG | 0.000|
VAdjSClk_ok | 18.218(R)| SLOW | 16.027(R)| FAST |Si57x_BUFG | 0.000|
VmeDDirVfcToVme_o | 17.452(R)| SLOW | 15.261(R)| FAST |Si57x_BUFG | 0.000|
VmeDOeN_oen | 20.039(R)| SLOW | 17.789(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<0> | 18.994(R)| SLOW | 15.325(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<1> | 19.431(R)| SLOW | 15.198(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<2> | 19.419(R)| SLOW | 15.319(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<3> | 19.760(R)| SLOW | 15.256(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<4> | 18.674(R)| SLOW | 14.864(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<5> | 19.180(R)| SLOW | 14.864(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<6> | 17.109(R)| SLOW | 13.431(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<7> | 17.707(R)| SLOW | 13.431(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<8> | 16.943(R)| SLOW | 13.455(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<9> | 17.187(R)| SLOW | 13.455(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<10> | 16.588(R)| SLOW | 12.957(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<11> | 16.317(R)| SLOW | 12.981(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<12> | 16.308(R)| SLOW | 12.981(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<13> | 16.289(R)| SLOW | 12.744(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<14> | 16.323(R)| SLOW | 12.494(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<15> | 16.088(R)| SLOW | 12.494(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<16> | 16.952(R)| SLOW | 14.038(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<17> | 16.567(R)| SLOW | 13.759(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<18> | 17.030(R)| SLOW | 13.679(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<19> | 17.566(R)| SLOW | 14.811(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<20> | 17.092(R)| SLOW | 14.308(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<21> | 16.829(R)| SLOW | 14.012(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<22> | 16.830(R)| SLOW | 14.012(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<23> | 16.915(R)| SLOW | 13.944(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<24> | 16.923(R)| SLOW | 14.099(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<25> | 16.922(R)| SLOW | 13.977(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<26> | 16.846(R)| SLOW | 13.909(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<27> | 16.598(R)| SLOW | 13.723(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<28> | 16.277(R)| SLOW | 13.326(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<29> | 16.773(R)| SLOW | 13.920(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<30> | 16.458(R)| SLOW | 13.465(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<31> | 16.629(R)| SLOW | 13.920(R)| FAST |Si57x_BUFG | 0.000|
VmeDtAckOe_oe | 19.883(R)| SLOW | 17.633(R)| FAST |Si57x_BUFG | 0.000|
VmeIackOut_on | 17.691(R)| SLOW | 15.544(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<1> | 18.205(R)| SLOW | 15.896(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<2> | 19.363(R)| SLOW | 17.054(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<3> | 19.751(R)| SLOW | 17.442(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<4> | 16.829(R)| SLOW | 14.501(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<5> | 16.345(R)| SLOW | 14.017(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<6> | 16.485(R)| SLOW | 14.235(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<7> | 18.561(R)| SLOW | 16.269(R)| FAST |Si57x_BUFG | 0.000|
------------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock Si57x_ikn to Pad
------------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------------+-----------------+------------+-----------------+------------+------------------+--------+
AFpgaProgD_iob8<7>| 10.828(R)| SLOW | 8.703(R)| FAST |Si57x_BUFG | 0.000|
FlashAFpgaClk_ok | 15.013(R)| SLOW | 12.822(R)| FAST |Si57x_BUFG | 0.000|
FlashAFpgaCs_on | 13.801(R)| SLOW | 11.654(R)| FAST |Si57x_BUFG | 0.000|
FlashAFpgaD_o | 16.040(R)| SLOW | 13.667(R)| FAST |Si57x_BUFG | 0.000|
FlashSFpgaClk_ok | 15.547(R)| SLOW | 13.356(R)| FAST |Si57x_BUFG | 0.000|
FlashSFpgaCs_on | 15.585(R)| SLOW | 13.438(R)| FAST |Si57x_BUFG | 0.000|
FlashSFpgaD_o | 16.716(R)| SLOW | 14.343(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<0> | 9.979(R)| SLOW | 7.761(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<1> | 15.507(R)| SLOW | 12.801(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<3> | 11.565(R)| SLOW | 9.337(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<4> | 10.439(R)| SLOW | 8.270(R)| FAST |Si57x_BUFG | 0.000|
FpLed_onb8<7> | 13.631(R)| SLOW | 11.359(R)| FAST |Si57x_BUFG | 0.000|
PllDacDin_o | 15.985(R)| SLOW | 13.612(R)| FAST |Si57x_BUFG | 0.000|
PllDacSClk_ok | 14.444(R)| SLOW | 12.253(R)| FAST |Si57x_BUFG | 0.000|
PllDacSynch_on | 14.797(R)| SLOW | 12.650(R)| FAST |Si57x_BUFG | 0.000|
PllDdsCs_on | 18.867(R)| SLOW | 16.720(R)| FAST |Si57x_BUFG | 0.000|
PllDdsPd_on | 18.478(R)| SLOW | 16.287(R)| FAST |Si57x_BUFG | 0.000|
PllDdsRefSel_o | 16.654(R)| SLOW | 14.464(R)| FAST |Si57x_BUFG | 0.000|
PllDdsReset_orn | 20.313(R)| SLOW | 18.122(R)| FAST |Si57x_BUFG | 0.000|
PllDdsSClk_ok | 18.930(R)| SLOW | 16.739(R)| FAST |Si57x_BUFG | 0.000|
PllDdsSDio_io | 21.969(R)| SLOW | 19.596(R)| FAST |Si57x_BUFG | 0.000|
PllDdsSynch_on | 18.562(R)| SLOW | 16.373(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Cs_on | 13.633(R)| SLOW | 11.427(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Pd_on | 17.516(R)| SLOW | 15.327(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1RefSel_o | 17.131(R)| SLOW | 14.984(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Reset_orn | 17.585(R)| SLOW | 15.396(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1SClk_ok | 17.449(R)| SLOW | 15.258(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1SDio_io | 17.833(R)| SLOW | 15.460(R)| FAST |Si57x_BUFG | 0.000|
PllFmc1Synch_on | 16.963(R)| SLOW | 14.816(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Cs_on | 12.689(R)| SLOW | 10.542(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Pd_on | 14.633(R)| SLOW | 12.421(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2RefSel_o | 14.375(R)| SLOW | 12.228(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Reset_orn | 14.554(R)| SLOW | 12.407(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2SClk_ok | 16.654(R)| SLOW | 14.463(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2SDio_io | 14.823(R)| SLOW | 12.450(R)| FAST |Si57x_BUFG | 0.000|
PllFmc2Synch_on | 14.954(R)| SLOW | 12.765(R)| FAST |Si57x_BUFG | 0.000|
PllSysCs_on | 13.888(R)| SLOW | 11.741(R)| FAST |Si57x_BUFG | 0.000|
PllSysPd_on | 17.875(R)| SLOW | 15.684(R)| FAST |Si57x_BUFG | 0.000|
PllSysRefSel_o | 14.836(R)| SLOW | 12.624(R)| FAST |Si57x_BUFG | 0.000|
PllSysReset_orn | 16.940(R)| SLOW | 14.793(R)| FAST |Si57x_BUFG | 0.000|
PllSysSClk_ok | 14.410(R)| SLOW | 12.219(R)| FAST |Si57x_BUFG | 0.000|
PllSysSDio_io | 17.427(R)| SLOW | 15.054(R)| FAST |Si57x_BUFG | 0.000|
PllSysSynch_on | 14.789(R)| SLOW | 12.600(R)| FAST |Si57x_BUFG | 0.000|
SysAppSlow_iob2<1>| 18.162(R)| SLOW | 16.037(R)| FAST |Si57x_BUFG | 0.000|
SysAppSlow_iob2<2>| 14.148(R)| SLOW | 12.023(R)| FAST |Si57x_BUFG | 0.000|
VAdcCs_on | 15.574(R)| SLOW | 13.427(R)| FAST |Si57x_BUFG | 0.000|
VAdcDin_o | 17.732(R)| SLOW | 15.359(R)| FAST |Si57x_BUFG | 0.000|
VAdcSClk_ok | 17.424(R)| SLOW | 15.233(R)| FAST |Si57x_BUFG | 0.000|
VAdjCs_on | 18.250(R)| SLOW | 16.103(R)| FAST |Si57x_BUFG | 0.000|
VAdjDin_o | 19.509(R)| SLOW | 17.136(R)| FAST |Si57x_BUFG | 0.000|
VAdjSClk_ok | 18.219(R)| SLOW | 16.028(R)| FAST |Si57x_BUFG | 0.000|
VmeDDirVfcToVme_o | 17.453(R)| SLOW | 15.262(R)| FAST |Si57x_BUFG | 0.000|
VmeDOeN_oen | 20.040(R)| SLOW | 17.790(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<0> | 18.995(R)| SLOW | 15.326(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<1> | 19.432(R)| SLOW | 15.199(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<2> | 19.420(R)| SLOW | 15.320(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<3> | 19.761(R)| SLOW | 15.257(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<4> | 18.675(R)| SLOW | 14.865(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<5> | 19.181(R)| SLOW | 14.865(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<6> | 17.110(R)| SLOW | 13.432(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<7> | 17.708(R)| SLOW | 13.432(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<8> | 16.944(R)| SLOW | 13.456(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<9> | 17.188(R)| SLOW | 13.456(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<10> | 16.589(R)| SLOW | 12.958(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<11> | 16.318(R)| SLOW | 12.982(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<12> | 16.309(R)| SLOW | 12.982(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<13> | 16.290(R)| SLOW | 12.745(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<14> | 16.324(R)| SLOW | 12.495(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<15> | 16.089(R)| SLOW | 12.495(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<16> | 16.953(R)| SLOW | 14.039(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<17> | 16.568(R)| SLOW | 13.760(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<18> | 17.031(R)| SLOW | 13.680(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<19> | 17.567(R)| SLOW | 14.812(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<20> | 17.093(R)| SLOW | 14.309(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<21> | 16.830(R)| SLOW | 14.013(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<22> | 16.831(R)| SLOW | 14.013(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<23> | 16.916(R)| SLOW | 13.945(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<24> | 16.924(R)| SLOW | 14.100(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<25> | 16.923(R)| SLOW | 13.978(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<26> | 16.847(R)| SLOW | 13.910(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<27> | 16.599(R)| SLOW | 13.724(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<28> | 16.278(R)| SLOW | 13.327(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<29> | 16.774(R)| SLOW | 13.921(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<30> | 16.459(R)| SLOW | 13.466(R)| FAST |Si57x_BUFG | 0.000|
VmeD_iob32<31> | 16.630(R)| SLOW | 13.921(R)| FAST |Si57x_BUFG | 0.000|
VmeDtAckOe_oe | 19.884(R)| SLOW | 17.634(R)| FAST |Si57x_BUFG | 0.000|
VmeIackOut_on | 17.692(R)| SLOW | 15.545(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<1> | 18.206(R)| SLOW | 15.897(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<2> | 19.364(R)| SLOW | 17.055(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<3> | 19.752(R)| SLOW | 17.443(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<4> | 16.830(R)| SLOW | 14.502(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<5> | 16.346(R)| SLOW | 14.018(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<6> | 16.486(R)| SLOW | 14.236(R)| FAST |Si57x_BUFG | 0.000|
VmeIrq_ob7<7> | 18.562(R)| SLOW | 16.270(R)| FAST |Si57x_BUFG | 0.000|
------------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock VcTcXo_ik to Pad
-------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
-------------+-----------------+------------+-----------------+------------+------------------+--------+
FpLed_onb8<5>| 12.442(R)| SLOW | 10.248(R)| FAST |VcTcXo_ik_BUFGP | 0.000|
FpLed_onb8<7>| 13.030(R)| SLOW | 10.733(R)| FAST |VcTcXo_ik_BUFGP | 0.000|
-------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock VmeSysClk_ik to Pad
-------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
-------------+-----------------+------------+-----------------+------------+------------------+--------+
FpLed_onb8<6>| 16.260(R)| SLOW | 14.051(R)| FAST |VmeSysClk_ik_BUFGP| 0.000|
FpLed_onb8<7>| 17.132(R)| SLOW | 14.820(R)| FAST |VmeSysClk_ik_BUFGP| 0.000|
-------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock Si57x_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 9.190| | | |
Si57x_ikn | 9.190| | | |
SysAppClk_ik | 2.260| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock Si57x_ikn
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 9.190| | | |
Si57x_ikn | 9.190| | | |
SysAppClk_ik | 2.260| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 3.395| | | |
Si57x_ikn | 3.395| | | |
SysAppClk_ik | 3.322| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VcTcXo_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VcTcXo_ik | 2.157| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VmeSysClk_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VmeSysClk_ik | 2.243| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
Si57x_ik |PllDdsClk_ok | 20.468|
Si57x_ik |PllFmc1Ref1_ok | 19.950|
Si57x_ik |PllFmc2Ref1_ok | 18.753|
Si57x_ik |PllSysRef12_ok | 17.542|
Si57x_ik |PllSysRef12_okn| 17.590|
Si57x_ik |SysAppClk_ok | 16.217|
Si57x_ikn |PllDdsClk_ok | 20.469|
Si57x_ikn |PllFmc1Ref1_ok | 19.951|
Si57x_ikn |PllFmc2Ref1_ok | 18.754|
Si57x_ikn |PllSysRef12_ok | 17.543|
Si57x_ikn |PllSysRef12_okn| 17.591|
Si57x_ikn |SysAppClk_ok | 16.218|
Switch_ib2<0> |FpLed_onb8<7> | 11.754|
Switch_ib2<1> |FpLed_onb8<7> | 11.679|
UseGa_i |FpLed_onb8<2> | 15.110|
VmeGaP_in |FpLed_onb8<2> | 16.469|
VmeGa_ib5n<0> |FpLed_onb8<2> | 16.438|
VmeGa_ib5n<1> |FpLed_onb8<2> | 16.537|
VmeGa_ib5n<2> |FpLed_onb8<2> | 16.144|
VmeGa_ib5n<3> |FpLed_onb8<2> | 16.027|
VmeGa_ib5n<4> |FpLed_onb8<2> | 15.830|
---------------+---------------+---------+
Analysis completed Thu Dec 16 17:57:33 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 272 MB
trunk/firmware/XilinxISE/SystemFpga/SFpga_preroute.twx 0 → 100644
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trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.html 0 → 100644
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (12/16/2010 - 18:45:27)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>SystemFpga.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>SFpga</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx150t-3fgg676</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>319 Warnings (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 &nbsp;<A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>796</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>796</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>917</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>891</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>571</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>154</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>166</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
<TD ALIGN=RIGHT>11</TD>
<TD ALIGN=RIGHT>21,680</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Dual Port RAM</TD>
<TD ALIGN=RIGHT>8</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>4</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>4</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Single Port RAM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD>
<TD ALIGN=RIGHT>3</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>3</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>15</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>6</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>9</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>371</TD>
<TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>1,113</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>382</TD>
<TD ALIGN=RIGHT>1,113</TD>
<TD ALIGN=RIGHT>34%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>196</TD>
<TD ALIGN=RIGHT>1,113</TD>
<TD ALIGN=RIGHT>17%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>535</TD>
<TD ALIGN=RIGHT>1,113</TD>
<TD ALIGN=RIGHT>48%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>32</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>85</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>330</TD>
<TD ALIGN=RIGHT>396</TD>
<TD ALIGN=RIGHT>83%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>328</TD>
<TD ALIGN=RIGHT>330</TD>
<TD ALIGN=RIGHT>99%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Master Pads</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Slave Pads</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>268</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>536</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>25%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
<TD ALIGN=RIGHT>4</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>12</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>586</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>586</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>586</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>384</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>180</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GTPA1_DUALs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCIE_A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.02</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Dec 16 18:41:15 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>126 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (2 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Dec 16 18:41:24 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Dec 16 18:43:00 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Dec 16 18:44:11 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>49 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Dec 16 18:44:36 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Dec 16 18:45:20 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>47 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Dec 16 17:57:34 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed Dec 15 15:16:36 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Dec 16 18:45:20 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Dec 16 18:45:27 2010</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 12/16/2010 - 18:45:28</center>
</BODY></HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="9">
<CmdHistory>
</CmdHistory>
</DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_usage.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="9">
<DesignStatistics TimeStamp="Thu Dec 16 18:45:18 2010"><group name="NetStatistics">
<item name="NumNets_Active" rev="9">
<attrib name="value" value="1863"/></item>
<item name="NumNets_Gnd" rev="9">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="9">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="9">
<attrib name="value" value="39"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="9">
<attrib name="value" value="205"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="9">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="9">
<attrib name="value" value="15"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="9">
<attrib name="value" value="253"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="9">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="9">
<attrib name="value" value="301"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="9">
<attrib name="value" value="1944"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="9">
<attrib name="value" value="358"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="9">
<attrib name="value" value="137"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="9">
<attrib name="value" value="50"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="9">
<attrib name="value" value="245"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="9">
<attrib name="value" value="245"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="9">
<attrib name="value" value="3687"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="9">
<attrib name="value" value="1558"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="9">
<attrib name="value" value="1419"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="9">
<attrib name="value" value="137"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="9">
<attrib name="value" value="116"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="9">
<attrib name="value" value="850"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="9">
<attrib name="value" value="4252"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="9">
<attrib name="value" value="5340"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="9">
<attrib name="value" value="298"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="9">
<attrib name="value" value="2304"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="9">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="9">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="9">
<attrib name="value" value="132"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="9">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="9">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="9">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="9">
<attrib name="value" value="342"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="9">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="9">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="9">
<attrib name="value" value="354"/></item>
<item name="NumNodesOfType_Vcc_REGINPUT" rev="9">
<attrib name="value" value="11"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="8">
<attrib name="value" value="330"/></item>
<item name="AGG_IO" rev="8">
<attrib name="value" value="330"/></item>
<item name="AGG_LOCED_IO" rev="8">
<attrib name="value" value="328"/></item>
<item name="AGG_SLICE" rev="8">
<attrib name="value" value="371"/></item>
<item name="NUM_BONDED_IOB" rev="8">
<attrib name="value" value="326"/></item>
<item name="NUM_BONDED_IOBM" rev="8">
<attrib name="value" value="2"/></item>
<item name="NUM_BONDED_IOBS" rev="8">
<attrib name="value" value="2"/></item>
<item name="NUM_BSFULL" rev="8">
<attrib name="value" value="535"/></item>
<item name="NUM_BSLUTONLY" rev="8">
<attrib name="value" value="382"/></item>
<item name="NUM_BSREGONLY" rev="8">
<attrib name="value" value="196"/></item>
<item name="NUM_BSUSED" rev="8">
<attrib name="value" value="1113"/></item>
<item name="NUM_BUFG" rev="8">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O5ANDO6" rev="8">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O6ONLY" rev="8">
<attrib name="value" value="4"/></item>
<item name="NUM_LOCED_IOB" rev="8">
<attrib name="value" value="324"/></item>
<item name="NUM_LOCED_IOBM" rev="8">
<attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOBS" rev="8">
<attrib name="value" value="2"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="8">
<attrib name="value" value="166"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="8">
<attrib name="value" value="154"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="8">
<attrib name="value" value="571"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="8">
<attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="8">
<attrib name="value" value="6"/></item>
<item name="NUM_LUT_RT_EXO5" rev="8">
<attrib name="value" value="6"/></item>
<item name="NUM_LUT_RT_EXO6" rev="8">
<attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT_O5" rev="8">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_O6" rev="8">
<attrib name="value" value="154"/></item>
<item name="NUM_SLICEL" rev="8">
<attrib name="value" value="70"/></item>
<item name="NUM_SLICEM" rev="8">
<attrib name="value" value="4"/></item>
<item name="NUM_SLICEX" rev="8">
<attrib name="value" value="297"/></item>
<item name="NUM_SLICE_CARRY4" rev="8">
<attrib name="value" value="52"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="8">
<attrib name="value" value="32"/></item>
<item name="NUM_SLICE_CYINIT" rev="8">
<attrib name="value" value="1259"/></item>
<item name="NUM_SLICE_F7MUX" rev="8">
<attrib name="value" value="18"/></item>
<item name="NUM_SLICE_FF" rev="8">
<attrib name="value" value="796"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="8">
<attrib name="value" value="118"/></item>
<item name="NUM_SRL_O6ONLY" rev="8">
<attrib name="value" value="3"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="8">
<attrib name="value" value="85"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="9">
<attrib name="value" value="4"/></item>
<item name="IOB-IOBM" rev="9">
<attrib name="value" value="161"/></item>
<item name="IOB-IOBS" rev="9">
<attrib name="value" value="165"/></item>
<item name="SLICEL-SLICEM" rev="9">
<attrib name="value" value="33"/></item>
<item name="SLICEX-SLICEL" rev="9">
<attrib name="value" value="76"/></item>
<item name="SLICEX-SLICEM" rev="9">
<attrib name="value" value="65"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Thu Dec 16 18:45:18 2010"><group name="SiteSummary">
<item name="BUFG" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="BUFG_BUFG" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="CARRY4" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="52"/></item>
<item name="FF_SR" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="73"/></item>
<item name="HARD0" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="IOB" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="326"/></item>
<item name="IOBM" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBM_OUTBUF" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBS" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB_IMUX" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="159"/></item>
<item name="IOB_INBUF" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="159"/></item>
<item name="IOB_OUTBUF" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="198"/></item>
<item name="LUT5" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="333"/></item>
<item name="LUT6" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="900"/></item>
<item name="LUT_OR_MEM5" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="LUT_OR_MEM6" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="NULLMUX" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="PAD" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="330"/></item>
<item name="REG_SR" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="723"/></item>
<item name="SELMUX2_1" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
<item name="SLICEL" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="70"/></item>
<item name="SLICEM" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="SLICEX" rev="9">
<attrib name="total" value="1000000"/><attrib name="used" value="297"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Thu Dec 16 18:45:18 2010"><group name="REG_SR">
<item name="CK" rev="9">
<attrib name="CK" value="723"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="9">
<attrib name="FF" value="723"/></item>
<item name="SRINIT" rev="9">
<attrib name="SRINIT0" value="671"/><attrib name="SRINIT1" value="52"/></item>
<item name="SYNC_ATTR" rev="9">
<attrib name="ASYNC" value="252"/><attrib name="SYNC" value="471"/></item>
</group>
<group name="LUT_OR_MEM5">
<item name="CLK" rev="9">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="9">
<attrib name="RAM" value="4"/></item>
<item name="RAMMODE" rev="9">
<attrib name="DPRAM32" value="4"/></item>
</group>
<group name="LUT_OR_MEM6">
<item name="CLK" rev="9">
<attrib name="CLK" value="11"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="9">
<attrib name="RAM" value="11"/></item>
<item name="RAMMODE" rev="9">
<attrib name="SRL16" value="3"/><attrib name="DPRAM32" value="4"/><attrib name="DPRAM64" value="4"/></item>
</group>
<group name="IOBM_OUTBUF">
<item name="SUSPEND" rev="9">
<attrib name="3STATE" value="2"/></item>
</group>
<group name="SLICEL">
<item name="CLK" rev="9">
<attrib name="CLK" value="40"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="SLICEM">
<item name="CLK" rev="9">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="9">
<attrib name="12" value="167"/></item>
<item name="SLEW" rev="9">
<attrib name="SLOW" value="167"/></item>
<item name="SUSPEND" rev="9">
<attrib name="3STATE" value="198"/></item>
</group>
<group name="SLICEX">
<item name="CLK" rev="9">
<attrib name="CLK" value="209"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_INBUF">
<item name="DIFF_TERM" rev="9">
<attrib name="TRUE" value="1"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="9">
<attrib name="CK" value="73"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="9">
<attrib name="SRINIT0" value="62"/><attrib name="SRINIT1" value="11"/></item>
<item name="SYNC_ATTR" rev="9">
<attrib name="ASYNC" value="37"/><attrib name="SYNC" value="36"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Thu Dec 16 18:45:18 2010"><group name="NULLMUX">
<item name="0" rev="9">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="9">
<attrib name="value" value="3"/></item>
</group>
<group name="REG_SR">
<item name="CE" rev="9">
<attrib name="value" value="401"/></item>
<item name="CK" rev="9">
<attrib name="value" value="723"/></item>
<item name="D" rev="9">
<attrib name="value" value="723"/></item>
<item name="Q" rev="9">
<attrib name="value" value="723"/></item>
<item name="SR" rev="9">
<attrib name="value" value="472"/></item>
</group>
<group name="LUT_OR_MEM5">
<item name="A1" rev="9">
<attrib name="value" value="4"/></item>
<item name="A2" rev="9">
<attrib name="value" value="4"/></item>
<item name="A3" rev="9">
<attrib name="value" value="4"/></item>
<item name="A4" rev="9">
<attrib name="value" value="4"/></item>
<item name="A5" rev="9">
<attrib name="value" value="4"/></item>
<item name="CLK" rev="9">
<attrib name="value" value="4"/></item>
<item name="DI1" rev="9">
<attrib name="value" value="4"/></item>
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<item name="OUTN" rev="9">
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<item name="DQ" rev="9">
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<attrib name="value" value="7"/></item>
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<attrib name="value" value="3"/></item>
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<attrib name="value" value="1"/></item>
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<attrib name="value" value="2"/></item>
<item name="BI" rev="9">
<attrib name="value" value="1"/></item>
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<attrib name="value" value="1"/></item>
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<attrib name="value" value="1"/></item>
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<attrib name="value" value="1"/></item>
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<attrib name="value" value="3"/></item>
<item name="CE" rev="9">
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<item name="CI" rev="9">
<attrib name="value" value="2"/></item>
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<item name="D1" rev="9">
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<item name="IN" rev="9">
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<item name="TRI" rev="9">
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<item name="SR" rev="9">
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<item name="PAD" rev="9">
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<group name="IOB_INBUF">
<item name="DIFFI_IN" rev="9">
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<item name="PAD" rev="9">
<attrib name="value" value="159"/></item>
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<item name="DI3" rev="9">
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<item name="O2" rev="9">
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<item name="O3" rev="9">
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<item name="S1" rev="9">
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<item name="S2" rev="9">
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<item name="S3" rev="9">
<attrib name="value" value="46"/></item>
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<group name="IOBS">
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<item name="PAD" rev="9">
<attrib name="value" value="2"/></item>
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<group name="LUT5">
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<item name="A2" rev="9">
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<item name="A3" rev="9">
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<item name="A4" rev="9">
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<item name="A5" rev="9">
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<item name="O5" rev="9">
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<item name="A2" rev="9">
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<item name="A3" rev="9">
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<item name="A4" rev="9">
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<item name="A5" rev="9">
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<item name="A6" rev="9">
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<item name="O6" rev="9">
<attrib name="value" value="900"/></item>
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<group name="SELMUX2_1">
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<item name="OUT" rev="9">
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<item name="S0" rev="9">
<attrib name="value" value="18"/></item>
</group>
<group name="IOB_IMUX">
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<attrib name="value" value="159"/></item>
</group>
<group name="IOB">
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<attrib name="value" value="1"/></item>
<item name="I" rev="9">
<attrib name="value" value="159"/></item>
<item name="O" rev="9">
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<item name="PAD" rev="9">
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<item name="PADOUT" rev="9">
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<item name="T" rev="9">
<attrib name="value" value="44"/></item>
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<item name="0" rev="9">
<attrib name="value" value="11"/></item>
</group>
<group name="FF_SR">
<item name="CE" rev="9">
<attrib name="value" value="40"/></item>
<item name="CK" rev="9">
<attrib name="value" value="73"/></item>
<item name="D" rev="9">
<attrib name="value" value="73"/></item>
<item name="Q" rev="9">
<attrib name="value" value="73"/></item>
<item name="SR" rev="9">
<attrib name="value" value="36"/></item>
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<group name="BUFG">
<item name="I0" rev="9">
<attrib name="value" value="4"/></item>
<item name="O" rev="9">
<attrib name="value" value="4"/></item>
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</ReportPinData>
<CmdHistory>
</CmdHistory>
</DeviceUsageSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Dec 16 18:40:47 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
</row>
</table>
</section>
<section stringID="XST_OPTION_SUMMARY">
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="SFpga.prj"/>
<item DEFAULT="Mixed" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="SFpga"/>
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
<item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx150t-3-fgg676"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="SFpga"/>
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
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trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise 0 → 100644
View file @ 23b1b4b5
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<transform xil_pn:end_ts="1292521276" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292521245">
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<outfile xil_pn:name="SFpga.lso"/>
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<outfile xil_pn:name="SFpga.prj"/>
<outfile xil_pn:name="SFpga.stx"/>
<outfile xil_pn:name="SFpga.syr"/>
<outfile xil_pn:name="SFpga.xst"/>
<outfile xil_pn:name="SFpga_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1292520620" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1292520620">
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<transform xil_pn:end_ts="1292521285" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292521276">
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<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<transform xil_pn:end_ts="1292521380" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292521285">
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<outfile xil_pn:name="SFpga_map.ncd"/>
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<outfile xil_pn:name="SFpga_summary.xml"/>
<outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
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<transform xil_pn:end_ts="1292521476" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292521380">
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<outfile xil_pn:name="SFpga.ptwx"/>
<outfile xil_pn:name="SFpga.unroutes"/>
<outfile xil_pn:name="SFpga.xpi"/>
<outfile xil_pn:name="SFpga_pad.csv"/>
<outfile xil_pn:name="SFpga_pad.txt"/>
<outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
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<transform xil_pn:end_ts="1292521527" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292521476">
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<outfile xil_pn:name="SFpga.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="sfpga.bgn"/>
<outfile xil_pn:name="sfpga.bit"/>
<outfile xil_pn:name="sfpga.drc"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
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<transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570">
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<transform xil_pn:end_ts="1292521476" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292521451">
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<transform xil_pn:end_ts="1292518654" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791353" xil_pn:start_ts="1292518630">
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<transform xil_pn:end_ts="1292518697" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1292518697">
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</generated_project>
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.xise 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
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<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
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<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="SFpga" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg676" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SFpga_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="SFpga_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SFpga_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SFpga_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="SFpga.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="SystemFpga" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-12-15T15:02:16" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F6031676C5FE434A8E9F8A1057A8E48F" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst 0 → 100644
View file @ 23b1b4b5
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292521275
OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/bitgen.xmsgs 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;4&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;5&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;7&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsSyncClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRModeDef0_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeTrst_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsSDo_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PllDacDout_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeP0LvdsTClkIn_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPllLock_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Sfp2ModeDef0_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Sfp2LoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRTxFault_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeAm_ib6&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Sfp2TxFault_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeP0LvdsBunchClkIn_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">TempIdDQ_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsDrOver_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRLoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsSyncSmpErr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeTdi_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeTck_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Fmc1PrsntM2C_in_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeTms_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Fmc2PrsntM2C_in_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/ibiswriter.xmsgs 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="PostProcessors" num="123" delta="new" >Uppercase letters not recommended in file names. Refer to the IBIS Specification (http://www.eigroup.org/ibis/ibis.htm) for allowed characters.
</msg>
<msg type="warning" file="PostProcessors" num="0" delta="new" >IBIS model <arg fmt="%s" index="1">LVDS_25_LR_25</arg> for I/O port <arg fmt="%s" index="2">Si57x_ik</arg> (pin <arg fmt="%s" index="3">R7</arg>) could not be found. This signal will be listed as a no connect (NC) in the output file.
</msg>
<msg type="warning" file="PostProcessors" num="0" delta="new" >IBIS model <arg fmt="%s" index="1">LVDS_25_LR_25</arg> for I/O port <arg fmt="%s" index="2">Si57x_ikn</arg> (pin <arg fmt="%s" index="3">R6</arg>) could not be found. This signal will be listed as a no connect (NC) in the output file.
</msg>
<msg type="warning" file="PostProcessors" num="0" delta="new" >
Xilinx IBISWriter has detected pins without buffer models. No IBIS model data is available for these I/O standards. This may be due to either of the following cases.
(1) The latest IBIS I/O model data has not yet been installed for <arg fmt="%s" index="1">spartan6</arg>. Please run XilinxUpdate to check availability of updated <arg fmt="%s" index="2">spartan6</arg> models. If an update is found, install it and run IBISWriter again.
(2) There are no IBIS models available for use at this time. If this error persists after XilinxUpdate has already been run, IBISWriter does not currently support this I/O Standard for this device.
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/map.xmsgs 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N450</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">51</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N452,
VmeAm_ib6&lt;2&gt;_IBUF,
VmeAm_ib6&lt;1&gt;_IBUF,
VmeDs_inb2&lt;2&gt;_IBUF,
VmeDs_inb2&lt;1&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">PllFmc12SFpga_ik</arg> connected to top level port <arg fmt="%s" index="2">PllFmc12SFpga_ik</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">PllFmc12SFpga_ikn</arg> connected to top level port <arg fmt="%s" index="2">PllFmc12SFpga_ikn</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">PllFmc22SFpga_ik</arg> connected to top level port <arg fmt="%s" index="2">PllFmc22SFpga_ik</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">PllFmc22SFpga_ikn</arg> connected to top level port <arg fmt="%s" index="2">PllFmc22SFpga_ikn</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">PllSys2SFpga_ik</arg> connected to top level port <arg fmt="%s" index="2">PllSys2SFpga_ik</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">PllSys2SFpga_ikn</arg> connected to top level port <arg fmt="%s" index="2">PllSys2SFpga_ikn</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">PllDds2SFpga_ik</arg> connected to top level port <arg fmt="%s" index="2">PllDds2SFpga_ik</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">PllDds2SFpga_ikn</arg> connected to top level port <arg fmt="%s" index="2">PllDds2SFpga_ikn</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdsSyncOut_ik</arg> connected to top level port <arg fmt="%s" index="2">DdsSyncOut_ik</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdsSyncOut_ikn</arg> connected to top level port <arg fmt="%s" index="2">DdsSyncOut_ikn</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;15&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;15&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;14&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;14&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;13&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;13&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;12&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;12&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;11&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;11&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;10&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;10&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;9&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;9&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;8&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;8&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;7&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;7&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;6&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;6&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;5&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;5&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;4&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;4&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;3&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;3&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;2&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;2&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;1&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;1&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdrDQ_iob16&lt;0&gt;</arg> connected to top level port <arg fmt="%s" index="2">DdrDQ_iob16&lt;0&gt;</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Si57xSDa_io</arg> connected to top level port <arg fmt="%s" index="2">Si57xSDa_io</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">AFpgaProgDone_io</arg> connected to top level port <arg fmt="%s" index="2">AFpgaProgDone_io</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">DdsIOUpdate_io</arg> connected to top level port <arg fmt="%s" index="2">DdsIOUpdate_io</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">WRModeDef2_io</arg> connected to top level port <arg fmt="%s" index="2">WRModeDef2_io</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Sfp2ModeDef2_io</arg> connected to top level port <arg fmt="%s" index="2">Sfp2ModeDef2_io</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Fmc1SDa_io</arg> connected to top level port <arg fmt="%s" index="2">Fmc1SDa_io</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Fmc2SDa_io</arg> connected to top level port <arg fmt="%s" index="2">Fmc2SDa_io</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">AFpgaProgProgram_o</arg> connected to top level port <arg fmt="%s" index="2">AFpgaProgProgram_o</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">VAdjInhibit_ozn</arg> connected to top level port <arg fmt="%s" index="2">VAdjInhibit_ozn</arg> has been removed.
</msg>
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">330</arg> IOs, <arg fmt="%d" index="2">328</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg>
<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
</msg>
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;4&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;5&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;7&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsSyncClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRModeDef0_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeTrst_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsSDo_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PllDacDout_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeP0LvdsTClkIn_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPllLock_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Sfp2ModeDef0_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Sfp2LoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRTxFault_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeAm_ib6&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Sfp2TxFault_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeP0LvdsBunchClkIn_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">TempIdDQ_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsDrOver_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRLoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsSyncSmpErr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeTdi_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeTck_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Fmc1PrsntM2C_in_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VmeTms_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">Fmc2PrsntM2C_in_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/ngdbuild.xmsgs 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N450</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N452</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;1&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;0&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;6&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;3&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;2&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;1&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;0&gt;</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgClk_io</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgCsi_io</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgRdWr_io</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgInit_io</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">TempIdDQ_io</arg>&apos; has no legal driver
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/par.xmsgs 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeDs_inb2&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeDs_inb2&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PcbRev_ib8&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PcbRev_ib8&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PcbRev_ib8&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PcbRev_ib8&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PcbRev_ib8&lt;4&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PcbRev_ib8&lt;5&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PcbRev_ib8&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PcbRev_ib8&lt;7&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsSyncClk_ik_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">WRModeDef0_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeTrst_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsSDo_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PllDacDout_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeP0LvdsTClkIn_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsPllLock_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">Sfp2ModeDef0_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">Sfp2LoS_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">WRTxFault_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeAm_ib6&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeAm_ib6&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">Sfp2TxFault_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeP0LvdsBunchClkIn_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">TempIdDQ_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsDrOver_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">WRLoS_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsSyncSmpErr_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeTdi_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeTck_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">Fmc1PrsntM2C_in_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VmeTms_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">Fmc2PrsntM2C_in_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">47</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">47</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg>
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/trce.xmsgs 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/xst.xmsgs 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="572" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Debouncer.v" Line 14: Macro &lt;<arg fmt="%s" index="1">dly</arg>&gt; is redefined.
</msg>
<msg type="warning" file="HDLCompiler" num="572" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/Debouncer.v" Line 21: Macro &lt;<arg fmt="%s" index="1">s_Idle</arg>&gt; is redefined.
</msg>
<msg type="warning" file="HDLCompiler" num="572" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 250: Macro &lt;<arg fmt="%s" index="1">dly</arg>&gt; is redefined.
</msg>
<msg type="warning" file="HDLCompiler" num="1016" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 485: Port <arg fmt="%s" index="1">osc_clk</arg> is not connected to this instance
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 325: Assignment to <arg fmt="%s" index="1">DdrLDQS_io</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 326: Assignment to <arg fmt="%s" index="1">DdrUDQS_io</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 546: Assignment to <arg fmt="%s" index="1">GenericOutputReg3</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 268: Net &lt;<arg fmt="%s" index="1">GenericInputReg1[31]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/SystemFpga.v" Line 273: Net &lt;<arg fmt="%s" index="1">SpiMiSo_b32[30]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="189" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">VmeDs_inb2</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 439: Assignment to <arg fmt="%s" index="1">WRGBitOut_o</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 442: Assignment to <arg fmt="%s" index="1">Sfp2GBitOut_o</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 444: Assignment to <arg fmt="%s" index="1">SataTx_o</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 446: Assignment to <arg fmt="%s" index="1">Gbit1Sys2App_o</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 448: Assignment to <arg fmt="%s" index="1">Gbit2Sys2App_o</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 451: Assignment to <arg fmt="%s" index="1">Gbit3Sys2App_o</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 453: Assignment to <arg fmt="%s" index="1">Gbit4Sys2App_o</arg> ignored, since the identifier is never used
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 253: Net &lt;<arg fmt="%s" index="1">VmeDs_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 440: Net &lt;<arg fmt="%s" index="1">WRGbitIn_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 441: Net &lt;<arg fmt="%s" index="1">WRRefClk_ik</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 443: Net &lt;<arg fmt="%s" index="1">Sfp2GbitIn_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 445: Net &lt;<arg fmt="%s" index="1">SataRx_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 447: Net &lt;<arg fmt="%s" index="1">Gbit1App2Sys_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 449: Net &lt;<arg fmt="%s" index="1">Gbit2App2Sys_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 450: Net &lt;<arg fmt="%s" index="1">Gbit12RefClk_ik</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 452: Net &lt;<arg fmt="%s" index="1">Gbit3App2Sys_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 454: Net &lt;<arg fmt="%s" index="1">Gbit4App2Sys_i</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"\VFC_SVN\firmware\XilinxISE\SystemFpga\../../../hdl/design/XilinxWrappers/SFpga.v" Line 455: Net &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeDs_inb2&lt;2:1&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">WRGBitOut_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">Sfp2GBitOut_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">SataTx_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">Gbit1Sys2App_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">Gbit2Sys2App_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">Gbit3Sys2App_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/xilinxwrappers/sfpga.v</arg>&quot; line <arg fmt="%d" index="2">233</arg>: Output port &lt;<arg fmt="%s" index="3">Gbit4Sys2App_o</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Core</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">VmeDs_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">WRGbitIn_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">WRRefClk_ik</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Sfp2GbitIn_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SataRx_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit1App2Sys_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit2App2Sys_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit12RefClk_ik</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit3App2Sys_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit4App2Sys_i</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">PcbRev_ib8&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTck_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTrst_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTdi_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTms_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">PllFmc12SFpga_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">PllFmc22SFpga_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">PllSys2SFpga_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">PllDds2SFpga_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">PllDacDout_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdsSyncSmpErr_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdsPllLock_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdsSDo_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdsDrOver_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdsSyncClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdsPdClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdsSyncOut_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeP0LvdsBunchClkIn_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeP0LvdsTClkIn_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdrLDQS_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DdrUDQS_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WRModeDef0_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WRTxFault_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WRLoS_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Sfp2ModeDef0_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Sfp2LoS_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Sfp2TxFault_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Fmc1PrsntM2C_in</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Fmc2PrsntM2C_in</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WRGbitIn_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WRRefClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Sfp2GbitIn_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">SataRx_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit1App2Sys_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit2App2Sys_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit12RefClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit3App2Sys_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit4App2Sys_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">485</arg>: Output port &lt;<arg fmt="%s" index="3">osc_clk</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_InterruptManager</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">533</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Generic4OutputRegs</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">GenericInputReg1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">GenericInputReg2</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">GenericInputReg3</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SpiMiSo_b32&lt;30:9&gt;</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">WRGBitOut_o</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Sfp2GBitOut_o</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SataTx_o</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit1Sys2App_o</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit2Sys2App_o</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit3Sys2App_o</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">Gbit4Sys2App_o</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Dat_ib32&lt;30:11&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Adr_ib22&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">AckGenericInputRegs_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Rst_irq</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">i_VmeInterface</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">ds2_shr_0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">i_VmeInterface</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_1</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">i_VmeInterface</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">ds2_shr_1</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">i_VmeInterface</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="3031" delta="old" >HDL ADVISOR - The RAM &lt;<arg fmt="%s" index="1">Mram_int_fifo</arg>&gt; will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
</msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">VmeInterfaceWB</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;ds2_shr_0&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">VmeInterfaceWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">ds1_shr_1</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">VmeInterfaceWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">ds2_shr_1</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">VmeInterfaceWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">CntrlShReg_b32_31</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">Slv2SerWB</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport 0 → 100644
View file @ 23b1b4b5
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2010-12-15T15:18:57</DateModified>
<ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/VFC_SVN/firmware/XilinxISE/SystemFpga</ImplementationReportsDirectory>
<DateInitialized>2010-12-15T15:02:31</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="SFpga_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="SFpga_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SFpga_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SFpga_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SFpga_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SFpga.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SFpga_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SFpga_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SFpga.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SFpga_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SFpga_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="SFpga.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SFpga.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SFpga.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SFpga.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="SFpga.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SFpga_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SFpga.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SFpga.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SFpga.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SFpga.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SFpga.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SFpga.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SFpga_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SFpga_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SFpga_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SFpga_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SFpga_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SFpga_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SFpga.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SFpga_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SFpga_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SFpga_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SFpga.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SFpga.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SFpga_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SystemFpga.projectmgr 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="utf-8"?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="SystemFpga" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/ApplicationFpga C:|VFC_SVN|hdl|design|ApplicationFpga.v</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>SFpga (C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000191000000020000000000000000000000000000000064ffffffff000000810000000000000002000001910000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>SFpga (C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Design Utilities</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a2000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Design Utilities</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000000d60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>AddrDecoderWBSys.v</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000010001000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Analyze Post-Place &amp; Route Static Timing</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >11</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000191000000010000000100000000000000000000000064ffffffff000000810000000000000001000001910000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Analyze Post-Place &amp; Route Static Timing</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a2000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
</Project>
trunk/firmware/XilinxISE/SystemFpga/pa.fromHdl.tcl 0 → 100644
View file @ 23b1b4b5
# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator
create_project -name SystemFpga -dir "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1" -part xc6slx150tfgg676-3
set_param project.pinAheadLayout yes
set srcset [get_property srcset [current_run -impl]]
set_property top SFpga $srcset
set_param project.paUcfFile "SFpga.ucf"
set hdlfile [add_files [list {../../../hdl/design/VmeInterfaceWB.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/SpiMasterWB.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/Slv2SerWB.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/Monostable.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/InterruptManagerWB.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/Generic4OutputRegs.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/Generic4InputRegs.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/Debouncer.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/AddrDecoderWBSys.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/SystemFpga.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../../../hdl/design/XilinxWrappers/SFpga.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files "SFpga.ucf" -fileset [get_property constrset [current_run]]
add_files -norecurse { {C:/VFC_SVN/firmware/XilinxISE/SystemFpga} }
open_rtl_design -part xc6slx150tfgg676-3
trunk/firmware/XilinxISE/SystemFpga/pa.fromNetlist.tcl 0 → 100644
View file @ 23b1b4b5
# PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator
create_project -name SystemFpga -dir "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1" -part xc6slx150tfgg676-3
set_property design_mode GateLvl [get_property srcset [current_run -impl]]
set_property edif_top_file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" [ get_property srcset [ current_run ] ]
add_files -norecurse { {C:/VFC_SVN/firmware/XilinxISE/SystemFpga} }
set_param project.pinAheadLayout yes
set_param project.paUcfFile "SFpga.ucf"
add_files "SFpga.ucf" -fileset [get_property constrset [current_run]]
open_netlist_design
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html 0 → 100644
View file @ 23b1b4b5
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1486</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4726</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4726</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4167</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>25.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>32.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>44.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>55.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>62.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>15.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>8.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.1119</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
trunk/firmware/XilinxISE/SystemFpga/planAhead.ngc2edif.log 0 → 100644
View file @ 23b1b4b5
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
trunk/firmware/XilinxISE/SystemFpga/planAhead_pid5076.debug 0 → 100644
View file @ 23b1b4b5
#-------------------------------------------------------------------------------
# PlanAhead v12.3
# Build 101344 by hdbuild on Sat Sep 4 00:26:34 MDT 2010
# Current time: 12/16/10 11:38:56 AM
# Process ID: 5076
# Platform: Windows
#
# This file is an indication that an internal PlanAhead error occurred.
# This information is useful for debugging. Please open a case with Xilinx
# Technical Support with this file and a testcase attached.
#-------------------------------------------------------------------------------
12/16/10 11:38:56 AM
java.lang.ArrayIndexOutOfBoundsException: 7
at sun.font.FontDesignMetrics.charsWidth(FontDesignMetrics.java:492)
at javax.swing.text.Utilities.getTabbedTextOffset(Utilities.java:381)
at javax.swing.text.Utilities.getTabbedTextOffset(Utilities.java:302)
at javax.swing.text.Utilities.getTabbedTextOffset(Utilities.java:286)
at javax.swing.text.PlainView.viewToModel(PlainView.java:403)
at javax.swing.text.FieldView.viewToModel(FieldView.java:263)
at javax.swing.plaf.basic.BasicTextUI$RootView.viewToModel(BasicTextUI.java:1540)
at javax.swing.plaf.basic.BasicTextUI.viewToModel(BasicTextUI.java:1089)
at javax.swing.text.DefaultCaret.positionCaret(DefaultCaret.java:292)
at javax.swing.text.DefaultCaret.adjustCaret(DefaultCaret.java:497)
at javax.swing.text.DefaultCaret.adjustCaretAndFocus(DefaultCaret.java:485)
at javax.swing.text.DefaultCaret.mousePressed(DefaultCaret.java:475)
at java.awt.AWTEventMulticaster.mousePressed(AWTEventMulticaster.java:263)
at java.awt.Component.processMouseEvent(Component.java:6260)
at javax.swing.JComponent.processMouseEvent(JComponent.java:3267)
at java.awt.Component.processEvent(Component.java:6028)
at java.awt.Container.processEvent(Container.java:2041)
at java.awt.Component.dispatchEventImpl(Component.java:4630)
at java.awt.Container.dispatchEventImpl(Container.java:2099)
at java.awt.Component.dispatchEvent(Component.java:4460)
at java.awt.LightweightDispatcher.retargetMouseEvent(Container.java:4574)
at java.awt.LightweightDispatcher.processMouseEvent(Container.java:4235)
at java.awt.LightweightDispatcher.dispatchEvent(Container.java:4168)
at java.awt.Container.dispatchEventImpl(Container.java:2085)
at java.awt.Window.dispatchEventImpl(Window.java:2475)
at java.awt.Component.dispatchEvent(Component.java:4460)
at java.awt.EventQueue.dispatchEvent(EventQueue.java:599)
at ui.frmwork.Y.dispatchEvent(SourceFile:73)
at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:269)
at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:184)
at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:174)
at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:169)
at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:161)
at java.awt.EventDispatchThread.run(EventDispatchThread.java:122)
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/constrs_1/designprops.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<Compat Version="1" Minor="3">
<CompatParts>
</CompatParts>
<ConfigModes>
<Mode Id="JTAG"/>
</ConfigModes>
<PortProps>
<Port Name="ManualAddress_ib5[4]" OffChipTerm="NONE"/>
<Port Name="ManualAddress_ib5[3]" OffChipTerm="NONE"/>
<Port Name="ManualAddress_ib5[2]" OffChipTerm="NONE"/>
<Port Name="ManualAddress_ib5[1]" OffChipTerm="NONE"/>
<Port Name="ManualAddress_ib5[0]" OffChipTerm="NONE"/>
<Port Name="VmeGa_ib5n[4]" OffChipTerm="NONE"/>
<Port Name="VmeGa_ib5n[3]" OffChipTerm="NONE"/>
<Port Name="VmeGa_ib5n[2]" OffChipTerm="NONE"/>
<Port Name="VmeGa_ib5n[1]" OffChipTerm="NONE"/>
<Port Name="VmeGa_ib5n[0]" OffChipTerm="NONE"/>
<Port Name="VmeA_iob31[31]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[30]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[29]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[28]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[27]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[26]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[25]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[24]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[23]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[22]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[21]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[20]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[19]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[18]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[17]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[16]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[15]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[14]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[13]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[12]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[11]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[10]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[9]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[8]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[7]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[6]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[5]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[4]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[3]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[2]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeA_iob31[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeAm_ib6[5]" OffChipTerm="NONE"/>
<Port Name="VmeAm_ib6[4]" OffChipTerm="NONE"/>
<Port Name="VmeAm_ib6[3]" OffChipTerm="NONE"/>
<Port Name="VmeAm_ib6[2]" OffChipTerm="NONE"/>
<Port Name="VmeAm_ib6[1]" OffChipTerm="NONE"/>
<Port Name="VmeAm_ib6[0]" OffChipTerm="NONE"/>
<Port Name="VmeDs_inb2[2]" OffChipTerm="NONE"/>
<Port Name="VmeDs_inb2[1]" OffChipTerm="NONE"/>
<Port Name="Switch_ib2[1]" OffChipTerm="NONE"/>
<Port Name="Switch_ib2[0]" OffChipTerm="NONE"/>
<Port Name="PcbRev_ib8[7]" OffChipTerm="NONE"/>
<Port Name="PcbRev_ib8[6]" OffChipTerm="NONE"/>
<Port Name="PcbRev_ib8[5]" OffChipTerm="NONE"/>
<Port Name="PcbRev_ib8[4]" OffChipTerm="NONE"/>
<Port Name="PcbRev_ib8[3]" OffChipTerm="NONE"/>
<Port Name="PcbRev_ib8[2]" OffChipTerm="NONE"/>
<Port Name="PcbRev_ib8[1]" OffChipTerm="NONE"/>
<Port Name="PcbRev_ib8[0]" OffChipTerm="NONE"/>
<Port Name="AFpgaProgD_iob8[7]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgD_iob8[6]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgD_iob8[5]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgD_iob8[4]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgD_iob8[3]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgD_iob8[2]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgD_iob8[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgD_iob8[0]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeIrq_ob7[7]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeIrq_ob7[6]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeIrq_ob7[5]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeIrq_ob7[4]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeIrq_ob7[3]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeIrq_ob7[2]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeIrq_ob7[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[31]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[30]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[29]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[28]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[27]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[26]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[25]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[24]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[23]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[22]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[21]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[20]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[19]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[18]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[17]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[16]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[15]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[14]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[13]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[12]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[11]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[10]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[9]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[8]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[7]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[6]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[5]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[4]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[3]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[2]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeD_iob32[0]" OffChipTerm="FP_VTT_50"/>
<Port Name="FpLed_onb8[7]" OffChipTerm="FP_VTT_50"/>
<Port Name="FpLed_onb8[6]" OffChipTerm="FP_VTT_50"/>
<Port Name="FpLed_onb8[5]" OffChipTerm="FP_VTT_50"/>
<Port Name="FpLed_onb8[4]" OffChipTerm="FP_VTT_50"/>
<Port Name="FpLed_onb8[3]" OffChipTerm="FP_VTT_50"/>
<Port Name="FpLed_onb8[2]" OffChipTerm="FP_VTT_50"/>
<Port Name="FpLed_onb8[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="FpLed_onb8[0]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgM_iob2[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgM_iob2[0]" OffChipTerm="FP_VTT_50"/>
<Port Name="SysAppSlow_iob2[2]" OffChipTerm="FP_VTT_50"/>
<Port Name="SysAppSlow_iob2[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsF_ob2[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsF_ob2[0]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsProfile_ob3[2]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsProfile_ob3[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsProfile_ob3[0]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[15]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[14]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[13]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[12]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[11]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[10]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[9]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[8]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[7]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[6]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[5]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[4]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[3]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[2]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[1]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsD_ob16[0]" OffChipTerm="FP_VTT_50"/>
<Port Name="DdrA_ob14[13]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[12]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[11]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[10]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[9]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[8]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[7]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[6]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[5]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[4]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[3]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[2]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[1]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrA_ob14[0]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrBA_ob3[2]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrBA_ob3[1]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrBA_ob3[0]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[15]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[14]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[13]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[12]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[11]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[10]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[9]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[8]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[7]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[6]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[5]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[4]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[3]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[2]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[1]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrDQ_iob16[0]" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="UseGa_i" OffChipTerm="NONE"/>
<Port Name="VmeGaP_in" OffChipTerm="NONE"/>
<Port Name="VmeLword_io" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeAs_in" OffChipTerm="NONE"/>
<Port Name="VmeSysClk_ik" OffChipTerm="NONE"/>
<Port Name="VmeWrite_in" OffChipTerm="NONE"/>
<Port Name="VmeIack_in" OffChipTerm="NONE"/>
<Port Name="VmeIackIn_in" OffChipTerm="NONE"/>
<Port Name="VmeSysReset_in" OffChipTerm="NONE"/>
<Port Name="VmeTck_i" OffChipTerm="NONE"/>
<Port Name="VmeTrst_i" OffChipTerm="NONE"/>
<Port Name="VmeTdi_i" OffChipTerm="NONE"/>
<Port Name="VmeTms_i" OffChipTerm="NONE"/>
<Port Name="VcTcXo_ik" OffChipTerm="NONE"/>
<Port Name="Si57x_ik" OffChipTerm="NONE"/>
<Port Name="Si57x_ikn" OffChipTerm="NONE"/>
<Port Name="PushButton_ion" OffChipTerm="FP_VTT_50"/>
<Port Name="SysAppClk_ik" OffChipTerm="NONE"/>
<Port Name="FlashSFpgaQ_i" OffChipTerm="NONE"/>
<Port Name="FlashAFpgaQ_i" OffChipTerm="NONE"/>
<Port Name="VAdcDout_i" OffChipTerm="NONE"/>
<Port Name="PllFmc1Ld_i" OffChipTerm="NONE"/>
<Port Name="PllFmc1Status_i" OffChipTerm="NONE"/>
<Port Name="PllFmc1RefMon_i" OffChipTerm="NONE"/>
<Port Name="PllFmc1Sdo_i" OffChipTerm="NONE"/>
<Port Name="PllFmc12SFpga_ik" OffChipTerm="NONE"/>
<Port Name="PllFmc12SFpga_ikn" OffChipTerm="NONE"/>
<Port Name="PllFmc2Ld_i" OffChipTerm="NONE"/>
<Port Name="PllFmc2Status_i" OffChipTerm="NONE"/>
<Port Name="PllFmc2RefMon_i" OffChipTerm="NONE"/>
<Port Name="PllFmc2Sdo_i" OffChipTerm="NONE"/>
<Port Name="PllFmc22SFpga_ik" OffChipTerm="NONE"/>
<Port Name="PllFmc22SFpga_ikn" OffChipTerm="NONE"/>
<Port Name="PllSysLd_i" OffChipTerm="NONE"/>
<Port Name="PllSysStatus_i" OffChipTerm="NONE"/>
<Port Name="PllSysRefMon_i" OffChipTerm="NONE"/>
<Port Name="PllSysSdo_i" OffChipTerm="NONE"/>
<Port Name="PllSys2SFpga_ik" OffChipTerm="NONE"/>
<Port Name="PllSys2SFpga_ikn" OffChipTerm="NONE"/>
<Port Name="PllDdsLd_i" OffChipTerm="NONE"/>
<Port Name="PllDdsStatus_i" OffChipTerm="NONE"/>
<Port Name="PllDdsRefMon_i" OffChipTerm="NONE"/>
<Port Name="PllDdsSdo_i" OffChipTerm="NONE"/>
<Port Name="PllDds2SFpga_ik" OffChipTerm="NONE"/>
<Port Name="PllDds2SFpga_ikn" OffChipTerm="NONE"/>
<Port Name="PllDacDout_i" OffChipTerm="NONE"/>
<Port Name="DdsSyncSmpErr_i" OffChipTerm="NONE"/>
<Port Name="DdsPllLock_i" OffChipTerm="NONE"/>
<Port Name="DdsSDo_i" OffChipTerm="NONE"/>
<Port Name="DdsRamSwpOvr_i" OffChipTerm="NONE"/>
<Port Name="DdsDrOver_i" OffChipTerm="NONE"/>
<Port Name="DdsSyncClk_ik" OffChipTerm="NONE"/>
<Port Name="DdsPdClk_ik" OffChipTerm="NONE"/>
<Port Name="DdsSyncOut_ik" OffChipTerm="NONE"/>
<Port Name="DdsSyncOut_ikn" OffChipTerm="NONE"/>
<Port Name="VmeP0LvdsBunchClkIn_i" OffChipTerm="NONE"/>
<Port Name="VmeP0LvdsTClkIn_i" OffChipTerm="NONE"/>
<Port Name="WRModeDef0_i" OffChipTerm="NONE"/>
<Port Name="WRTxFault_i" OffChipTerm="NONE"/>
<Port Name="WRLoS_i" OffChipTerm="NONE"/>
<Port Name="Sfp2ModeDef0_i" OffChipTerm="NONE"/>
<Port Name="Sfp2LoS_i" OffChipTerm="NONE"/>
<Port Name="Sfp2TxFault_i" OffChipTerm="NONE"/>
<Port Name="Fmc1PrsntM2C_in" OffChipTerm="NONE"/>
<Port Name="Fmc2PrsntM2C_in" OffChipTerm="NONE"/>
<Port Name="VmeDtAckOe_oe" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeDtAck_on" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeDOeN_oen" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeDDirVfcToVme_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeIackOut_on" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeAOeN_oen" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeADirVfcToVme_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeRetryOe_oe" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeRetry_on" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeBerr_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeTdoOe_oe" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeTdo_o" OffChipTerm="FP_VTT_50"/>
<Port Name="Si57xSCl_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="Si57xSDa_io" OffChipTerm="FP_VTT_50"/>
<Port Name="Si57xOe_o" OffChipTerm="FP_VTT_50"/>
<Port Name="FpGpIo1OutputMode_o" OffChipTerm="FP_VTT_50"/>
<Port Name="FpGpIo2OutputMode_o" OffChipTerm="FP_VTT_50"/>
<Port Name="FpGpIo34OutputMode_o" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgDone_io" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgClk_io" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgProgram_o" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgCsi_io" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgRdWr_io" OffChipTerm="FP_VTT_50"/>
<Port Name="AFpgaProgInit_io" OffChipTerm="FP_VTT_50"/>
<Port Name="SysAppClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="FlashSFpgaD_o" OffChipTerm="FP_VTT_50"/>
<Port Name="FlashSFpgaClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="FlashSFpgaCs_on" OffChipTerm="FP_VTT_50"/>
<Port Name="FlashAFpgaD_o" OffChipTerm="FP_VTT_50"/>
<Port Name="FlashAFpgaClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="FlashAFpgaCs_on" OffChipTerm="FP_VTT_50"/>
<Port Name="VAdcSClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="VAdcDin_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VAdcCs_on" OffChipTerm="FP_VTT_50"/>
<Port Name="VAdjCs_on" OffChipTerm="FP_VTT_50"/>
<Port Name="VAdjSClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="VAdjDin_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VAdjInhibit_ozn" OffChipTerm="FP_VTT_50"/>
<Port Name="VAdjSpi_o" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc1RefSel_o" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc1Ref1_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc1Pd_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc1Synch_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc1Reset_orn" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc1SClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc1SDio_io" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc1Cs_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc2RefSel_o" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc2Ref1_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc2Pd_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc2Synch_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc2Reset_orn" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc2SClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc2SDio_io" OffChipTerm="FP_VTT_50"/>
<Port Name="PllFmc2Cs_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllSysRefSel_o" OffChipTerm="FP_VTT_50"/>
<Port Name="PllSysRef12_ok" OffChipTerm="NONE"/>
<Port Name="PllSysRef12_okn" OffChipTerm="NONE"/>
<Port Name="PllSysPd_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllSysSynch_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllSysReset_orn" OffChipTerm="FP_VTT_50"/>
<Port Name="PllSysSClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="PllSysSDio_io" OffChipTerm="FP_VTT_50"/>
<Port Name="PllSysCs_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDdsRefSel_o" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDdsPd_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDdsSynch_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDdsReset_orn" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDdsClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDdsSClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDdsSDio_io" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDdsCs_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDacSClk_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDacSynch_on" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDacDin_o" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDacClrn_orn" OffChipTerm="FP_VTT_50"/>
<Port Name="PllDacLDac_on" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsTxEnable_o" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsMasterRst_or" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsPowerDown_o" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsIOUpdate_io" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsOsk_o" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsDrHold_o" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsSClk_o" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsSDio_io" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsIoReset_or" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsDrCtl_o" OffChipTerm="FP_VTT_50"/>
<Port Name="DdsSyncIn_ok" OffChipTerm="NONE"/>
<Port Name="DdsSyncIn_okn" OffChipTerm="NONE"/>
<Port Name="VmeP0BuslineDir_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0BuslineOe_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0HwLowByteDir_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0HwLowByteOe_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0HwHighByteDir_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0HwHighByteOe_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0BunchSelectDir_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0BunchSelectOe_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0LvdsBunchClkOut_o" OffChipTerm="FP_VTT_50"/>
<Port Name="VmeP0LvdsTClkOut_o" OffChipTerm="FP_VTT_50"/>
<Port Name="TempIdDQ_io" OffChipTerm="FP_VTT_50"/>
<Port Name="DdrReset_or" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrCkE_o" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrWe_o" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrCk_ok" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrCk_okn" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrODT_o" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrRAS_o" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrCAS_o" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrUDM_o" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrLDM_o" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrLDQS_io" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrLDQS_ion" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrUDQS_io" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="DdrUDQS_ion" OffChipTerm="NP_VTT_50_FP_VTT_50"/>
<Port Name="WRModeDef1_i" OffChipTerm="FP_VTT_50"/>
<Port Name="WRModeDef2_io" OffChipTerm="FP_VTT_50"/>
<Port Name="WRRateSelect_o" OffChipTerm="FP_VTT_50"/>
<Port Name="WRTxDisable_o" OffChipTerm="FP_VTT_50"/>
<Port Name="Sfp2ModeDef1_i" OffChipTerm="FP_VTT_50"/>
<Port Name="Sfp2ModeDef2_io" OffChipTerm="FP_VTT_50"/>
<Port Name="Sfp2RateSelect" OffChipTerm="FP_VTT_50"/>
<Port Name="Sfp2TxDisable_o" OffChipTerm="FP_VTT_50"/>
<Port Name="Fmc1PGC2M_in" OffChipTerm="FP_VTT_50"/>
<Port Name="Fmc2PGC2M_in" OffChipTerm="FP_VTT_50"/>
<Port Name="Fmc1SDa_io" OffChipTerm="FP_VTT_50"/>
<Port Name="Fmc1SCl_ok" OffChipTerm="FP_VTT_50"/>
<Port Name="Fmc2SDa_io" OffChipTerm="FP_VTT_50"/>
<Port Name="Fmc2SCl_ok" OffChipTerm="FP_VTT_50"/>
</PortProps>
</Compat>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/constrs_1/fileset.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<DARoots Version="1" Minor="7">
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ucf">
</File>
<File Path="$PDATADIR/constrs_1/designprops.xml">
<FileInfo SFType="CompatPartsDb"/>
</File>
<File Path="$PDATADIR/constrs_1/usercols.xml">
<FileInfo SFType="UserColsDb"/>
</File>
<Config>
<Option Name="TargetPart" Val="xc6slx150tfgg676-3"/>
</Config>
</FileSet>
</DARoots>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/constrs_1/usercols.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<UserColInfo Version="1" Minor="0">
</UserColInfo>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/runs/impl_1.psg 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="ISE Defaults" Flow="ISE12">
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
</StratHandle>
<Step Id="ngdbuild">
</Step>
<Step Id="map">
<Option Id="FFPackEnum">3</Option>
</Step>
<Step Id="par">
</Step>
<Step Id="trce">
</Step>
<Step Id="xdl">
</Step>
</Strategy>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/runs/runs.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<Runs Version="1" Minor="4">
<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx150tfgg676-3" ConstrsSet="constrs_1" State="current"/>
</Runs>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/sources_1/chipscope.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<ChipScope Version="1" Minor="2">
<UnassignedNets>
</UnassignedNets>
</ChipScope>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/sources_1/fileset.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<DARoots Version="1" Minor="7">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="EDIFSrcs"/>
<File Path="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc">
<FileInfo RelPath="SFpga.ngc"/>
</File>
<File Path="$PDATADIR/sources_1/ports.xml">
<FileInfo SFType="PortsDb"/>
</File>
<File Path="$PDATADIR/sources_1/chipscope.xml">
<FileInfo SFType="ChipscopeDb"/>
</File>
<Config>
<Option Name="DesignMode" Val="GateLvl"/>
<Option Name="GateLvlMode" Val="EDIF"/>
<Option Name="TopFile" Val="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc"/>
</Config>
</FileSet>
</DARoots>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/sources_1/ports.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<Interface Version="1" Minor="1">
<Ifc Id="ROOT" Top="1">
<Bus Id="ManualAddress_ib5">
<Port Id="4" Dir="IN"/>
<Port Id="3" Dir="IN"/>
<Port Id="2" Dir="IN"/>
<Port Id="1" Dir="IN"/>
<Port Id="0" Dir="IN"/>
</Bus>
<Bus Id="VmeGa_ib5n">
<Port Id="4" Dir="IN"/>
<Port Id="3" Dir="IN"/>
<Port Id="2" Dir="IN"/>
<Port Id="1" Dir="IN"/>
<Port Id="0" Dir="IN"/>
</Bus>
<Bus Id="VmeA_iob31">
<Port Id="31" Dir="INOUT"/>
<Port Id="30" Dir="INOUT"/>
<Port Id="29" Dir="INOUT"/>
<Port Id="28" Dir="INOUT"/>
<Port Id="27" Dir="INOUT"/>
<Port Id="26" Dir="INOUT"/>
<Port Id="25" Dir="INOUT"/>
<Port Id="24" Dir="INOUT"/>
<Port Id="23" Dir="INOUT"/>
<Port Id="22" Dir="INOUT"/>
<Port Id="21" Dir="INOUT"/>
<Port Id="20" Dir="INOUT"/>
<Port Id="19" Dir="INOUT"/>
<Port Id="18" Dir="INOUT"/>
<Port Id="17" Dir="INOUT"/>
<Port Id="16" Dir="INOUT"/>
<Port Id="15" Dir="INOUT"/>
<Port Id="14" Dir="INOUT"/>
<Port Id="13" Dir="INOUT"/>
<Port Id="12" Dir="INOUT"/>
<Port Id="11" Dir="INOUT"/>
<Port Id="10" Dir="INOUT"/>
<Port Id="9" Dir="INOUT"/>
<Port Id="8" Dir="INOUT"/>
<Port Id="7" Dir="INOUT"/>
<Port Id="6" Dir="INOUT"/>
<Port Id="5" Dir="INOUT"/>
<Port Id="4" Dir="INOUT"/>
<Port Id="3" Dir="INOUT"/>
<Port Id="2" Dir="INOUT"/>
<Port Id="1" Dir="INOUT"/>
</Bus>
<Bus Id="VmeAm_ib6">
<Port Id="5" Dir="IN"/>
<Port Id="4" Dir="IN"/>
<Port Id="3" Dir="IN"/>
<Port Id="2" Dir="IN"/>
<Port Id="1" Dir="IN"/>
<Port Id="0" Dir="IN"/>
</Bus>
<Bus Id="VmeDs_inb2">
<Port Id="2" Dir="IN"/>
<Port Id="1" Dir="IN"/>
</Bus>
<Bus Id="Switch_ib2">
<Port Id="1" Dir="IN"/>
<Port Id="0" Dir="IN"/>
</Bus>
<Bus Id="PcbRev_ib8">
<Port Id="7" Dir="IN"/>
<Port Id="6" Dir="IN"/>
<Port Id="5" Dir="IN"/>
<Port Id="4" Dir="IN"/>
<Port Id="3" Dir="IN"/>
<Port Id="2" Dir="IN"/>
<Port Id="1" Dir="IN"/>
<Port Id="0" Dir="IN"/>
</Bus>
<Bus Id="AFpgaProgD_iob8">
<Port Id="7" Dir="INOUT"/>
<Port Id="6" Dir="INOUT"/>
<Port Id="5" Dir="INOUT"/>
<Port Id="4" Dir="INOUT"/>
<Port Id="3" Dir="INOUT"/>
<Port Id="2" Dir="INOUT"/>
<Port Id="1" Dir="INOUT"/>
<Port Id="0" Dir="INOUT"/>
</Bus>
<Bus Id="VmeIrq_ob7">
<Port Id="7" Dir="OUT"/>
<Port Id="6" Dir="OUT"/>
<Port Id="5" Dir="OUT"/>
<Port Id="4" Dir="OUT"/>
<Port Id="3" Dir="OUT"/>
<Port Id="2" Dir="OUT"/>
<Port Id="1" Dir="OUT"/>
</Bus>
<Bus Id="VmeD_iob32">
<Port Id="31" Dir="INOUT"/>
<Port Id="30" Dir="INOUT"/>
<Port Id="29" Dir="INOUT"/>
<Port Id="28" Dir="INOUT"/>
<Port Id="27" Dir="INOUT"/>
<Port Id="26" Dir="INOUT"/>
<Port Id="25" Dir="INOUT"/>
<Port Id="24" Dir="INOUT"/>
<Port Id="23" Dir="INOUT"/>
<Port Id="22" Dir="INOUT"/>
<Port Id="21" Dir="INOUT"/>
<Port Id="20" Dir="INOUT"/>
<Port Id="19" Dir="INOUT"/>
<Port Id="18" Dir="INOUT"/>
<Port Id="17" Dir="INOUT"/>
<Port Id="16" Dir="INOUT"/>
<Port Id="15" Dir="INOUT"/>
<Port Id="14" Dir="INOUT"/>
<Port Id="13" Dir="INOUT"/>
<Port Id="12" Dir="INOUT"/>
<Port Id="11" Dir="INOUT"/>
<Port Id="10" Dir="INOUT"/>
<Port Id="9" Dir="INOUT"/>
<Port Id="8" Dir="INOUT"/>
<Port Id="7" Dir="INOUT"/>
<Port Id="6" Dir="INOUT"/>
<Port Id="5" Dir="INOUT"/>
<Port Id="4" Dir="INOUT"/>
<Port Id="3" Dir="INOUT"/>
<Port Id="2" Dir="INOUT"/>
<Port Id="1" Dir="INOUT"/>
<Port Id="0" Dir="INOUT"/>
</Bus>
<Bus Id="FpLed_onb8">
<Port Id="7" Dir="OUT"/>
<Port Id="6" Dir="OUT"/>
<Port Id="5" Dir="OUT"/>
<Port Id="4" Dir="OUT"/>
<Port Id="3" Dir="OUT"/>
<Port Id="2" Dir="OUT"/>
<Port Id="1" Dir="OUT"/>
<Port Id="0" Dir="OUT"/>
</Bus>
<Bus Id="AFpgaProgM_iob2">
<Port Id="1" Dir="INOUT"/>
<Port Id="0" Dir="INOUT"/>
</Bus>
<Bus Id="SysAppSlow_iob2">
<Port Id="2" Dir="INOUT"/>
<Port Id="1" Dir="INOUT"/>
</Bus>
<Bus Id="DdsF_ob2">
<Port Id="1" Dir="OUT"/>
<Port Id="0" Dir="OUT"/>
</Bus>
<Bus Id="DdsProfile_ob3">
<Port Id="2" Dir="OUT"/>
<Port Id="1" Dir="OUT"/>
<Port Id="0" Dir="OUT"/>
</Bus>
<Bus Id="DdsD_ob16">
<Port Id="15" Dir="OUT"/>
<Port Id="14" Dir="OUT"/>
<Port Id="13" Dir="OUT"/>
<Port Id="12" Dir="OUT"/>
<Port Id="11" Dir="OUT"/>
<Port Id="10" Dir="OUT"/>
<Port Id="9" Dir="OUT"/>
<Port Id="8" Dir="OUT"/>
<Port Id="7" Dir="OUT"/>
<Port Id="6" Dir="OUT"/>
<Port Id="5" Dir="OUT"/>
<Port Id="4" Dir="OUT"/>
<Port Id="3" Dir="OUT"/>
<Port Id="2" Dir="OUT"/>
<Port Id="1" Dir="OUT"/>
<Port Id="0" Dir="OUT"/>
</Bus>
<Bus Id="DdrA_ob14">
<Port Id="13" Dir="OUT"/>
<Port Id="12" Dir="OUT"/>
<Port Id="11" Dir="OUT"/>
<Port Id="10" Dir="OUT"/>
<Port Id="9" Dir="OUT"/>
<Port Id="8" Dir="OUT"/>
<Port Id="7" Dir="OUT"/>
<Port Id="6" Dir="OUT"/>
<Port Id="5" Dir="OUT"/>
<Port Id="4" Dir="OUT"/>
<Port Id="3" Dir="OUT"/>
<Port Id="2" Dir="OUT"/>
<Port Id="1" Dir="OUT"/>
<Port Id="0" Dir="OUT"/>
</Bus>
<Bus Id="DdrBA_ob3">
<Port Id="2" Dir="OUT"/>
<Port Id="1" Dir="OUT"/>
<Port Id="0" Dir="OUT"/>
</Bus>
<Bus Id="DdrDQ_iob16">
<Port Id="15" Dir="INOUT"/>
<Port Id="14" Dir="INOUT"/>
<Port Id="13" Dir="INOUT"/>
<Port Id="12" Dir="INOUT"/>
<Port Id="11" Dir="INOUT"/>
<Port Id="10" Dir="INOUT"/>
<Port Id="9" Dir="INOUT"/>
<Port Id="8" Dir="INOUT"/>
<Port Id="7" Dir="INOUT"/>
<Port Id="6" Dir="INOUT"/>
<Port Id="5" Dir="INOUT"/>
<Port Id="4" Dir="INOUT"/>
<Port Id="3" Dir="INOUT"/>
<Port Id="2" Dir="INOUT"/>
<Port Id="1" Dir="INOUT"/>
<Port Id="0" Dir="INOUT"/>
</Bus>
<Port Id="UseGa_i" Dir="IN"/>
<Port Id="VmeGaP_in" Dir="IN"/>
<Port Id="VmeLword_io" Dir="INOUT"/>
<Port Id="VmeAs_in" Dir="IN"/>
<Port Id="VmeSysClk_ik" Dir="IN"/>
<Port Id="VmeWrite_in" Dir="IN"/>
<Port Id="VmeIack_in" Dir="IN"/>
<Port Id="VmeIackIn_in" Dir="IN"/>
<Port Id="VmeSysReset_in" Dir="IN"/>
<Port Id="VmeTck_i" Dir="IN"/>
<Port Id="VmeTrst_i" Dir="IN"/>
<Port Id="VmeTdi_i" Dir="IN"/>
<Port Id="VmeTms_i" Dir="IN"/>
<Port Id="VcTcXo_ik" Dir="IN"/>
<Port Id="Si57x_ik" Dir="IN"/>
<Port Id="Si57x_ikn" Dir="IN"/>
<Port Id="PushButton_ion" Dir="INOUT"/>
<Port Id="SysAppClk_ik" Dir="IN"/>
<Port Id="FlashSFpgaQ_i" Dir="IN"/>
<Port Id="FlashAFpgaQ_i" Dir="IN"/>
<Port Id="VAdcDout_i" Dir="IN"/>
<Port Id="PllFmc1Ld_i" Dir="IN"/>
<Port Id="PllFmc1Status_i" Dir="IN"/>
<Port Id="PllFmc1RefMon_i" Dir="IN"/>
<Port Id="PllFmc1Sdo_i" Dir="IN"/>
<Port Id="PllFmc12SFpga_ik" Dir="IN"/>
<Port Id="PllFmc12SFpga_ikn" Dir="IN"/>
<Port Id="PllFmc2Ld_i" Dir="IN"/>
<Port Id="PllFmc2Status_i" Dir="IN"/>
<Port Id="PllFmc2RefMon_i" Dir="IN"/>
<Port Id="PllFmc2Sdo_i" Dir="IN"/>
<Port Id="PllFmc22SFpga_ik" Dir="IN"/>
<Port Id="PllFmc22SFpga_ikn" Dir="IN"/>
<Port Id="PllSysLd_i" Dir="IN"/>
<Port Id="PllSysStatus_i" Dir="IN"/>
<Port Id="PllSysRefMon_i" Dir="IN"/>
<Port Id="PllSysSdo_i" Dir="IN"/>
<Port Id="PllSys2SFpga_ik" Dir="IN"/>
<Port Id="PllSys2SFpga_ikn" Dir="IN"/>
<Port Id="PllDdsLd_i" Dir="IN"/>
<Port Id="PllDdsStatus_i" Dir="IN"/>
<Port Id="PllDdsRefMon_i" Dir="IN"/>
<Port Id="PllDdsSdo_i" Dir="IN"/>
<Port Id="PllDds2SFpga_ik" Dir="IN"/>
<Port Id="PllDds2SFpga_ikn" Dir="IN"/>
<Port Id="PllDacDout_i" Dir="IN"/>
<Port Id="DdsSyncSmpErr_i" Dir="IN"/>
<Port Id="DdsPllLock_i" Dir="IN"/>
<Port Id="DdsSDo_i" Dir="IN"/>
<Port Id="DdsRamSwpOvr_i" Dir="IN"/>
<Port Id="DdsDrOver_i" Dir="IN"/>
<Port Id="DdsSyncClk_ik" Dir="IN"/>
<Port Id="DdsPdClk_ik" Dir="IN"/>
<Port Id="DdsSyncOut_ik" Dir="IN"/>
<Port Id="DdsSyncOut_ikn" Dir="IN"/>
<Port Id="VmeP0LvdsBunchClkIn_i" Dir="IN"/>
<Port Id="VmeP0LvdsTClkIn_i" Dir="IN"/>
<Port Id="WRModeDef0_i" Dir="IN"/>
<Port Id="WRTxFault_i" Dir="IN"/>
<Port Id="WRLoS_i" Dir="IN"/>
<Port Id="Sfp2ModeDef0_i" Dir="IN"/>
<Port Id="Sfp2LoS_i" Dir="IN"/>
<Port Id="Sfp2TxFault_i" Dir="IN"/>
<Port Id="Fmc1PrsntM2C_in" Dir="IN"/>
<Port Id="Fmc2PrsntM2C_in" Dir="IN"/>
<Port Id="VmeDtAckOe_oe" Dir="OUT"/>
<Port Id="VmeDtAck_on" Dir="OUT"/>
<Port Id="VmeDOeN_oen" Dir="OUT"/>
<Port Id="VmeDDirVfcToVme_o" Dir="OUT"/>
<Port Id="VmeIackOut_on" Dir="OUT"/>
<Port Id="VmeAOeN_oen" Dir="OUT"/>
<Port Id="VmeADirVfcToVme_o" Dir="OUT"/>
<Port Id="VmeRetryOe_oe" Dir="OUT"/>
<Port Id="VmeRetry_on" Dir="OUT"/>
<Port Id="VmeBerr_o" Dir="OUT"/>
<Port Id="VmeTdoOe_oe" Dir="OUT"/>
<Port Id="VmeTdo_o" Dir="OUT"/>
<Port Id="Si57xSCl_ok" Dir="OUT"/>
<Port Id="Si57xSDa_io" Dir="INOUT"/>
<Port Id="Si57xOe_o" Dir="OUT"/>
<Port Id="FpGpIo1OutputMode_o" Dir="OUT"/>
<Port Id="FpGpIo2OutputMode_o" Dir="OUT"/>
<Port Id="FpGpIo34OutputMode_o" Dir="OUT"/>
<Port Id="AFpgaProgDone_io" Dir="INOUT"/>
<Port Id="AFpgaProgClk_io" Dir="INOUT"/>
<Port Id="AFpgaProgProgram_o" Dir="OUT"/>
<Port Id="AFpgaProgCsi_io" Dir="INOUT"/>
<Port Id="AFpgaProgRdWr_io" Dir="INOUT"/>
<Port Id="AFpgaProgInit_io" Dir="INOUT"/>
<Port Id="SysAppClk_ok" Dir="OUT"/>
<Port Id="FlashSFpgaD_o" Dir="OUT"/>
<Port Id="FlashSFpgaClk_ok" Dir="OUT"/>
<Port Id="FlashSFpgaCs_on" Dir="OUT"/>
<Port Id="FlashAFpgaD_o" Dir="OUT"/>
<Port Id="FlashAFpgaClk_ok" Dir="OUT"/>
<Port Id="FlashAFpgaCs_on" Dir="OUT"/>
<Port Id="VAdcSClk_ok" Dir="OUT"/>
<Port Id="VAdcDin_o" Dir="OUT"/>
<Port Id="VAdcCs_on" Dir="OUT"/>
<Port Id="VAdjCs_on" Dir="OUT"/>
<Port Id="VAdjSClk_ok" Dir="OUT"/>
<Port Id="VAdjDin_o" Dir="OUT"/>
<Port Id="VAdjInhibit_ozn" Dir="OUT"/>
<Port Id="VAdjSpi_o" Dir="OUT"/>
<Port Id="PllFmc1RefSel_o" Dir="OUT"/>
<Port Id="PllFmc1Ref1_ok" Dir="OUT"/>
<Port Id="PllFmc1Pd_on" Dir="OUT"/>
<Port Id="PllFmc1Synch_on" Dir="OUT"/>
<Port Id="PllFmc1Reset_orn" Dir="OUT"/>
<Port Id="PllFmc1SClk_ok" Dir="OUT"/>
<Port Id="PllFmc1SDio_io" Dir="INOUT"/>
<Port Id="PllFmc1Cs_on" Dir="OUT"/>
<Port Id="PllFmc2RefSel_o" Dir="OUT"/>
<Port Id="PllFmc2Ref1_ok" Dir="OUT"/>
<Port Id="PllFmc2Pd_on" Dir="OUT"/>
<Port Id="PllFmc2Synch_on" Dir="OUT"/>
<Port Id="PllFmc2Reset_orn" Dir="OUT"/>
<Port Id="PllFmc2SClk_ok" Dir="OUT"/>
<Port Id="PllFmc2SDio_io" Dir="INOUT"/>
<Port Id="PllFmc2Cs_on" Dir="OUT"/>
<Port Id="PllSysRefSel_o" Dir="OUT"/>
<Port Id="PllSysRef12_ok" Dir="OUT"/>
<Port Id="PllSysRef12_okn" Dir="OUT"/>
<Port Id="PllSysPd_on" Dir="OUT"/>
<Port Id="PllSysSynch_on" Dir="OUT"/>
<Port Id="PllSysReset_orn" Dir="OUT"/>
<Port Id="PllSysSClk_ok" Dir="OUT"/>
<Port Id="PllSysSDio_io" Dir="INOUT"/>
<Port Id="PllSysCs_on" Dir="OUT"/>
<Port Id="PllDdsRefSel_o" Dir="OUT"/>
<Port Id="PllDdsPd_on" Dir="OUT"/>
<Port Id="PllDdsSynch_on" Dir="OUT"/>
<Port Id="PllDdsReset_orn" Dir="OUT"/>
<Port Id="PllDdsClk_ok" Dir="OUT"/>
<Port Id="PllDdsSClk_ok" Dir="OUT"/>
<Port Id="PllDdsSDio_io" Dir="INOUT"/>
<Port Id="PllDdsCs_on" Dir="OUT"/>
<Port Id="PllDacSClk_ok" Dir="OUT"/>
<Port Id="PllDacSynch_on" Dir="OUT"/>
<Port Id="PllDacDin_o" Dir="OUT"/>
<Port Id="PllDacClrn_orn" Dir="OUT"/>
<Port Id="PllDacLDac_on" Dir="OUT"/>
<Port Id="DdsTxEnable_o" Dir="OUT"/>
<Port Id="DdsMasterRst_or" Dir="OUT"/>
<Port Id="DdsPowerDown_o" Dir="OUT"/>
<Port Id="DdsIOUpdate_io" Dir="INOUT"/>
<Port Id="DdsOsk_o" Dir="OUT"/>
<Port Id="DdsDrHold_o" Dir="OUT"/>
<Port Id="DdsSClk_o" Dir="OUT"/>
<Port Id="DdsSDio_io" Dir="OUT"/>
<Port Id="DdsIoReset_or" Dir="OUT"/>
<Port Id="DdsDrCtl_o" Dir="OUT"/>
<Port Id="DdsSyncIn_ok" Dir="OUT"/>
<Port Id="DdsSyncIn_okn" Dir="OUT"/>
<Port Id="VmeP0BuslineDir_o" Dir="OUT"/>
<Port Id="VmeP0BuslineOe_o" Dir="OUT"/>
<Port Id="VmeP0HwLowByteDir_o" Dir="OUT"/>
<Port Id="VmeP0HwLowByteOe_o" Dir="OUT"/>
<Port Id="VmeP0HwHighByteDir_o" Dir="OUT"/>
<Port Id="VmeP0HwHighByteOe_o" Dir="OUT"/>
<Port Id="VmeP0BunchSelectDir_o" Dir="OUT"/>
<Port Id="VmeP0BunchSelectOe_o" Dir="OUT"/>
<Port Id="VmeP0LvdsBunchClkOut_o" Dir="OUT"/>
<Port Id="VmeP0LvdsTClkOut_o" Dir="OUT"/>
<Port Id="TempIdDQ_io" Dir="INOUT"/>
<Port Id="DdrReset_or" Dir="OUT"/>
<Port Id="DdrCkE_o" Dir="OUT"/>
<Port Id="DdrWe_o" Dir="OUT"/>
<Port Id="DdrCk_ok" Dir="OUT"/>
<Port Id="DdrCk_okn" Dir="OUT"/>
<Port Id="DdrODT_o" Dir="OUT"/>
<Port Id="DdrRAS_o" Dir="OUT"/>
<Port Id="DdrCAS_o" Dir="OUT"/>
<Port Id="DdrUDM_o" Dir="OUT"/>
<Port Id="DdrLDM_o" Dir="OUT"/>
<Port Id="DdrLDQS_io" Dir="INOUT"/>
<Port Id="DdrLDQS_ion" Dir="INOUT"/>
<Port Id="DdrUDQS_io" Dir="INOUT"/>
<Port Id="DdrUDQS_ion" Dir="INOUT"/>
<Port Id="WRModeDef1_i" Dir="OUT"/>
<Port Id="WRModeDef2_io" Dir="INOUT"/>
<Port Id="WRRateSelect_o" Dir="OUT"/>
<Port Id="WRTxDisable_o" Dir="OUT"/>
<Port Id="Sfp2ModeDef1_i" Dir="OUT"/>
<Port Id="Sfp2ModeDef2_io" Dir="INOUT"/>
<Port Id="Sfp2RateSelect" Dir="OUT"/>
<Port Id="Sfp2TxDisable_o" Dir="OUT"/>
<Port Id="Fmc1PGC2M_in" Dir="OUT"/>
<Port Id="Fmc2PGC2M_in" Dir="OUT"/>
<Port Id="Fmc1SDa_io" Dir="INOUT"/>
<Port Id="Fmc1SCl_ok" Dir="OUT"/>
<Port Id="Fmc2SDa_io" Dir="INOUT"/>
<Port Id="Fmc2SCl_ok" Dir="OUT"/>
<DiffPair Pos="Si57x_ik" Neg="Si57x_ikn"/>
<DiffPair Pos="PllFmc12SFpga_ik" Neg="PllFmc12SFpga_ikn"/>
<DiffPair Pos="PllFmc22SFpga_ik" Neg="PllFmc22SFpga_ikn"/>
<DiffPair Pos="PllSys2SFpga_ik" Neg="PllSys2SFpga_ikn"/>
<DiffPair Pos="PllDds2SFpga_ik" Neg="PllDds2SFpga_ikn"/>
<DiffPair Pos="DdsSyncOut_ik" Neg="DdsSyncOut_ikn"/>
<DiffPair Pos="PllSysRef12_ok" Neg="PllSysRef12_okn"/>
<DiffPair Pos="DdsSyncIn_ok" Neg="DdsSyncIn_okn"/>
<DiffPair Pos="DdrCk_ok" Neg="DdrCk_okn"/>
<DiffPair Pos="DdrLDQS_io" Neg="DdrLDQS_ion"/>
<DiffPair Pos="DdrUDQS_io" Neg="DdrUDQS_ion"/>
</Ifc>
</Interface>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.data/wt/webtalk_pa.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Thu Dec 16 18:30:15 2010">
<section name="Project Information" visible="false">
<property name="ProjectID" value="38e8d76333c944a3b569175753d76247" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="GateLvl" type="DesignMode"/>
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="SaveDesign" value="2" type="JavaHandler"/>
</item>
<item name="Other">
<property name="GuiMode" value="0" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/>
<property name="ISEMode" value="17" type="ISEMode"/>
</item>
</section>
</application>
</document>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/SystemFpga.ppr 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0"?>
<Project Version="4" Minor="6">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
</Project>
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/planAhead.jou 0 → 100644
View file @ 23b1b4b5
#-----------------------------------------------------------
# PlanAhead v12.3
# Build 101344 by hdbuild on Sat Sep 4 00:26:34 MDT 2010
# Start of session at: Thu Dec 16 18:11:18 2010
# Process ID: 5196
# Log file: C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1/planAhead.log
# Journal file: C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
start_gui -source C:/VFC_SVN/firmware/XilinxISE/SystemFpga/pa.fromNetlist.tcl
# create_project -name SystemFpga -dir "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1" -part xc6slx150tfgg676-3
# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
# set_property edif_top_file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {C:/VFC_SVN/firmware/XilinxISE/SystemFpga} }
# set_param project.pinAheadLayout yes
# set_param project.paUcfFile "SFpga.ucf"
# add_files "SFpga.ucf" -fileset [get_property constrset [current_run]]
# open_netlist_design
set_property IOSTANDARD DIFF_SSTL15_II [get_ports DdrCk_okn DdrCk_ok]
close_design
open_netlist_design -name constrs_1
set_property IOSTANDARD DIFF_SSTL15_II [get_ports DdrLDQS_io]
set_property IOSTANDARD DIFF_SSTL15_II [get_ports DdrUDQS_ion DdrUDQS_io]
save_design
set_property IOSTANDARD DIFF_SSTL15_II [get_ports DdrCk_okn DdrCk_ok]
save_design
exit
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/planAhead.log 0 → 100644
View file @ 23b1b4b5
#-----------------------------------------------------------
# PlanAhead v12.3
# Build 101344 by hdbuild on Sat Sep 4 00:26:34 MDT 2010
# Start of session at: Thu Dec 16 18:11:18 2010
# Process ID: 5196
# Log file: C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1/planAhead.log
# Journal file: C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead
INFO: [HD-Licensing 1] Got a license: PlanAhead
INFO: [HD-Licensing 3] Your PlanAhead license expires in -199 day(s)
INFO: [HD-ArchReader 0] Loading parts and site information from C:\Xilinx\12.3\ISE_DS\PlanAhead\parts\arch.xml
INFO: [HD-RTPRIM 0] Parsing RTL primitives file 'C:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file 'C:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
start_gui -source C:/VFC_SVN/firmware/XilinxISE/SystemFpga/pa.fromNetlist.tcl
# create_project -name SystemFpga -dir "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/planAhead_run_1" -part xc6slx150tfgg676-3
# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
# set_property edif_top_file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {C:/VFC_SVN/firmware/XilinxISE/SystemFpga} }
# set_param project.pinAheadLayout yes
# set_param project.paUcfFile "SFpga.ucf"
# add_files "SFpga.ucf" -fileset [get_property constrset [current_run]]
# open_netlist_design
INFO: Run is defaulting to constrset part: xc6slx150tfgg676-3
INFO: [HD-EDIFIN 0] Parsing Edif File '.\.HDI-PlanAhead-5196-bqplv2\ngc2edif\SFpga.edif'
INFO: [HD-EDIFIN 1] Finished Parsing Edif File '.\.HDI-PlanAhead-5196-bqplv2\ngc2edif\SFpga.edif'
INFO: [HD-Unisim Transformer 0] Analyzing 38 legacy Unisim elements for replacement
INFO: [HD-Unisim Transformer 1] No Unisim elements were transformed.
WARN: [HD-NETLIST 3] Netlist 'SFpga' is not ideal for floorplanning, since the cellview 'SFpga' defined in file 'SFpga.ngc' contains large number of primitives. Please consider enabling hierarchy in synthesis before floorplan. You can enable hierarchy in XST by setting '-keep_hierarchy=yes' or '-netlist_hierarchy=rebuilt' flags.
INFO: [HD-ArchReader 7] Loading clock regions from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lxt/xc6slx150t/ClockRegion.xml
INFO: [HD-ArchReader 8] Loading clock buffers from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lxt/xc6slx150t/ClockBuffers.xml
INFO: [HD-ArchReader 3] Loading package from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lxt/xc6slx150t/fgg676/Package.xml
INFO: [HD-ArchReader 13] Loading package pin functions from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/PinFunctions.xml...
INFO: [HD-ArchReader 4] Loading io standards from C:/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan6/IOStandards.xml
INFO: [HD-ArchReader 12] Loading device configuration modes from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/ConfigModes.xml
INFO: [HD-GDRC 0] Loading list of drcs for the architecture : C:/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan6/drc.xml
INFO: [HD-UCFReader 0] Parsing UCF File : .\SFpga.ucf
INFO: [HD-UCFReader 1] Finished Parsing UCF File : .\SFpga.ucf
DESIGN RULE CHECK VIOLATION REPORT
Build: PlanAhead v12.3 by hdbuild
on Sat Sep 4 00:26:34 MDT 2010
Report: by boccardi on host bqplv2, pid 5196
on Thu Dec 16 18:11:37 2010
REPORT SUMMARY
Netlist: netlist
Floorplan: <none>
Design limits: <entire design considered>
Checks: Unknown block name
Unknown Unisim pin name
Mismatching Attribute
Max vios: <unlimited>
Vios found: 0
REPORT DETAILS
INFO: [HD-LIB 0] Reading timing library C:/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan6/spartan6.lib .
INFO: [HD-LIB 1] Done reading timing library C:/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan6/spartan6.lib .
set_property IOSTANDARD DIFF_SSTL15_II [get_ports DdrCk_okn DdrCk_ok]
close_design
open_netlist_design -name constrs_1
INFO: Run is defaulting to constrset part: xc6slx150tfgg676-3
INFO: [HD-EDIFIN 0] Parsing Edif File '.\.HDI-PlanAhead-5196-bqplv2\ngc2edif\SFpga.edif'
INFO: [HD-EDIFIN 1] Finished Parsing Edif File '.\.HDI-PlanAhead-5196-bqplv2\ngc2edif\SFpga.edif'
INFO: [HD-Unisim Transformer 0] Analyzing 40 legacy Unisim elements for replacement
INFO: [HD-Unisim Transformer 1] No Unisim elements were transformed.
WARN: [HD-NETLIST 3] Netlist 'SFpga' is not ideal for floorplanning, since the cellview 'SFpga' defined in file 'SFpga.ngc' contains large number of primitives. Please consider enabling hierarchy in synthesis before floorplan. You can enable hierarchy in XST by setting '-keep_hierarchy=yes' or '-netlist_hierarchy=rebuilt' flags.
INFO: [HD-ArchReader 7] Loading clock regions from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lxt/xc6slx150t/ClockRegion.xml
INFO: [HD-ArchReader 8] Loading clock buffers from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lxt/xc6slx150t/ClockBuffers.xml
INFO: [HD-ArchReader 3] Loading package from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lxt/xc6slx150t/fgg676/Package.xml
INFO: [HD-ArchReader 13] Loading package pin functions from C:/Xilinx/12.3/ISE_DS/PlanAhead/parts/xilinx/spartan6/PinFunctions.xml...
INFO: [HD-ArchReader 4] Loading io standards from C:/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan6/IOStandards.xml
INFO: [HD-GDRC 0] Loading list of drcs for the architecture : C:/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan6/drc.xml
INFO: [HD-UCFReader 0] Parsing UCF File : .\SFpga.ucf
INFO: [HD-UCFReader 1] Finished Parsing UCF File : .\SFpga.ucf
DESIGN RULE CHECK VIOLATION REPORT
Build: PlanAhead v12.3 by hdbuild
on Sat Sep 4 00:26:34 MDT 2010
Report: by boccardi on host bqplv2, pid 5196
on Thu Dec 16 18:28:49 2010
REPORT SUMMARY
Netlist: netlist
Floorplan: <none>
Design limits: <entire design considered>
Checks: Unknown block name
Unknown Unisim pin name
Mismatching Attribute
Max vios: <unlimited>
Vios found: 0
REPORT DETAILS
INFO: [HD-LIB 0] Reading timing library C:/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan6/spartan6.lib .
INFO: [HD-LIB 1] Done reading timing library C:/Xilinx/12.3/ISE_DS/PlanAhead/./parts/xilinx/spartan6/spartan6.lib .
set_property IOSTANDARD DIFF_SSTL15_II [get_ports DdrLDQS_io]
set_property IOSTANDARD DIFF_SSTL15_II [get_ports DdrUDQS_ion DdrUDQS_io]
save_design
set_property IOSTANDARD DIFF_SSTL15_II [get_ports DdrCk_okn DdrCk_ok]
save_design
exit
INFO: [HD-Application 0] Exiting PlanAhead...
INFO: [HD-Licensing 2] Releasing license: PlanAhead
trunk/firmware/XilinxISE/SystemFpga/planAhead_run_1/planAhead_run.log 0 → 100644
View file @ 23b1b4b5
****** PlanAhead v12.3
**** Build 101344 by hdbuild on Sat Sep 4 00:26:34 MDT 2010
** Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved.
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Release 12.3 - ngc2edif M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design SFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to SFpga.xncf, ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SFpga.edif ...
ngc2edif: Total memory usage is 38464 kilobytes
INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead
INFO: [HD-Licensing 1] Got a license: PlanAhead
INFO: [HD-Licensing 3] Your PlanAhead license expires in -199 day(s)
INFO: [HD-ArchReader 0] Loading parts and site information from C:\Xilinx\12.3\ISE_DS\PlanAhead\parts\arch.xml
INFO: [HD-RTPRIM 0] Parsing RTL primitives file 'C:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file 'C:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
starting gui ...
INFO: [HD-Application 0] Exiting PlanAhead...
INFO: [HD-Licensing 2] Releasing license: PlanAhead
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn 0 → 100644
View file @ 23b1b4b5
Release 12.3 - Bitgen M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx150t.nph' in environment
C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf.
Thu Dec 16 18:44:48 2010
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 2** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No** |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| multipin_wakeup | No** |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No** |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | 0xFFFF |
+----------------------+----------------------+
| spi_buswidth | 1** |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from SFpga.pcf.
Running DRC.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<3>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<4>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<5>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<6>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<7>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRModeDef0_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTrst_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSDo_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PllDacDout_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsTClkIn_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPllLock_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2ModeDef0_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2LoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRTxFault_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsBunchClkIn_i_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TempIdDQ_io_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsDrOver_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTdi_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTck_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc1PrsntM2C_in_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTms_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc2PrsntM2C_in_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
DRC detected 0 errors and 47 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "sfpga.bit".
Bitstream generation is complete.
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc 0 → 100644
View file @ 23b1b4b5
Release 12.3 Drc M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:48 2010
drc -z SFpga.ncd SFpga.pcf
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<3>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<4>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<5>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<6>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<7>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRModeDef0_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTrst_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSDo_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PllDacDout_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsTClkIn_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPllLock_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2ModeDef0_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2LoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRTxFault_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeP0LvdsBunchClkIn_i_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TempIdDQ_io_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsDrOver_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTdi_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTck_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc1PrsntM2C_in_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeTms_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Fmc2PrsntM2C_in_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
DRC detected 0 errors and 47 warnings. Please see the previously displayed
individual error or warning messages for more details.
trunk/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html 0 → 100644
View file @ 23b1b4b5
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>&nbsp;<BR><HR>&nbsp;<BR>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Software Version and Target Device</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD><xtag-property name="ProductVersion">ISE:12.3</xtag-property><xtag-property name="ProductConfiguration"> (ISE)</xtag-property><xtag-property name="BuildVersion"> - M.70d</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Family:</B></TD>
<TD><xtag-property name="TargetFamily">Spartan6</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
<TD><xtag-property name="OSPlatform">NT</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD><xtag-property name="TargetDevice">xc6slx150t</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">d36a4175861f4f48ac5a6ada421762f9</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">3</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Registration ID</B></TD>
<TD><xtag-property name="RegistrationID">174122088_179509804_641</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Speed:</B></TD>
<TD><xtag-property name="TargetSpeed">-3</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2010-12-16T18:45:20</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="UserEnvironment">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows XP Professional</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 3 (build 2600)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value> Intel(R) Pentium(R) D CPU 3.40GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3389 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows XP Professional</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 3 (build 2600)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value> Intel(R) Pentium(R) D CPU 3.40GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3389 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Device Usage Statistics</B></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="MacroStatistics">
<TD>
<xtag-group><xtag-group-name name="Adders/Subtractors=5">Adders/Subtractors=5</xtag-group-name>
<UL>
<LI><xtag-item1>12-bit adder=1</xtag-item1></LI>
<LI><xtag-item1>16-bit adder=1</xtag-item1></LI>
<LI><xtag-item1>22-bit adder=1</xtag-item1></LI>
<LI><xtag-item1>3-bit adder=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Comparators=9">Comparators=9</xtag-group-name>
<UL>
<LI><xtag-item1>1-bit comparator equal=1</xtag-item1></LI>
<LI><xtag-item1>12-bit comparator equal=1</xtag-item1></LI>
<LI><xtag-item1>16-bit comparator equal=2</xtag-item1></LI>
<LI><xtag-item1>3-bit comparator equal=4</xtag-item1></LI>
<LI><xtag-item1>8-bit comparator equal=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Counters=10">Counters=10</xtag-group-name>
<UL>
<LI><xtag-item1>16-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>20-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>22-bit up counter=3</xtag-item1></LI>
<LI><xtag-item1>3-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>4-bit updown counter=1</xtag-item1></LI>
<LI><xtag-item1>9-bit up counter=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FSMs=2">FSMs=2</xtag-group-name>
</xtag-group>
<xtag-group><xtag-group-name name="Multiplexers=117">Multiplexers=117</xtag-group-name>
<UL>
<LI><xtag-item1>1-bit 2-to-1 multiplexer=44</xtag-item1></LI>
<LI><xtag-item1>1-bit 32-to-1 multiplexer=1</xtag-item1></LI>
<LI><xtag-item1>1-bit 4-to-1 multiplexer=35</xtag-item1></LI>
<LI><xtag-item1>12-bit 2-to-1 multiplexer=2</xtag-item1></LI>
<LI><xtag-item1>16-bit 2-to-1 multiplexer=8</xtag-item1></LI>
<LI><xtag-item1>22-bit 2-to-1 multiplexer=2</xtag-item1></LI>
<LI><xtag-item1>32-bit 2-to-1 multiplexer=20</xtag-item1></LI>
<LI><xtag-item1>32-bit 4-to-1 multiplexer=2</xtag-item1></LI>
<LI><xtag-item1>32-bit 7-to-1 multiplexer=1</xtag-item1></LI>
<LI><xtag-item1>5-bit 2-to-1 multiplexer=1</xtag-item1></LI>
<LI><xtag-item1>7-bit 2-to-1 multiplexer=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="RAMs=1">RAMs=1</xtag-group-name>
<UL>
<LI><xtag-item1>8x8-bit dual-port distributed RAM=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Registers=680">Registers=680</xtag-group-name>
<UL>
<LI><xtag-item1>Flip-Flops=680</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Xors=4">Xors=4</xtag-group-name>
<UL>
<LI><xtag-item1>1-bit xor3=2</xtag-item1></LI>
<LI><xtag-item1>1-bit xor6=2</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
<xtag-section name="DesignStatistics">
<TD>
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>AGG_BONDED_IO=330</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=330</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=328</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=371</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=326</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=535</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=382</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=196</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1113</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=324</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=166</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=154</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=571</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=6</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=6</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=154</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=70</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=297</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=52</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=32</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1259</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_F7MUX=18</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=796</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=118</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=3</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=85</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=1863</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=39</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=205</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=253</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=19</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=301</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=1944</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=358</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=137</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=50</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=245</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=245</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3687</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1558</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1419</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=137</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=116</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=850</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4252</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5340</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=298</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2304</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=132</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=342</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=354</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=11</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>BUFG-BUFGMUX=4</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=161</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=33</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=76</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=65</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
<xtag-section name="DeviceUsage">
<TD>
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
<UL>
<LI><xtag-item2>BUFG=4</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=4</xtag-item2></LI>
<LI><xtag-item2>CARRY4=52</xtag-item2></LI>
<LI><xtag-item2>FF_SR=73</xtag-item2></LI>
<LI><xtag-item2>HARD0=11</xtag-item2></LI>
<LI><xtag-item2>IOB=326</xtag-item2></LI>
<LI><xtag-item2>IOBM=2</xtag-item2></LI>
<LI><xtag-item2>IOBM_OUTBUF=2</xtag-item2></LI>
<LI><xtag-item2>IOBS=2</xtag-item2></LI>
<LI><xtag-item2>IOB_IMUX=159</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=159</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI>
<LI><xtag-item2>LUT5=333</xtag-item2></LI>
<LI><xtag-item2>LUT6=900</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM5=4</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM6=11</xtag-item2></LI>
<LI><xtag-item2>NULLMUX=3</xtag-item2></LI>
<LI><xtag-item2>PAD=330</xtag-item2></LI>
<LI><xtag-item2>REG_SR=723</xtag-item2></LI>
<LI><xtag-item2>SELMUX2_1=18</xtag-item2></LI>
<LI><xtag-item2>SLICEL=70</xtag-item2></LI>
<LI><xtag-item2>SLICEM=4</xtag-item2></LI>
<LI><xtag-item2>SLICEX=297</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Configuration Data</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="ReportConfigData">
<TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:73] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:62] [SRINIT1:11]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:37] [SYNC:36]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item3>SUSPEND=[3STATE:2]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
<UL>
<LI><xtag-item3>DIFF_TERM=[TRUE:1]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item3>DRIVEATTRBOX=[12:167]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:167]</xtag-item3></LI>
<LI><xtag-item3>SUSPEND=[3STATE:198]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:4] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LUT_OR_MEM=[RAM:4]</xtag-item3></LI>
<LI><xtag-item3>RAMMODE=[DPRAM32:4]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:11] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LUT_OR_MEM=[RAM:11]</xtag-item3></LI>
<LI><xtag-item3>RAMMODE=[SRL16:3] [DPRAM32:4] [DPRAM64:4]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:723] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:723]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:671] [SRINIT1:52]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:252] [SYNC:471]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:40] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:4] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:209] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Pin Data</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="ReportConfigData">
<TD>
<xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=4</xtag-item1></LI>
<LI><xtag-item1>O=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=4</xtag-item1></LI>
<LI><xtag-item1>O=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL>
<LI><xtag-item1>CIN=40</xtag-item1></LI>
<LI><xtag-item1>CO1=2</xtag-item1></LI>
<LI><xtag-item1>CO2=1</xtag-item1></LI>
<LI><xtag-item1>CO3=41</xtag-item1></LI>
<LI><xtag-item1>CYINIT=12</xtag-item1></LI>
<LI><xtag-item1>DI0=51</xtag-item1></LI>
<LI><xtag-item1>DI1=47</xtag-item1></LI>
<LI><xtag-item1>DI2=47</xtag-item1></LI>
<LI><xtag-item1>DI3=41</xtag-item1></LI>
<LI><xtag-item1>O0=48</xtag-item1></LI>
<LI><xtag-item1>O1=47</xtag-item1></LI>
<LI><xtag-item1>O2=43</xtag-item1></LI>
<LI><xtag-item1>O3=43</xtag-item1></LI>
<LI><xtag-item1>S0=52</xtag-item1></LI>
<LI><xtag-item1>S1=51</xtag-item1></LI>
<LI><xtag-item1>S2=47</xtag-item1></LI>
<LI><xtag-item1>S3=46</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=40</xtag-item1></LI>
<LI><xtag-item1>CK=73</xtag-item1></LI>
<LI><xtag-item1>D=73</xtag-item1></LI>
<LI><xtag-item1>Q=73</xtag-item1></LI>
<LI><xtag-item1>SR=36</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
<UL>
<LI><xtag-item1>0=11</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
<UL>
<LI><xtag-item1>DIFFI_IN=1</xtag-item1></LI>
<LI><xtag-item1>I=159</xtag-item1></LI>
<LI><xtag-item1>O=198</xtag-item1></LI>
<LI><xtag-item1>PAD=326</xtag-item1></LI>
<LI><xtag-item1>PADOUT=1</xtag-item1></LI>
<LI><xtag-item1>T=44</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOBM">IOBM</xtag-group-name>
<UL>
<LI><xtag-item1>DIFFO_OUT=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
<LI><xtag-item1>PAD=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=2</xtag-item1></LI>
<LI><xtag-item1>OUT=2</xtag-item1></LI>
<LI><xtag-item1>OUTN=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOBS">IOBS</xtag-group-name>
<UL>
<LI><xtag-item1>DIFFO_IN=2</xtag-item1></LI>
<LI><xtag-item1>PAD=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name>
<UL>
<LI><xtag-item1>I=159</xtag-item1></LI>
<LI><xtag-item1>OUT=159</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
<UL>
<LI><xtag-item1>DIFFI_IN=1</xtag-item1></LI>
<LI><xtag-item1>OUT=159</xtag-item1></LI>
<LI><xtag-item1>PAD=159</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=198</xtag-item1></LI>
<LI><xtag-item1>OUT=198</xtag-item1></LI>
<LI><xtag-item1>TRI=44</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A1=48</xtag-item1></LI>
<LI><xtag-item1>A2=49</xtag-item1></LI>
<LI><xtag-item1>A3=124</xtag-item1></LI>
<LI><xtag-item1>A4=130</xtag-item1></LI>
<LI><xtag-item1>A5=64</xtag-item1></LI>
<LI><xtag-item1>O5=333</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=311</xtag-item1></LI>
<LI><xtag-item1>A2=482</xtag-item1></LI>
<LI><xtag-item1>A3=576</xtag-item1></LI>
<LI><xtag-item1>A4=824</xtag-item1></LI>
<LI><xtag-item1>A5=751</xtag-item1></LI>
<LI><xtag-item1>A6=886</xtag-item1></LI>
<LI><xtag-item1>O6=900</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
<UL>
<LI><xtag-item1>A1=4</xtag-item1></LI>
<LI><xtag-item1>A2=4</xtag-item1></LI>
<LI><xtag-item1>A3=4</xtag-item1></LI>
<LI><xtag-item1>A4=4</xtag-item1></LI>
<LI><xtag-item1>A5=4</xtag-item1></LI>
<LI><xtag-item1>CLK=4</xtag-item1></LI>
<LI><xtag-item1>DI1=4</xtag-item1></LI>
<LI><xtag-item1>O5=4</xtag-item1></LI>
<LI><xtag-item1>WA1=4</xtag-item1></LI>
<LI><xtag-item1>WA2=4</xtag-item1></LI>
<LI><xtag-item1>WA3=4</xtag-item1></LI>
<LI><xtag-item1>WA4=4</xtag-item1></LI>
<LI><xtag-item1>WA5=4</xtag-item1></LI>
<LI><xtag-item1>WE=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=11</xtag-item1></LI>
<LI><xtag-item1>A2=11</xtag-item1></LI>
<LI><xtag-item1>A3=11</xtag-item1></LI>
<LI><xtag-item1>A4=11</xtag-item1></LI>
<LI><xtag-item1>A5=11</xtag-item1></LI>
<LI><xtag-item1>A6=11</xtag-item1></LI>
<LI><xtag-item1>CLK=11</xtag-item1></LI>
<LI><xtag-item1>DI1=4</xtag-item1></LI>
<LI><xtag-item1>DI2=7</xtag-item1></LI>
<LI><xtag-item1>O6=8</xtag-item1></LI>
<LI><xtag-item1>WA1=8</xtag-item1></LI>
<LI><xtag-item1>WA2=8</xtag-item1></LI>
<LI><xtag-item1>WA3=8</xtag-item1></LI>
<LI><xtag-item1>WA4=8</xtag-item1></LI>
<LI><xtag-item1>WA5=8</xtag-item1></LI>
<LI><xtag-item1>WA6=8</xtag-item1></LI>
<LI><xtag-item1>WE=11</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="NULLMUX">NULLMUX</xtag-group-name>
<UL>
<LI><xtag-item1>0=3</xtag-item1></LI>
<LI><xtag-item1>OUT=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name>
<UL>
<LI><xtag-item1>PAD=330</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=401</xtag-item1></LI>
<LI><xtag-item1>CK=723</xtag-item1></LI>
<LI><xtag-item1>D=723</xtag-item1></LI>
<LI><xtag-item1>Q=723</xtag-item1></LI>
<LI><xtag-item1>SR=472</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name>
<UL>
<LI><xtag-item1>0=18</xtag-item1></LI>
<LI><xtag-item1>1=18</xtag-item1></LI>
<LI><xtag-item1>OUT=18</xtag-item1></LI>
<LI><xtag-item1>S0=18</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A=6</xtag-item1></LI>
<LI><xtag-item1>A1=9</xtag-item1></LI>
<LI><xtag-item1>A2=10</xtag-item1></LI>
<LI><xtag-item1>A3=13</xtag-item1></LI>
<LI><xtag-item1>A4=46</xtag-item1></LI>
<LI><xtag-item1>A5=27</xtag-item1></LI>
<LI><xtag-item1>A6=59</xtag-item1></LI>
<LI><xtag-item1>AMUX=18</xtag-item1></LI>
<LI><xtag-item1>AQ=36</xtag-item1></LI>
<LI><xtag-item1>AX=8</xtag-item1></LI>
<LI><xtag-item1>B=9</xtag-item1></LI>
<LI><xtag-item1>B1=8</xtag-item1></LI>
<LI><xtag-item1>B2=11</xtag-item1></LI>
<LI><xtag-item1>B3=13</xtag-item1></LI>
<LI><xtag-item1>B4=48</xtag-item1></LI>
<LI><xtag-item1>B5=28</xtag-item1></LI>
<LI><xtag-item1>B6=58</xtag-item1></LI>
<LI><xtag-item1>BMUX=18</xtag-item1></LI>
<LI><xtag-item1>BQ=37</xtag-item1></LI>
<LI><xtag-item1>BX=6</xtag-item1></LI>
<LI><xtag-item1>C1=7</xtag-item1></LI>
<LI><xtag-item1>C2=8</xtag-item1></LI>
<LI><xtag-item1>C3=19</xtag-item1></LI>
<LI><xtag-item1>C4=49</xtag-item1></LI>
<LI><xtag-item1>C5=33</xtag-item1></LI>
<LI><xtag-item1>C6=62</xtag-item1></LI>
<LI><xtag-item1>CE=15</xtag-item1></LI>
<LI><xtag-item1>CIN=40</xtag-item1></LI>
<LI><xtag-item1>CLK=40</xtag-item1></LI>
<LI><xtag-item1>CMUX=32</xtag-item1></LI>
<LI><xtag-item1>COUT=40</xtag-item1></LI>
<LI><xtag-item1>CQ=35</xtag-item1></LI>
<LI><xtag-item1>CX=21</xtag-item1></LI>
<LI><xtag-item1>D=1</xtag-item1></LI>
<LI><xtag-item1>D1=8</xtag-item1></LI>
<LI><xtag-item1>D2=21</xtag-item1></LI>
<LI><xtag-item1>D3=24</xtag-item1></LI>
<LI><xtag-item1>D4=53</xtag-item1></LI>
<LI><xtag-item1>D5=35</xtag-item1></LI>
<LI><xtag-item1>D6=62</xtag-item1></LI>
<LI><xtag-item1>DMUX=17</xtag-item1></LI>
<LI><xtag-item1>DQ=34</xtag-item1></LI>
<LI><xtag-item1>DX=7</xtag-item1></LI>
<LI><xtag-item1>SR=22</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
<UL>
<LI><xtag-item1>A=2</xtag-item1></LI>
<LI><xtag-item1>A1=3</xtag-item1></LI>
<LI><xtag-item1>A2=3</xtag-item1></LI>
<LI><xtag-item1>A3=3</xtag-item1></LI>
<LI><xtag-item1>A4=3</xtag-item1></LI>
<LI><xtag-item1>A5=3</xtag-item1></LI>
<LI><xtag-item1>A6=3</xtag-item1></LI>
<LI><xtag-item1>AI=2</xtag-item1></LI>
<LI><xtag-item1>AMUX=1</xtag-item1></LI>
<LI><xtag-item1>AQ=1</xtag-item1></LI>
<LI><xtag-item1>AX=2</xtag-item1></LI>
<LI><xtag-item1>B=2</xtag-item1></LI>
<LI><xtag-item1>B1=2</xtag-item1></LI>
<LI><xtag-item1>B2=2</xtag-item1></LI>
<LI><xtag-item1>B3=2</xtag-item1></LI>
<LI><xtag-item1>B4=2</xtag-item1></LI>
<LI><xtag-item1>B5=2</xtag-item1></LI>
<LI><xtag-item1>B6=2</xtag-item1></LI>
<LI><xtag-item1>BI=1</xtag-item1></LI>
<LI><xtag-item1>BMUX=1</xtag-item1></LI>
<LI><xtag-item1>BX=1</xtag-item1></LI>
<LI><xtag-item1>C=1</xtag-item1></LI>
<LI><xtag-item1>C1=3</xtag-item1></LI>
<LI><xtag-item1>C2=3</xtag-item1></LI>
<LI><xtag-item1>C3=3</xtag-item1></LI>
<LI><xtag-item1>C4=3</xtag-item1></LI>
<LI><xtag-item1>C5=3</xtag-item1></LI>
<LI><xtag-item1>C6=3</xtag-item1></LI>
<LI><xtag-item1>CE=4</xtag-item1></LI>
<LI><xtag-item1>CI=2</xtag-item1></LI>
<LI><xtag-item1>CLK=4</xtag-item1></LI>
<LI><xtag-item1>CMUX=1</xtag-item1></LI>
<LI><xtag-item1>CQ=1</xtag-item1></LI>
<LI><xtag-item1>CX=2</xtag-item1></LI>
<LI><xtag-item1>D1=3</xtag-item1></LI>
<LI><xtag-item1>D2=3</xtag-item1></LI>
<LI><xtag-item1>D3=3</xtag-item1></LI>
<LI><xtag-item1>D4=3</xtag-item1></LI>
<LI><xtag-item1>D5=3</xtag-item1></LI>
<LI><xtag-item1>D6=3</xtag-item1></LI>
<LI><xtag-item1>DI=2</xtag-item1></LI>
<LI><xtag-item1>DMUX=1</xtag-item1></LI>
<LI><xtag-item1>DQ=1</xtag-item1></LI>
<LI><xtag-item1>DX=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=111</xtag-item1></LI>
<LI><xtag-item1>A1=97</xtag-item1></LI>
<LI><xtag-item1>A2=141</xtag-item1></LI>
<LI><xtag-item1>A3=176</xtag-item1></LI>
<LI><xtag-item1>A4=190</xtag-item1></LI>
<LI><xtag-item1>A5=190</xtag-item1></LI>
<LI><xtag-item1>A6=198</xtag-item1></LI>
<LI><xtag-item1>AMUX=45</xtag-item1></LI>
<LI><xtag-item1>AQ=169</xtag-item1></LI>
<LI><xtag-item1>AX=70</xtag-item1></LI>
<LI><xtag-item1>B=85</xtag-item1></LI>
<LI><xtag-item1>B1=73</xtag-item1></LI>
<LI><xtag-item1>B2=116</xtag-item1></LI>
<LI><xtag-item1>B3=143</xtag-item1></LI>
<LI><xtag-item1>B4=149</xtag-item1></LI>
<LI><xtag-item1>B5=152</xtag-item1></LI>
<LI><xtag-item1>B6=150</xtag-item1></LI>
<LI><xtag-item1>BMUX=36</xtag-item1></LI>
<LI><xtag-item1>BQ=133</xtag-item1></LI>
<LI><xtag-item1>BX=67</xtag-item1></LI>
<LI><xtag-item1>C=58</xtag-item1></LI>
<LI><xtag-item1>C1=82</xtag-item1></LI>
<LI><xtag-item1>C2=101</xtag-item1></LI>
<LI><xtag-item1>C3=129</xtag-item1></LI>
<LI><xtag-item1>C4=141</xtag-item1></LI>
<LI><xtag-item1>C5=143</xtag-item1></LI>
<LI><xtag-item1>C6=142</xtag-item1></LI>
<LI><xtag-item1>CE=110</xtag-item1></LI>
<LI><xtag-item1>CLK=209</xtag-item1></LI>
<LI><xtag-item1>CMUX=30</xtag-item1></LI>
<LI><xtag-item1>CQ=149</xtag-item1></LI>
<LI><xtag-item1>CX=64</xtag-item1></LI>
<LI><xtag-item1>D=91</xtag-item1></LI>
<LI><xtag-item1>D1=72</xtag-item1></LI>
<LI><xtag-item1>D2=107</xtag-item1></LI>
<LI><xtag-item1>D3=134</xtag-item1></LI>
<LI><xtag-item1>D4=148</xtag-item1></LI>
<LI><xtag-item1>D5=150</xtag-item1></LI>
<LI><xtag-item1>D6=155</xtag-item1></LI>
<LI><xtag-item1>DMUX=38</xtag-item1></LI>
<LI><xtag-item1>DQ=127</xtag-item1></LI>
<LI><xtag-item1>DX=60</xtag-item1></LI>
<LI><xtag-item1>SR=152</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD><B>Tool Usage</B></TD></TR>
<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>ibiswriter -intstyle ise -vccaux &lt;fname&gt;.5 -truncate 20 &lt;fname&gt;.ncd &lt;fname&gt;.ibs</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>4</xtag-total-run-started></td>
<td><xtag-total-run-finished>4</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>edif2ngd</xtag-program-name></td>
<td><xtag-total-run-started>5</xtag-total-run-started></td>
<td><xtag-total-run-finished>5</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ibiswriter</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>19</xtag-total-run-started></td>
<td><xtag-total-run-finished>9</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngc2edif</xtag-program-name></td>
<td><xtag-total-run-started>12</xtag-total-run-started></td>
<td><xtag-total-run-finished>12</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>23</xtag-total-run-started></td>
<td><xtag-total-run-finished>23</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>9</xtag-total-run-started></td>
<td><xtag-total-run-finished>9</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>11</xtag-total-run-started></td>
<td><xtag-total-run-finished>11</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>30</xtag-total-run-started></td>
<td><xtag-total-run-finished>30</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISEHelpViewerData">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Help Statistics</B></TD></TR>
<TR ALIGN=LEFT><TD COLSPAN=2><xtag-group><B><xtag-group-name name="SearchFoundList">
Search words with results</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>input standard </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>lvds </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>verilog </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group><TR VALIGN=TOP><TD COLSPAN=2><xtag-group><B><xtag-group-name name="OpenedHelpFiles">
Help files</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>/doc/usenglish/isehelp/cgn_c_df_verilog_flow.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/cgn_c_df_verilog_instantiation_example.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/cgn_p_add_ip_com_flow.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/dsm_c_design_summary_overview.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/gls_r_glossary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_constraints_entry_methods.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_pin_assignment_pace.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ism_r_verlang_expressions.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pn_db_npw_project_summary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/pp_db_hdl_options_syn.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pp_p_process_io_pin_planning_pre_syn.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/sse_p_adding_attr.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="Project Statistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Project Statistics</B></TD></TR>
<TR>
<TD><xtag-design-property-name>PROP_Enable_Message_Filtering</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_FitterReportFormat</xtag-process-property-name>=<xtag-process-property-value>HTML</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_LastAppliedGoal</xtag-design-property-name>=<xtag-design-property-value>Balanced</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_LastAppliedStrategy</xtag-design-property-name>=<xtag-design-property-value>Xilinx Default (unlocked)</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_ManualCompileOrderImp</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_Simulator</xtag-design-property-name>=<xtag-design-property-value>ISim (VHDL/Verilog)</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_SynthTopFile</xtag-process-property-name>=<xtag-process-property-value>changed</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_Top_Level_Module_Type</xtag-design-property-name>=<xtag-design-property-value>HDL</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_UseSmartGuide</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_UserConstraintEditorPreference</xtag-process-property-name>=<xtag-process-property-value>Text Editor</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>3</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
</TR><TR><TD><xtag-process-property-name>PROP_lockPinsUcfFile</xtag-process-property-name>=<xtag-process-property-value>changed</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_AutoTop</xtag-design-property-name>=<xtag-design-property-value>true</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_DevFamily</xtag-design-property-name>=<xtag-design-property-value>Spartan6</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_DevDevice</xtag-design-property-name>=<xtag-design-property-value>xc6slx150t</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_DevFamilyPMName</xtag-design-property-name>=<xtag-design-property-value>spartan6</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>fgg676</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-3</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>Verilog</xtag-design-property-value></TD>
<TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD>
</TR><TR><TD><xtag-source-property-name>FILE_VERILOG</xtag-source-property-name>=<xtag-source-property-value>11</xtag-source-property-value></TD>
</TR></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="UnisimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>189</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>99</xtag-preunisim-param-value></TD>
</TR>
<TR>
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<TR>
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<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
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<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>135</xtag-postunisim-param-value></TD>
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</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
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<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
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<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD>
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<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>121</xtag-postunisim-param-value></TD>
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<TR>
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<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>18</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>152</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
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<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>65</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFTDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
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&nbsp;<BR></BODY></HTML>
trunk/firmware/XilinxISE/SystemFpga/webtalk.log 0 → 100644
View file @ 23b1b4b5
Release 12.3 - WebTalk (M.70d)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=3
WebTalk Summary
----------------
INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-16T18:45:27. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml 0 → 100644
View file @ 23b1b4b5
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Dec 16 18:44:36 2010">
<section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="3" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="3" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="Spartan6" type="design"/>
<property name="PROP_DevDevice" value="xc6slx150t" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
<property name="PROP_DevPackage" value="fgg676" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-3" type="design"/>
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
<property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VERILOG" value="11" type="source"/>
</section>
</application>
</document>
trunk/hdl/design/ApplicationFpga.v
View file @ 23b1b4b5
......@@ -2,7 +2,8 @@
module ApplicationFpga(
input SysAppClk_i,
input SysAppClk_ik,
output SysAppClk_ok,
inout [2:1] SysAppSlow_iob2,
inout [7:0] AFpgaProgD_iob8,
......@@ -22,7 +23,7 @@ module ApplicationFpga(
// Clock
//#####################################
wire Clk_k = SysAppClk_i;
wire Clk_k = SysAppClk_ik;
//#####################################
......@@ -65,11 +66,11 @@ Ser2MstWB i_Ser2MstWB(
.Stb_o(StbMaster),
.Dat_ib32(DatMasterI_b32),
.Ack_i(AckMaster),
.SerClk_ik(SysAppClk_i),
.SerClk_ik(SysAppClk_ik),
.SerDat_i(SysAppSlow_iob2[1]),
.SerCntrl_i(SysAppSlow_iob2[2]),
.Stb_i(AFpgaProgD_iob8[7]),
.SerClk_ok(AFpgaProgD_iob8[6]),
.SerClk_ok(SysAppClk_ok),
.SerDat_o(AFpgaProgD_iob8[5]),
.Ack_o(AFpgaProgD_iob8[4]));
......
trunk/hdl/design/SystemFpga.v
View file @ 23b1b4b5
......@@ -36,7 +36,7 @@ module SystemFpga (
input VmeTms_i,
// CLOCKS
input VcTcXo_ik,
(* IOSTANDARD="LVDS" *)input Si57x_ik,
input Si57x_ik,
output Si57xSCl_ok,
inout Si57xSDa_io,
output Si57xOe_o,
......@@ -44,6 +44,8 @@ module SystemFpga (
inout PushButton_ion,
// SWITCHES
input [1:0] Switch_ib2,
// Temperature and Unique ID 1-wire chip
inout TempIdDQ_io,
// Front Panel GPIO
output [7:0] FpLed_onb8,
// Front Panel GPIO
......@@ -51,7 +53,9 @@ module SystemFpga (
output FpGpIo2OutputMode_o,
output FpGpIo34OutputMode_o,
// Application FPGA Programming Pins
inout [7:0] AFpgaProgD_iob8,
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgDone_io,
output AFpgaProgProgram_o,
inout AFpgaProgClk_io,
inout [1:0] AFpgaProgM_iob2,
inout AFpgaProgCsi_io,
......@@ -59,6 +63,7 @@ module SystemFpga (
inout AFpgaProgInit_io,
// Application FPGA Clk
output SysAppClk_ok,
input SysAppClk_ik,
// Application FPGA Slow Communication
inout [2:1] SysAppSlow_iob2,
// Flash PROMs Interfaces
......@@ -94,7 +99,7 @@ module SystemFpga (
inout PllFmc1SDio_io,
input PllFmc1Sdo_i,
output PllFmc1Cs_on,
input PllFmc12SFpgaP_ik,
input PllFmc12SFpga_ik,
input PllFmc2Ld_i,
input PllFmc2Status_i,
input PllFmc2RefMon_i,
......@@ -107,7 +112,7 @@ module SystemFpga (
inout PllFmc2SDio_io,
input PllFmc2Sdo_i,
output PllFmc2Cs_on,
input PllFmc22SFpgaP_ik,
input PllFmc22SFpga_ik,
input PllSysLd_i,
input PllSysStatus_i,
input PllSysRefMon_i,
......@@ -120,7 +125,7 @@ module SystemFpga (
inout PllSysSDio_io,
input PllSysSdo_i,
output PllSysCs_on,
input PllSys2SFpgaP_ik,
input PllSys2SFpga_ik,
input PllDdsLd_i,
input PllDdsStatus_i,
input PllDdsRefMon_i,
......@@ -133,7 +138,7 @@ module SystemFpga (
inout PllDdsSDio_io,
input PllDdsSdo_i,
output PllDdsCs_on,
input PllDds2SFpgaP_ik,
input PllDds2SFpga_ik,
// PLL DAC
output PllDacSClk_ok,
output PllDacSynch_on,
......@@ -190,8 +195,12 @@ module SystemFpga (
output DdrCAS_o,
output DdrUDM_o,
output DdrLDM_o,
inout DdrLDQS_io,
inout DdrUDQS_io,
input DdrLDQS_i,
output DdrLDQS_o,
output DdrLDQSDir_o,
input DdrUDQS_i,
output DdrUDQS_o,
output DdrUDQSDir_o,
// Miscellaneaus
input [7:0] PcbRev_ib8,
// SFP Controls
......@@ -343,7 +352,10 @@ assign DdsSDio_io= 1'b0;
assign DdsIoReset_or= 1'b0;
assign DdsDrCtl_o= 1'b0;
assign DdsSyncIn_ok= 1'b0;
assign DdrUDQS_o = 1'b0;
assign DdrUDQSDir_o = 1'b1;
assign DdrLDQS_o = 1'b0;
assign DdrLDQSDir_o = 1'b1;
//####################################
// FP Leds
......@@ -427,6 +439,7 @@ assign VmeRetry_on = 1'b1;
assign VmeBerr_o = 1'b0;
assign VmeIrq_ob7 = ~VmeIrq_b7n;
assign VmeTdoOe_oe = 1'b0;
assign VmeTdo_o = 1'b0;
assign InterrupLevel = InterruptConfigReg_b32[30:28];
assign IntVector_b8 = InterruptConfigReg_b32[7:0];
......@@ -562,14 +575,16 @@ Slv2SerWB i_Slv2SerWB(
.Stb_i(StbSlv2SerWB),
.Dat_ob32(DatSlv2SerWBO_b32),
.Ack_o(AckSlv2SerWB),
.SerClk_ok(SysAppClk_o),
.SerClk_ok(SysAppClk_ok),
.SerDat_o(SysAppSlow_iob2[1]),
.SerCntrl_o(SysAppSlow_iob2[2]),
.Stb_o(AFpgaProgD_iob8[7]),
.SerClk_ik(AFpgaProgD_iob8[6]),
.SerClk_ik(SysAppClk_ik),
.SerDat_i(AFpgaProgD_iob8[5]),
.Ack_i(AFpgaProgD_iob8[4]));
assign AFpgaProgDone_io = 1'bz;
assign AFpgaProgProgram_o = 1'bz;
//#####################################
// SPI master
//#####################################
......@@ -668,19 +683,19 @@ assign PllStatusBits_b32[31:16] = 16'h0;
assign PllStatusBits_b32[15] = PllFmc1Ld_i;
assign PllStatusBits_b32[14] = PllFmc1Status_i;
assign PllStatusBits_b32[13] = PllFmc1RefMon_i;
assign PllStatusBits_b32[12] = PllFmc12SFpgaP_ik;
assign PllStatusBits_b32[12] = 1'b0;//PllFmc12SFpga_ik;
assign PllStatusBits_b32[11] = PllFmc2Ld_i;
assign PllStatusBits_b32[10] = PllFmc2Status_i;
assign PllStatusBits_b32[9] = PllFmc2RefMon_i;
assign PllStatusBits_b32[8] = PllFmc22SFpgaP_ik;
assign PllStatusBits_b32[8] = 1'b0;//PllFmc22SFpga_ik;
assign PllStatusBits_b32[7] = PllSysLd_i;
assign PllStatusBits_b32[6] = PllSysStatus_i;
assign PllStatusBits_b32[5] = PllSysRefMon_i;
assign PllStatusBits_b32[4] = PllSys2SFpgaP_ik;
assign PllStatusBits_b32[4] = 1'b0;//PllSys2SFpga_ik;
assign PllStatusBits_b32[3] = PllDdsLd_i;
assign PllStatusBits_b32[2] = PllDdsStatus_i;
assign PllStatusBits_b32[1] = PllDdsRefMon_i;
assign PllStatusBits_b32[0] = PllDds2SFpgaP_ik;
assign PllStatusBits_b32[0] = 1'b0;//PllDds2SFpga_ik;
assign PllFmc1Ref1_ok = Clk_k;
assign PllFmc2Ref1_ok = Clk_k;
......
trunk/hdl/design/VmeInterfaceWB.v
View file @ 23b1b4b5
......@@ -4,13 +4,13 @@ module VmeInterfaceWB(
input rst_i,
input clk_i,
output [21:0] adr_o,
output [31:0] dat_o,
output reg [21:0] adr_o,
output reg [31:0] dat_o,
input [31:0] dat_i,
output we_o,
output stb_o,
output reg we_o,
output reg stb_o,
input ack_i,
output cyc_o,
output reg cyc_o,
input UseGa_i,
input [4:0] ManualAddress_i,
......@@ -41,12 +41,6 @@ module VmeInterfaceWB(
parameter dly = 1;
reg [21:0] adr_o;
reg [31:0] dat_o;
reg we_o;
reg stb_o;
reg cyc_o;
reg oe_vme_data;
reg [1:0] ds1_shr, ds2_shr;
......@@ -243,4 +237,4 @@ end
endmodule
\ No newline at end of file
trunk/hdl/design/XilinxWrappers/SFpga.v
View file @ 23b1b4b5
`timescale 1ns/1ns
module VfcSFpga (
module SFpga (
input UseGa_i,
input [4:0] ManualAddress_ib5,
input [4:0] VmeGa_ib5n,
input VmeGaP_in,
output [7:1] VmeIrq_ob7,
inout [31:0] VmeD_iob32,
inout [31:0] VmeD_iob32,
output VmeDtAckOe_oe,
output VmeDtAck_on,
inout [31:1] VmeA_iob31,
......@@ -45,14 +43,16 @@ module VfcSFpga (
output FpGpIo1OutputMode_o,
output FpGpIo2OutputMode_o,
output FpGpIo34OutputMode_o,
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgClk_io,
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgDone_io,
inout AFpgaProgClk_io,
output AFpgaProgProgram_o,
inout [1:0] AFpgaProgM_iob2,
inout AFpgaProgCsi_io,
inout AFpgaProgRdWr_io,
inout AFpgaProgInit_io,
output SysAppClk_ok,
output SysAppClk_okn,
output SysAppClk_ok,
input SysAppClk_ik,
inout [2:1] SysAppSlow_iob2,
output FlashSFpgaD_o,
output FlashSFpgaClk_ok,
......@@ -83,8 +83,8 @@ module VfcSFpga (
inout PllFmc1SDio_io,
input PllFmc1Sdo_i,
output PllFmc1Cs_on,
input PllFmc12SFpgaP_ik,
input PllFmc12SFpgaP_ikn,
input PllFmc12SFpga_ik,
input PllFmc12SFpga_ikn,
input PllFmc2Ld_i,
input PllFmc2Status_i,
input PllFmc2RefMon_i,
......@@ -97,8 +97,8 @@ module VfcSFpga (
inout PllFmc2SDio_io,
input PllFmc2Sdo_i,
output PllFmc2Cs_on,
input PllFmc22SFpgaP_ik,
input PllFmc22SFpgaP_ikn,
input PllFmc22SFpga_ik,
input PllFmc22SFpga_ikn,
input PllSysLd_i,
input PllSysStatus_i,
input PllSysRefMon_i,
......@@ -112,8 +112,8 @@ module VfcSFpga (
inout PllSysSDio_io,
input PllSysSdo_i,
output PllSysCs_on,
input PllSys2SFpgaP_ik,
input PllSys2SFpgaP_ikn,
input PllSys2SFpga_ik,
input PllSys2SFpga_ikn,
input PllDdsLd_i,
input PllDdsStatus_i,
input PllDdsRefMon_i,
......@@ -126,8 +126,8 @@ module VfcSFpga (
inout PllDdsSDio_io,
input PllDdsSdo_i,
output PllDdsCs_on,
input PllDds2SFpgaP_ik,
input PllDds2SFpgaP_ikn,
input PllDds2SFpga_ik,
input PllDds2SFpga_ikn,
output PllDacSClk_ok,
output PllDacSynch_on,
output PllDacDin_o,
......@@ -170,6 +170,7 @@ module VfcSFpga (
output VmeP0LvdsBunchClkOut_o,
input VmeP0LvdsTClkIn_i,
output VmeP0LvdsTClkOut_o,
inout TempIdDQ_io,
output [13:0] DdrA_ob14,
output [2:0] DdrBA_ob3,
inout [15:0] DdrDQ_iob16,
......@@ -177,13 +178,16 @@ module VfcSFpga (
output DdrCkE_o,
output DdrWe_o,
output DdrCk_ok,
output DdrCk_okn,
output DdrODT_o,
output DdrRAS_o,
output DdrCAS_o,
output DdrUDM_o,
output DdrLDM_o,
inout DdrLDQS_io,
inout DdrLDQS_ion,
inout DdrUDQS_io,
inout DdrUDQS_ion,
input [7:0] PcbRev_ib8,
input WRModeDef0_i,
output WRModeDef1_i,
......@@ -206,7 +210,7 @@ module VfcSFpga (
inout Fmc1SDa_io,
output Fmc1SCl_ok,
inout Fmc2SDa_io,
output Fmc2SCl_ok,
output Fmc2SCl_ok/*,
output WRGBitOut_o,
input WRGbitIn_i,
input WRRefClk_ik,
......@@ -223,246 +227,265 @@ module VfcSFpga (
input Gbit3App2Sys_i,
output Gbit4Sys2App_o,
input Gbit4App2Sys_i,
input Gbit34RefClk_ik
input Gbit34RefClk_ik */
);
module SystemFpga (
// VME BUS SIGNALS
input UseGa_i,
input [4:0] ManualAddress_ib5,
input [4:0] VmeGa_ib5n,
input VmeGaP_in,
output [7:1] VmeIrq_ob7, // Active high because of the connection on the board
inout [31:0] VmeD_iob32,
output VmeDtAckOe_oe,
output VmeDtAck_on,
inout [31:1] VmeA_iob31,
inout VmeLword_io,
input [5:0] VmeAm_ib6,
input VmeAs_in,
input VmeSysClk_ik,
input VmeWrite_in,
output VmeDOeN_oen,
output VmeDDirVfcToVme_o,
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
input [2:1] VmeDs_inb2,
output VmeAOeN_oen,
output VmeADirVfcToVme_o,
output VmeRetryOe_oe,
output VmeRetry_on,
output VmeBerr_o, // Active high because of the connection on the board
input VmeSysReset_in,
input VmeTck_i,
input VmeTrst_i,
output VmeTdoOe_oe,
output VmeTdo_o,
input VmeTdi_i,
input VmeTms_i,
// CLOCKS
input VcTcXo_ik,
input Si57x_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
output Si57xSCl_ok,
inout Si57xSDa_io,
output Si57xOe_o,
// PUSH BUTTON
inout PushButton_ion,
// SWITCHES
input [1:0] Switch_ib2,
// Front Panel GPIO
output [7:0] FpLed_onb8,
// Front Panel GPIO
output FpGpIo1OutputMode_o,
output FpGpIo2OutputMode_o,
output FpGpIo34OutputMode_o,
// Application FPGA Programming Pins
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgClk_io,
inout [1:0] AFpgaProgM_iob2,
inout AFpgaProgCsi_io,
inout AFpgaProgRdWr_io,
inout AFpgaProgInit_io,
// Application FPGA Clk
output SysAppClk_ok/* synthesis xc_padtype = "OBUFG_LVDS" */,
// Application FPGA Slow Communication
inout [2:1] SysAppSlow_iob2,
// Flash PROMs Interfaces
output FlashSFpgaD_o,
output FlashSFpgaClk_ok,
output FlashSFpgaCs_on,
input FlashSFpgaQ_i,
output FlashAFpgaD_o,
output FlashAFpgaClk_ok,
output FlashAFpgaCs_on,
input FlashAFpgaQ_i,
// Voltage Monitoring ADC interface
output VAdcSClk_ok,
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_on,
// VAdj Control
output VAdjCs_on,
output VAdjSClk_ok,
output VAdjDin_o,
output VAdjInhibit_ozn,
output VAdjSpi_o,
// PLLs control
input PllFmc1Ld_i,
input PllFmc1Status_i,
input PllFmc1RefMon_i,
output PllFmc1RefSel_o,
output PllFmc1Ref1_ok,
output PllFmc1Pd_on,
output PllFmc1Synch_on,
output PllFmc1Reset_orn,
output PllFmc1SClk_ok,
inout PllFmc1SDio_io,
input PllFmc1Sdo_i,
output PllFmc1Cs_on,
input PllFmc12SFpgaP_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
input PllFmc2Ld_i,
input PllFmc2Status_i,
input PllFmc2RefMon_i,
output PllFmc2RefSel_o,
output PllFmc2Ref1_ok,
output PllFmc2Pd_on,
output PllFmc2Synch_on,
output PllFmc2Reset_orn,
output PllFmc2SClk_ok,
inout PllFmc2SDio_io,
input PllFmc2Sdo_i,
output PllFmc2Cs_on,
input PllFmc22SFpgaP_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
input PllSysLd_i,
input PllSysStatus_i,
input PllSysRefMon_i,
output PllSysRefSel_o,
output PllSysRef12_ok/* synthesis xc_padtype = "OBUFG_LVDS" */,
output PllSysPd_on,
output PllSysSynch_on,
output PllSysReset_orn,
output PllSysSClk_ok,
inout PllSysSDio_io,
input PllSysSdo_i,
output PllSysCs_on,
input PllSys2SFpgaP_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
input PllDdsLd_i,
input PllDdsStatus_i,
input PllDdsRefMon_i,
output PllDdsRefSel_o,
output PllDdsPd_on,
output PllDdsSynch_on,
output PllDdsReset_orn,
output PllDdsClk_ok,
output PllDdsSClk_ok,
inout PllDdsSDio_io,
input PllDdsSdo_i,
output PllDdsCs_on,
input PllDds2SFpgaP_ik/* synthesis xc_padtype = "OBUFG_LVDS" */,
// PLL DAC
output PllDacSClk_ok,
output PllDacSynch_on,
output PllDacDin_o,
input PllDacDout_i,
output PllDacClrn_orn,
output PllDacLDac_on,
// DDS
output [1:0] DdsF_ob2,
output [2:0] DdsProfile_ob3,
output [15:0] DdsD_ob16,
input DdsSyncSmpErr_i,
output DdsTxEnable_o,
output DdsMasterRst_or,
output DdsPowerDown_o,
input DdsPllLock_i,
inout DdsIOUpdate_io,
output DdsOsk_o,
output DdsDrHold_o,
output DdsSClk_o,
input DdsSDo_i,
output DdsSDio_io,
input DdsRamSwpOvr_i,
output DdsIoReset_or,
output DdsDrCtl_o,
input DdsDrOver_i,
input DdsSyncClk_ik,
input DdsPdClk_ik,
input DdsSyncOut_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
output DdsSyncIn_ok/* synthesis xc_padtype = "OBUFG_LVDS" */,
// VME P0
output VmeP0BuslineDir_o,
output VmeP0BuslineOe_o,
output VmeP0HwLowByteDir_o,
output VmeP0HwLowByteOe_o,
output VmeP0HwHighByteDir_o,
output VmeP0HwHighByteOe_o,
output VmeP0BunchSelectDir_o,
output VmeP0BunchSelectOe_o,
input VmeP0LvdsBunchClkIn_i,
output VmeP0LvdsBunchClkOut_o,
input VmeP0LvdsTClkIn_i,
output VmeP0LvdsTClkOut_o,
// DDR
output [13:0] DdrA_ob14,
output [2:0] DdrBA_ob3,
inout [15:0] DdrDQ_iob16,
output DdrReset_or,
output DdrCkE_o,
output DdrWe_o,
output DdrCk_ok,
output DdrODT_o,
output DdrRAS_o,
output DdrCAS_o,
output DdrUDM_o,
output DdrLDM_o,
inout DdrLDQS_io,
inout DdrUDQS_io,
// Miscellaneaus
input [7:0] PcbRev_ib8,
// SFP Controls
input WRModeDef0_i,
output WRModeDef1_i,
inout WRModeDef2_io,
output WRRateSelect_o,
output WRTxDisable_o,
input WRTxFault_i,
input WRLoS_i,
input Sfp2ModeDef0_i,
output Sfp2ModeDef1_i,
inout Sfp2ModeDef2_io,
output Sfp2RateSelect,
input Sfp2LoS_i,
output Sfp2TxDisable_o,
input Sfp2TxFault_i,
// FMC controls
output Fmc1PGC2M_in,
input Fmc1PrsntM2C_in,
output Fmc2PGC2M_in,
input Fmc2PrsntM2C_in,
inout Fmc1SDa_io,
output Fmc1SCl_ok,
inout Fmc2SDa_io,
output Fmc2SCl_ok,
// GBit signals
output WRGBitOut_o,
input WRGbitIn_i,
input WRRefClk_ik,
output Sfp2GBitOut_o,
input Sfp2GbitIn_i,
output SataTx_o,
input SataRx_i,
output Gbit1Sys2App_o,
input Gbit1App2Sys_i,
output Gbit2Sys2App_o,
input Gbit2App2Sys_i,
input Gbit12RefClk_ik,
output Gbit3Sys2App_o,
input Gbit3App2Sys_i,
output Gbit4Sys2App_o,
input Gbit4App2Sys_i,
input Gbit34RefClk_ik
);
SystemFpga i_Core(
.UseGa_i(UseGa_i),
.ManualAddress_ib5(ManualAddress_ib5),
.VmeGa_ib5n(VmeGa_ib5n),
.VmeGaP_in(VmeGaP_in),
.VmeIrq_ob7(VmeIrq_ob7),
.VmeD_iob32(VmeD_iob32),
.VmeDtAckOe_oe(VmeDtAckOe_oe),
.VmeDtAck_on(VmeDtAck_on),
.VmeA_iob31(VmeA_iob31),
.VmeLword_io(VmeLword_io),
.VmeAm_ib6(VmeAm_ib6),
.VmeAs_in(VmeAs_in),
.VmeSysClk_ik(VmeSysClk_ik),
.VmeWrite_in(VmeWrite_in),
.VmeDOeN_oen(VmeDOeN_oen),
.VmeDDirVfcToVme_o(VmeDDirVfcToVme_o),
.VmeIack_in(VmeIack_in),
.VmeIackIn_in(VmeIackIn_in),
.VmeIackOut_on(VmeIackOut_on),
.VmeDs_inb2(VmeDs_i),
.VmeAOeN_oen(VmeAOeN_oen),
.VmeADirVfcToVme_o(VmeADirVfcToVme_o),
.VmeRetryOe_oe(VmeRetryOe_oe),
.VmeRetry_on(VmeRetry_on),
.VmeBerr_o(VmeBerr_o),
.VmeSysReset_in(VmeSysReset_in),
.VmeTck_i(VmeTck_i),
.VmeTrst_i(VmeTrst_i),
.VmeTdoOe_oe(VmeTdoOe_oe),
.VmeTdo_o(VmeTdo_o),
.VmeTdi_i(VmeTdi_i),
.VmeTms_i(VmeTms_i),
.VcTcXo_ik(VcTcXo_ik),
.Si57x_ik(Si57x),
.Si57xSCl_ok(Si57xSCl_ok),
.Si57xSDa_io(Si57xSDa_io),
.Si57xOe_o(Si57xOe_o),
.PushButton_ion(PushButton_ion),
.Switch_ib2(Switch_ib2),
.TempIdDQ_io(TempIdDQ_io),
.FpLed_onb8(FpLed_onb8),
.FpGpIo1OutputMode_o(FpGpIo1OutputMode_o),
.FpGpIo2OutputMode_o(FpGpIo2OutputMode_o),
.FpGpIo34OutputMode_o(FpGpIo34OutputMode_o),
.AFpgaProgD_iob8(AFpgaProgD_iob8),
.AFpgaProgDone_io(AFpgaProgDone_io),
.AFpgaProgProgram_o(AFpgaProgProgram_o),
.AFpgaProgClk_io(AFpgaProgClk_io),
.AFpgaProgM_iob2(AFpgaProgM_iob2),
.AFpgaProgCsi_io(AFpgaProgCsi_io),
.AFpgaProgRdWr_io(AFpgaProgRdWr_io),
.AFpgaProgInit_io(AFpgaProgInit_io),
.SysAppClk_ok(SysAppClk_ok),
.SysAppClk_ik(SysAppClk_ik),
.SysAppSlow_iob2(SysAppSlow_iob2),
.FlashSFpgaD_o(FlashSFpgaD_o),
.FlashSFpgaClk_ok(FlashSFpgaClk_ok),
.FlashSFpgaCs_on(FlashSFpgaCs_on),
.FlashSFpgaQ_i(FlashSFpgaQ_i),
.FlashAFpgaD_o(FlashAFpgaD_o),
.FlashAFpgaClk_ok(FlashAFpgaClk_ok),
.FlashAFpgaCs_on(FlashAFpgaCs_on),
.FlashAFpgaQ_i(FlashAFpgaQ_i),
.VAdcSClk_ok(VAdcSClk_ok),
.VAdcDout_i(VAdcDout_i),
.VAdcDin_o(VAdcDin_o),
.VAdcCs_on(VAdcCs_on),
.VAdjCs_on(VAdjCs_on),
.VAdjSClk_ok(VAdjSClk_ok),
.VAdjDin_o(VAdjDin_o),
.VAdjInhibit_ozn(VAdjInhibit_ozn),
.VAdjSpi_o(VAdjSpi_o),
.PllFmc1Ld_i(PllFmc1Ld_i),
.PllFmc1Status_i(PllFmc1Status_i),
.PllFmc1RefMon_i(PllFmc1RefMon_i),
.PllFmc1RefSel_o(PllFmc1RefSel_o),
.PllFmc1Ref1_ok(PllFmc1Ref1_ok),
.PllFmc1Pd_on(PllFmc1Pd_on),
.PllFmc1Synch_on(PllFmc1Synch_on),
.PllFmc1Reset_orn(PllFmc1Reset_orn),
.PllFmc1SClk_ok(PllFmc1SClk_ok),
.PllFmc1SDio_io(PllFmc1SDio_io),
.PllFmc1Sdo_i(PllFmc1Sdo_i),
.PllFmc1Cs_on(PllFmc1Cs_on),
.PllFmc12SFpga_ik(PllFmc12SFpga),
.PllFmc2Ld_i(PllFmc2Ld_i),
.PllFmc2Status_i(PllFmc2Status_i),
.PllFmc2RefMon_i(PllFmc2RefMon_i),
.PllFmc2RefSel_o(PllFmc2RefSel_o),
.PllFmc2Ref1_ok(PllFmc2Ref1_ok),
.PllFmc2Pd_on(PllFmc2Pd_on),
.PllFmc2Synch_on(PllFmc2Synch_on),
.PllFmc2Reset_orn(PllFmc2Reset_orn),
.PllFmc2SClk_ok(PllFmc2SClk_ok),
.PllFmc2SDio_io(PllFmc2SDio_io),
.PllFmc2Sdo_i(PllFmc2Sdo_i),
.PllFmc2Cs_on(PllFmc2Cs_on),
.PllFmc22SFpga_ik(PllFmc22SFpga),
.PllSysLd_i(PllSysLd_i),
.PllSysStatus_i(PllSysStatus_i),
.PllSysRefMon_i(PllSysRefMon_i),
.PllSysRefSel_o(PllSysRefSel_o),
.PllSysRef12_ok(PllSysRef12),
.PllSysPd_on(PllSysPd_on),
.PllSysSynch_on(PllSysSynch_on),
.PllSysReset_orn(PllSysReset_orn),
.PllSysSClk_ok(PllSysSClk_ok),
.PllSysSDio_io(PllSysSDio_io),
.PllSysSdo_i(PllSysSdo_i),
.PllSysCs_on(PllSysCs_on),
.PllSys2SFpga_ik(PllSys2SFpga),
.PllDdsLd_i(PllDdsLd_i),
.PllDdsStatus_i(PllDdsStatus_i),
.PllDdsRefMon_i(PllDdsRefMon_i),
.PllDdsRefSel_o(PllDdsRefSel_o),
.PllDdsPd_on(PllDdsPd_on),
.PllDdsSynch_on(PllDdsSynch_on),
.PllDdsReset_orn(PllDdsReset_orn),
.PllDdsClk_ok(PllDdsClk_ok),
.PllDdsSClk_ok(PllDdsSClk_ok),
.PllDdsSDio_io(PllDdsSDio_io),
.PllDdsSdo_i(PllDdsSdo_i),
.PllDdsCs_on(PllDdsCs_on),
.PllDds2SFpga_ik(PllDds2SFpga),
.PllDacSClk_ok(PllDacSClk_ok),
.PllDacSynch_on(PllDacSynch_on),
.PllDacDin_o(PllDacDin_o),
.PllDacDout_i(PllDacDout_i),
.PllDacClrn_orn(PllDacClrn_orn),
.PllDacLDac_on(PllDacLDac_on),
.DdsF_ob2(DdsF_ob2),
.DdsProfile_ob3(DdsProfile_ob3),
.DdsD_ob16(DdsD_ob16),
.DdsSyncSmpErr_i(DdsSyncSmpErr_i),
.DdsTxEnable_o(DdsTxEnable_o),
.DdsMasterRst_or(DdsMasterRst_or),
.DdsPowerDown_o(DdsPowerDown_o),
.DdsPllLock_i(DdsPllLock_i),
.DdsIOUpdate_io(DdsIOUpdate_io),
.DdsOsk_o(DdsOsk_o),
.DdsDrHold_o(DdsDrHold_o),
.DdsSClk_o(DdsSClk_o),
.DdsSDo_i(DdsSDo_i),
.DdsSDio_io(DdsSDio_io),
.DdsRamSwpOvr_i(DdsRamSwpOvr_i),
.DdsIoReset_or(DdsIoReset_or),
.DdsDrCtl_o(DdsDrCtl_o),
.DdsDrOver_i(DdsDrOver_i),
.DdsSyncClk_ik(DdsSyncClk_ik),
.DdsPdClk_ik(DdsPdClk_ik),
.DdsSyncOut_ik(DdsSyncOut),
.DdsSyncIn_ok(DdsSyncIn),
.VmeP0BuslineDir_o(VmeP0BuslineDir_o),
.VmeP0BuslineOe_o(VmeP0BuslineOe_o),
.VmeP0HwLowByteDir_o(VmeP0HwLowByteDir_o),
.VmeP0HwLowByteOe_o(VmeP0HwLowByteOe_o),
.VmeP0HwHighByteDir_o(VmeP0HwHighByteDir_o),
.VmeP0HwHighByteOe_o(VmeP0HwHighByteOe_o),
.VmeP0BunchSelectDir_o(VmeP0BunchSelectDir_o),
.VmeP0BunchSelectOe_o(VmeP0BunchSelectOe_o),
.VmeP0LvdsBunchClkIn_i(VmeP0LvdsBunchClkIn_i),
.VmeP0LvdsBunchClkOut_o(VmeP0LvdsBunchClkOut_o),
.VmeP0LvdsTClkIn_i(VmeP0LvdsTClkIn_i),
.VmeP0LvdsTClkOut_o(VmeP0LvdsTClkOut_o),
.DdrA_ob14(DdrA_ob14),
.DdrBA_ob3(DdrBA_ob3),
.DdrDQ_iob16(DdrDQ_iob16),
.DdrReset_or(DdrReset_or),
.DdrCkE_o(DdrCkE_o),
.DdrWe_o(DdrWe_o),
.DdrCk_ok(DdrCk),
.DdrODT_o(DdrODT_o),
.DdrRAS_o(DdrRAS_o),
.DdrCAS_o(DdrCAS_o),
.DdrUDM_o(DdrUDM_o),
.DdrLDM_o(DdrLDM_o),
.DdrLDQS_i(DdrLDQS_i),
.DdrLDQS_o(DdrLDQS_o),
.DdrLDQSDir_o(DdrLDQSDir_o),
.DdrUDQS_i(DdrUDQS_i),
.DdrUDQS_o(DdrUDQS_o),
.DdrUDQSDir_o(DdrUDQSDir_o),
.PcbRev_ib8(PcbRev_ib8),
.WRModeDef0_i(WRModeDef0_i),
.WRModeDef1_i(WRModeDef1_i),
.WRModeDef2_io(WRModeDef2_io),
.WRRateSelect_o(WRRateSelect_o),
.WRTxDisable_o(WRTxDisable_o),
.WRTxFault_i(WRTxFault_i),
.WRLoS_i(WRLoS_i),
.Sfp2ModeDef0_i(Sfp2ModeDef0_i),
.Sfp2ModeDef1_i(Sfp2ModeDef1_i),
.Sfp2ModeDef2_io(Sfp2ModeDef2_io),
.Sfp2RateSelect(Sfp2RateSelect),
.Sfp2LoS_i(Sfp2LoS_i),
.Sfp2TxDisable_o(Sfp2TxDisable_o),
.Sfp2TxFault_i(Sfp2TxFault_i),
.Fmc1PGC2M_in(Fmc1PGC2M_in),
.Fmc1PrsntM2C_in(Fmc1PrsntM2C_in),
.Fmc2PGC2M_in(Fmc2PGC2M_in),
.Fmc2PrsntM2C_in(Fmc2PrsntM2C_in),
.Fmc1SDa_io(Fmc1SDa_io),
.Fmc1SCl_ok(Fmc1SCl_ok),
.Fmc2SDa_io(Fmc2SDa_io),
.Fmc2SCl_ok(Fmc2SCl_ok),
.WRGBitOut_o(WRGBitOut_o),
.WRGbitIn_i(WRGbitIn_i),
.WRRefClk_ik(WRRefClk_ik),
.Sfp2GBitOut_o(Sfp2GBitOut_o),
.Sfp2GbitIn_i(Sfp2GbitIn_i),
.SataTx_o(SataTx_o),
.SataRx_i(SataRx_i),
.Gbit1Sys2App_o(Gbit1Sys2App_o),
.Gbit1App2Sys_i(Gbit1App2Sys_i),
.Gbit2Sys2App_o(Gbit2Sys2App_o),
.Gbit2App2Sys_i(Gbit2App2Sys_i),
.Gbit12RefClk_ik(Gbit12RefClk_ik),
.Gbit3Sys2App_o(Gbit3Sys2App_o),
.Gbit3App2Sys_i(Gbit3App2Sys_i),
.Gbit4Sys2App_o(Gbit4Sys2App_o),
.Gbit4App2Sys_i(Gbit4App2Sys_i),
.Gbit34RefClk_ik(Gbit34RefClk_ik));
IBUFGDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT"))
i_Si57x_ik (.O(Si57x), .I(Si57x_ik), .IB(Si57x_ikn));
IBUFGDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT"))
i_PllFmc12SFpga_ik (.O(PllFmc12SFpga), .I(PllFmc12SFpga_ik), .IB(PllFmc12SFpga_ikn));
IBUFGDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT"))
i_PllFmc22SFpga_ik (.O(PllFmc22SFpga), .I(PllFmc22SFpga_ik), .IB(PllFmc22SFpga_ikn));
IBUFGDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT"))
i_PllSys2SFpga_ik (.O(PllSys2SFpga), .I(PllSys2SFpga_ik), .IB(PllSys2SFpga_ikn));
IBUFGDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT"))
i_DdsSyncOut_ik (.O(DdsSyncOut), .I(DdsSyncOut_ik), .IB(DdsSyncOut_ikn));
IBUFGDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT"))
i_PllDds2SFpga_ik (.O(PllDds2SFpga), .I(PllDds2SFpga_ik), .IB(PllDds2SFpga_ikn));
OBUFDS #(.IOSTANDARD("DEFAULT"))
i_DdsSyncIn_ok (.O(DdsSyncIn_ok), .OB(DdsSyncIn_okn), .I(DdsSyncIn));
OBUFDS #(.IOSTANDARD("DEFAULT"))
i_PllSysRef12_ok (.O(PllSysRef12_ok), .OB(PllSysRef12_okn), .I(PllSysRef12));
OBUFDS #(.IOSTANDARD("DEFAULT"))
i_DdrCk_ok (.O(DdrCk_ok), .OB(DdrCk_okn), .I(DdrCk));
IOBUFDS #(.IOSTANDARD("DEFAULT"))
i_DdrLDQS_io (.O(DdrLDQS_i), .IO(DdrLDQS_io), .IOB(DdrLDQS_ion), .I(DdrLDQS_o), .T(DdrLDQSDir_o));
IOBUFDS #(.IOSTANDARD("DEFAULT"))
i_DdrUDQS_io (.O(DdrUDQS_i), .IO(DdrUDQS_io), .IOB(DdrUDQS_ion), .I(DdrUDQS_o), .T(DdrUDQSDir_o));
endmodule
trunk/hdl/schematic/VFCBoard.v
View file @ 23b1b4b5
......@@ -343,7 +343,7 @@ wire [1:0] a_Switch_b2 = i_Sw1_b8[8:7];
wire a_UseGa = i_Sw1_b8[6];
wire [4:0] a_NoGa_b5 = i_Sw1_b8[5:1];
wire SysAppClk;
wire Sys2AppClk, App2SysClk;
wire [2:1] SysAppSlow_b2;
wire [7:0] AFpgaProgD_b8;
wire AFpgaProgClk;
......@@ -401,7 +401,8 @@ SystemFpga i_SystemFpga(
.FpGpIo2OutputMode_o(FpGpIo2OutputMode),
.FpGpIo34OutputMode_o(FpGpIo34OutputMode),
.SysAppClk_o(SysAppClk),
.SysAppClk_ok(Sys2AppClk),
.SysAppClk_ik(App2SysClk),
.SysAppSlow_iob2(SysAppSlow_b2),
.AFpgaProgD_iob8(AFpgaProgD_b8),
......@@ -444,7 +445,7 @@ SystemFpga i_SystemFpga(
.PllFmc1SDio_io(),
.PllFmc1Sdo_i(),
.PllFmc1Cs_on(),
.PllFmc12SFpgaP_ik(),
.PllFmc12SFpga_ik(),
.PllFmc2Ld_i(),
.PllFmc2Status_i(),
......@@ -458,7 +459,7 @@ SystemFpga i_SystemFpga(
.PllFmc2SDio_io(),
.PllFmc2Sdo_i(),
.PllFmc2Cs_on(),
.PllFmc22SFpgaP_ik(),
.PllFmc22SFpga_ik(),
.PllSysLd_i(),
.PllSysStatus_i(),
......@@ -472,7 +473,7 @@ SystemFpga i_SystemFpga(
.PllSysSDio_io(),
.PllSysSdo_i(),
.PllSysCs_on(),
.PllSys2SFpgaP_ik(),
.PllSys2SFpga_ik(),
.PllDdsLd_i(),
.PllDdsStatus_i(),
......@@ -486,7 +487,7 @@ SystemFpga i_SystemFpga(
.PllDdsSDio_io(),
.PllDdsSdo_i(),
.PllDdsCs_on(),
.PllDds2SFpgaP_ik(),
.PllDds2SFpga_ik(),
.PllDacSClk_ok(),
.PllDacSynch_on(),
......@@ -503,7 +504,8 @@ SystemFpga i_SystemFpga(
ApplicationFpga i_ApplicationFpga(
.SysAppClk_i(SysAppClk),
.SysAppClk_ik(Sys2AppClk),
.SysAppClk_ok(App2SysClk),
.SysAppSlow_iob2(SysAppSlow_b2),
.AFpgaProgD_iob8(AFpgaProgD_b8),
......
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