Commit 265c6bd0 authored by Andrea Boccardi's avatar Andrea Boccardi

added a doc, recompiled the system FPGA

parent cd70b752
This diff is collapsed.
......@@ -15,8 +15,8 @@ Checking Constraint Associations...
Done...
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N450' has no driver
WARNING:NgdBuild:452 - logical net 'N452' has no driver
WARNING:NgdBuild:452 - logical net 'N456' has no driver
WARNING:NgdBuild:452 - logical net 'N458' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
......@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary:
Total memory usage is 155980 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 4 sec
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"...
......@@ -75,3 +75,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010
Mon Dec 20 08:27:29 2010
# NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Fri Dec 17 11:12:22 2010
PCBE13225:: Mon Dec 20 08:26:58 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -21,38 +21,38 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 812
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 573
Number using O5 output only: 172
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 4
Number used as Single Port RAM: 0
Number used as Shift Register: 3
Number using O6 output only: 3
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 32
Number with same-slice register load: 23
Number used exclusively as route-thrus: 30
Number with same-slice register load: 21
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 5227 unrouted; REAL time: 12 secs
Phase 1 : 5256 unrouted; REAL time: 11 secs
Phase 2 : 4601 unrouted; REAL time: 15 secs
Phase 2 : 4603 unrouted; REAL time: 15 secs
Phase 3 : 1750 unrouted; REAL time: 21 secs
Phase 3 : 1808 unrouted; REAL time: 20 secs
Phase 4 : 1750 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Phase 4 : 1808 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 30 secs
Total REAL time to Router completion: 30 secs
Total CPU time to Router completion: 29 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Total REAL time to Router completion: 29 secs
Total CPU time to Router completion: 28 secs
Partition Implementation Status
-------------------------------
......@@ -192,18 +192,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 229 | 0.260 | 1.710 |
| Si57x_BUFG | BUFGMUX_X2Y4| No | 220 | 0.242 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.009 | 1.640 |
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.008 | 1.643 |
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.186 | 1.693 |
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.189 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 223 | 0.000 | 7.868 |
| i_Core/Rst_rq | Local| | 211 | 0.000 | 3.873 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.686 |
| e/stb_o | Local| | 19 | 0.000 | 4.113 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.435ns| 7.898ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.429ns| 7.904ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.225ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.464ns| 3.869ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.442ns| | 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.826ns| 3.507ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.468ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -237,10 +237,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 32 secs
Total CPU time to PAR completion: 32 secs
Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 31 secs
Peak Memory Usage: 546 MB
Peak Memory Usage: 545 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
//! **************************************************************************
// Written by: Map M.70d on Fri Dec 17 11:12:18 2010
// Written by: Map M.70d on Mon Dec 20 08:26:52 2010
//! **************************************************************************
SCHEMATIC START;
......@@ -333,7 +333,8 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
......@@ -435,6 +436,12 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_24" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_19" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_18" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_17" BEL
......@@ -455,9 +462,13 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_2" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_1" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_ClearMonostable/Counter_c_25" BEL
"i_Core/i_ClearMonostable/Counter_c_24" BEL
"i_Core/i_ClearMonostable/Counter_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_22" BEL
"i_Core/i_ClearMonostable/Counter_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_20" BEL
"i_Core/i_ClearMonostable/Counter_c_19" BEL
"i_Core/i_ClearMonostable/Counter_c_18" BEL
"i_Core/i_ClearMonostable/Counter_c_17" BEL
......@@ -478,9 +489,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_2" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_2" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_1" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL
......@@ -959,11 +968,15 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "i_Core/Mshreg_VmeSysReset_dx_1"
BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL "PllSysRef12_ok" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
......
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.435" best="7.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.464" best="3.869" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.442" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.429" best="7.904" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.225" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.826" best="3.507" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.468" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010
Mon Dec 20 08:27:29 2010
All signals are completely routed.
......
......@@ -22,10 +22,10 @@
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
</tr>
<tr>
<td>XILINX</td>
......
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 11:11:25 2010
Mapped Date : Mon Dec 20 08:25:44 2010
Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
......@@ -89,20 +89,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 16 secs
Total CPU time at the beginning of Placer: 12 secs
Total REAL time at the beginning of Placer: 30 secs
Total CPU time at the beginning of Placer: 13 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:fbd9bf1c) REAL time: 21 secs
Phase 1.1 Initial Placement Analysis (Checksum:ee27935a) REAL time: 36 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:fbd9bf1c) REAL time: 22 secs
Phase 2.7 Design Feasibility Check (Checksum:ee27935a) REAL time: 36 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:fbd9bf1c) REAL time: 22 secs
Phase 3.31 Local Placement Optimization (Checksum:ee27935a) REAL time: 36 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
......@@ -120,42 +120,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:b9a90c54) REAL time: 29 secs
(Checksum:d3736e22) REAL time: 44 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:b9a90c54) REAL time: 29 secs
Phase 5.36 Local Placement Optimization (Checksum:d3736e22) REAL time: 44 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:b9a90c54) REAL time: 29 secs
Phase 6.30 Global Clock Region Assignment (Checksum:d3736e22) REAL time: 44 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:5a4374ed) REAL time: 30 secs
Phase 7.3 Local Placement Optimization (Checksum:d47075b5) REAL time: 45 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b9b9c566) REAL time: 30 secs
Phase 8.5 Local Placement Optimization (Checksum:d384eabe) REAL time: 45 secs
Phase 9.8 Global Placement
...
........
.......................
................
......
Phase 9.8 Global Placement (Checksum:94595592) REAL time: 36 secs
.....................................
....
Phase 9.8 Global Placement (Checksum:7253f7a8) REAL time: 52 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:94595592) REAL time: 36 secs
Phase 10.5 Local Placement Optimization (Checksum:7253f7a8) REAL time: 52 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:df505277) REAL time: 47 secs
Phase 11.18 Placement Optimization (Checksum:85580283) REAL time: 1 mins 2 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:df505277) REAL time: 47 secs
Phase 12.5 Local Placement Optimization (Checksum:85580283) REAL time: 1 mins 2 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:967c17e4) REAL time: 47 secs
Phase 13.34 Placement Validation (Checksum:8244a4e2) REAL time: 1 mins 3 secs
Total REAL time to Placer completion: 52 secs
Total CPU time to Placer completion: 47 secs
Total REAL time to Placer completion: 1 mins 7 secs
Total CPU time to Placer completion: 48 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
......@@ -261,41 +261,41 @@ Design Summary:
Number of errors: 0
Number of warnings: 83
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 812
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 573
Number using O5 output only: 172
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 4
Number used as Single Port RAM: 0
Number used as Shift Register: 3
Number using O6 output only: 3
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 32
Number with same-slice register load: 23
Number used exclusively as route-thrus: 30
Number with same-slice register load: 21
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of unique control sets: 32
Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1%
to control set restrictions: 83 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -336,11 +336,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02
Average Fanout of Non-Clock Nets: 3.01
Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 54 secs
Total CPU time to MAP completion: 49 secs
Peak Memory Usage: 630 MB
Total REAL time to MAP completion: 1 mins 10 secs
Total CPU time to MAP completion: 50 secs
Mapping completed.
See MAP report file "SFpga_map.mrp" for details.
......@@ -10,48 +10,48 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 11:11:25 2010
Mapped Date : Mon Dec 20 08:25:44 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 83
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 812
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 573
Number using O5 output only: 172
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 4
Number used as Single Port RAM: 0
Number used as Shift Register: 3
Number using O6 output only: 3
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 32
Number with same-slice register load: 23
Number used exclusively as route-thrus: 30
Number with same-slice register load: 21
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of unique control sets: 32
Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1%
to control set restrictions: 83 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02
Average Fanout of Non-Clock Nets: 3.01
Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 54 secs
Total CPU time to MAP completion: 49 secs
Peak Memory Usage: 630 MB
Total REAL time to MAP completion: 1 mins 10 secs
Total CPU time to MAP completion: 50 secs
Table of Contents
-----------------
......@@ -299,10 +299,10 @@ WARNING:PhysDesignRules:367 - The signal
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network N450 has no load.
INFO:LIT:243 - Logical network N456 has no load.
INFO:LIT:395 - The above info message is repeated 51 more times for the
following (max. 5 shown):
N452,
N458,
VmeAm_ib6<2>_IBUF,
VmeAm_ib6<1>_IBUF,
VmeDs_inb2<2>_IBUF,
......
......@@ -5,14 +5,14 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Fri Dec 17 11:12:20 2010">
<application stringID="Map" timeStamp="Mon Dec 20 08:26:54 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
......@@ -64,15 +64,15 @@
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/>
</section>
<task stringID="MAP_PACK_REPORT">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="796">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="796"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="812">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="812"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="911">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="154"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="571"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="933">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="172"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="573"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="166"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
......@@ -84,7 +84,7 @@
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="3"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="5"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
......@@ -116,20 +116,20 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="644084"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="54 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="49 secs "/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="645556"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="1 mins 10 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="50 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="796">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="796"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="812">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="812"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="934">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="154"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="571"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="954">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="172"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="573"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="166"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
......@@ -141,24 +141,24 @@
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="3"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="5"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="23"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="21"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="23"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="21"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="374">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="70"/>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="365">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="84"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="300"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="277"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1101">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="386"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="167"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="548"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1098">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="364"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="144"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="590"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
......
......@@ -5,14 +5,14 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Fri Dec 17 11:11:22 2010">
<application stringID="NgdBuild" timeStamp="Mon Dec 20 08:25:40 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
......@@ -68,11 +68,11 @@
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="189"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="99"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="191"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="101"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="313"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="325"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
......@@ -81,30 +81,30 @@
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="163"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="163"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="121"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="112"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="181"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="166"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="113"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="146"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="299"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="204"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="181"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="199"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="189"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="99"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="191"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="101"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="313"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="325"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
......@@ -113,23 +113,23 @@
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="163"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="163"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="121"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="112"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="181"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="166"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="113"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="146"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="299"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="204"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="181"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="199"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
......
#Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Fri Dec 17 11:12:54 2010
#Mon Dec 20 08:27:29 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010
Mon Dec 20 08:27:29 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......
......@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="15">
<DesignSummary rev="17">
<CmdHistory>
</CmdHistory>
</DesignSummary>
......@@ -107,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292580677" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292580654">
<transform xil_pn:end_ts="1292829931" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292829909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -129,7 +129,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292580684" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292580677">
<transform xil_pn:end_ts="1292829942" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292829931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -139,7 +139,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292580741" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292580684">
<transform xil_pn:end_ts="1292830015" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292829942">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -155,7 +155,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292580788" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292580741">
<transform xil_pn:end_ts="1292830063" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292830015">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -170,10 +170,11 @@
<outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292580816" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292580788">
<transform xil_pn:end_ts="1292830091" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292830063">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<outfile xil_pn:name="SFpga.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="sfpga.bgn"/>
......@@ -183,9 +184,10 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1292580983" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292580980">
<transform xil_pn:end_ts="1292832753" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292832751">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570">
<status xil_pn:value="SuccessfullyRun"/>
......@@ -197,7 +199,7 @@
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1292580788" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292580776">
<transform xil_pn:end_ts="1292830063" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292830051">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/>
......
......@@ -97,11 +97,11 @@
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
......
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292580676
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292829930
OK
......@@ -5,11 +5,11 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N450</arg> has no load.
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">N456</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">51</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N452,
<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">51</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N458,
VmeAm_ib6&lt;2&gt;_IBUF,
VmeAm_ib6&lt;1&gt;_IBUF,
VmeDs_inb2&lt;2&gt;_IBUF,
......@@ -137,7 +137,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Place" num="834" delta="new" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">330</arg> IOs, <arg fmt="%d" index="2">328</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
<msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">330</arg> IOs, <arg fmt="%d" index="2">328</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg>
<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
......
......@@ -5,10 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N450</arg>&apos; has no driver
<msg type="warning" file="NgdBuild" num="452" delta="new" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N456</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N452</arg>&apos; has no driver
<msg type="warning" file="NgdBuild" num="452" delta="new" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N458</arg>&apos; has no driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;1&gt;</arg>&apos; has no legal driver
......
......@@ -8,8 +8,38 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/AddrDecoderWBSys.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Debouncer.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4InputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/InterruptManagerWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Monostable.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Slv2SerWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SpiMasterWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/VmeInterfaceWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v\&quot; into library work</arg>
</msg>
</messages>
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2010-12-17T11:09:45</DateModified>
<DateModified>2010-12-20T09:27:08</DateModified>
<ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......
......@@ -64,13 +64,13 @@
<ClosedNode>Implement Design/Translate</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Generate Target PROM/ACE File</SelectedItem>
<SelectedItem>Generate Programming File</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >14</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Target PROM/ACE File</CurrentItem>
<CurrentItem>Generate Programming File</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
......
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1486</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4740</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4740</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4274</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1498</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4733</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4733</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4267</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>15.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>21.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>29.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>16.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>15.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>28.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>15.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>8.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0984</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0983</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
......@@ -5,7 +5,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf.
Fri Dec 17 11:13:13 2010
Mon Dec 20 08:27:48 2010
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
......
Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:13:13 2010
Mon Dec 20 08:27:48 2010
drc -z SFpga.ncd SFpga.pcf
......
......@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=6
ProjectIteration=7
WebTalk Summary
----------------
......@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-17T11:13:36. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-20T08:28:11. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Dec 17 11:13:08 2010">
<application name="pn" timeStamp="Mon Dec 20 08:27:43 2010">
<section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="6" type="project"/>
<property name="ProjectIteration" value="7" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section>
......@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="6" type="process"/>
<property name="PROP_intWbtProjectIteration" value="7" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
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