Commit 265c6bd0 authored by Andrea Boccardi's avatar Andrea Boccardi

added a doc, recompiled the system FPGA

parent cd70b752
......@@ -15,8 +15,8 @@ Checking Constraint Associations...
Done...
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N450' has no driver
WARNING:NgdBuild:452 - logical net 'N452' has no driver
WARNING:NgdBuild:452 - logical net 'N456' has no driver
WARNING:NgdBuild:452 - logical net 'N458' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
......@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary:
Total memory usage is 155980 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 4 sec
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"...
......@@ -75,3 +75,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
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Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010
Mon Dec 20 08:27:29 2010
# NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Fri Dec 17 11:12:22 2010
PCBE13225:: Mon Dec 20 08:26:58 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -21,38 +21,38 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 812
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 573
Number using O5 output only: 172
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 4
Number used as Single Port RAM: 0
Number used as Shift Register: 3
Number using O6 output only: 3
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 32
Number with same-slice register load: 23
Number used exclusively as route-thrus: 30
Number with same-slice register load: 21
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 5227 unrouted; REAL time: 12 secs
Phase 1 : 5256 unrouted; REAL time: 11 secs
Phase 2 : 4601 unrouted; REAL time: 15 secs
Phase 2 : 4603 unrouted; REAL time: 15 secs
Phase 3 : 1750 unrouted; REAL time: 21 secs
Phase 3 : 1808 unrouted; REAL time: 20 secs
Phase 4 : 1750 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Phase 4 : 1808 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 30 secs
Total REAL time to Router completion: 30 secs
Total CPU time to Router completion: 29 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Total REAL time to Router completion: 29 secs
Total CPU time to Router completion: 28 secs
Partition Implementation Status
-------------------------------
......@@ -192,18 +192,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 229 | 0.260 | 1.710 |
| Si57x_BUFG | BUFGMUX_X2Y4| No | 220 | 0.242 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.009 | 1.640 |
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.008 | 1.643 |
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.186 | 1.693 |
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.189 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 223 | 0.000 | 7.868 |
| i_Core/Rst_rq | Local| | 211 | 0.000 | 3.873 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.686 |
| e/stb_o | Local| | 19 | 0.000 | 4.113 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.435ns| 7.898ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.429ns| 7.904ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.225ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.464ns| 3.869ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.442ns| | 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.826ns| 3.507ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.468ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -237,10 +237,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 32 secs
Total CPU time to PAR completion: 32 secs
Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 31 secs
Peak Memory Usage: 546 MB
Peak Memory Usage: 545 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
//! **************************************************************************
// Written by: Map M.70d on Fri Dec 17 11:12:18 2010
// Written by: Map M.70d on Mon Dec 20 08:26:52 2010
//! **************************************************************************
SCHEMATIC START;
......@@ -333,7 +333,8 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
......@@ -435,6 +436,12 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_24" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_19" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_18" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_17" BEL
......@@ -455,9 +462,13 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_2" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_1" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_ClearMonostable/Counter_c_25" BEL
"i_Core/i_ClearMonostable/Counter_c_24" BEL
"i_Core/i_ClearMonostable/Counter_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_22" BEL
"i_Core/i_ClearMonostable/Counter_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_20" BEL
"i_Core/i_ClearMonostable/Counter_c_19" BEL
"i_Core/i_ClearMonostable/Counter_c_18" BEL
"i_Core/i_ClearMonostable/Counter_c_17" BEL
......@@ -478,9 +489,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_2" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_2" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_1" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL
......@@ -959,11 +968,15 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "i_Core/Mshreg_VmeSysReset_dx_1"
BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL "PllSysRef12_ok" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
......
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.435" best="7.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.464" best="3.869" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.442" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.429" best="7.904" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.225" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.826" best="3.507" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.468" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
......@@ -4,13 +4,13 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs
Total CPU time to Xst completion: 0.52 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs
Total CPU time to Xst completion: 0.52 secs
--> Reading design: SFpga.prj
......@@ -273,14 +273,14 @@ WARNING:Xst:653 - Signal <Gbit1Sys2App_o> is used but never assigned. This sourc
WARNING:Xst:653 - Signal <Gbit2Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit3Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 22-bit register for signal <VcTcXoDivider_c>.
Found 22-bit register for signal <VmeSysClkDivider_c>.
Found 24-bit register for signal <VcTcXoDivider_c>.
Found 24-bit register for signal <VmeSysClkDivider_c>.
Found 2-bit register for signal <VmeSysReset_dx>.
Found 1-bit register for signal <Rst_rq>.
Found 22-bit register for signal <Si57xDivider_c>.
Found 22-bit adder for signal <Si57xDivider_c[21]_GND_2_o_add_9_OUT> created at line 380.
Found 22-bit adder for signal <VcTcXoDivider_c[21]_GND_2_o_add_12_OUT> created at line 383.
Found 22-bit adder for signal <VmeSysClkDivider_c[21]_GND_2_o_add_15_OUT> created at line 386.
Found 24-bit register for signal <Si57xDivider_c>.
Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_9_OUT> created at line 380.
Found 24-bit adder for signal <VcTcXoDivider_c[23]_GND_2_o_add_12_OUT> created at line 383.
Found 24-bit adder for signal <VmeSysClkDivider_c[23]_GND_2_o_add_15_OUT> created at line 386.
Found 1-bit 4-to-1 multiplexer for signal <a_FpLed7> created at line 388.
Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 296
Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 300
......@@ -317,22 +317,22 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 634
Summary:
inferred 3 Adder/Subtractor(s).
inferred 69 D-type flip-flop(s).
inferred 75 D-type flip-flop(s).
inferred 1 Multiplexer(s).
inferred 33 Tristate(s).
Unit <SystemFpga> synthesized.
Synthesizing Unit <Monostable>.
Related source file is "/vfc_svn/hdl/design/monostable.v".
g_CounterBits = 20
Found 3-bit register for signal <AsynchInAX_db3>.
Found 20-bit register for signal <Counter_c>.
g_CounterBits = 26
Found 4-bit register for signal <AsynchInAX_db4>.
Found 26-bit register for signal <Counter_c>.
Found 1-bit register for signal <SynchOutput_oq>.
Found 1-bit register for signal <AsynchIn_ax>.
Found 20-bit adder for signal <Counter_c[19]_GND_25_o_add_6_OUT> created at line 20.
Found 26-bit adder for signal <Counter_c[25]_GND_25_o_add_6_OUT> created at line 20.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 25 D-type flip-flop(s).
inferred 32 D-type flip-flop(s).
Unit <Monostable> synthesized.
Synthesizing Unit <Debouncer>.
......@@ -611,8 +611,9 @@ Macro Statistics
# Adders/Subtractors : 13
12-bit adder : 1
16-bit adder : 2
20-bit adder : 2
22-bit adder : 4
22-bit adder : 1
24-bit adder : 3
26-bit adder : 2
3-bit adder : 2
4-bit addsub : 1
9-bit adder : 1
......@@ -621,12 +622,13 @@ Macro Statistics
12-bit register : 1
16-bit register : 2
2-bit register : 4
20-bit register : 2
22-bit register : 4
3-bit register : 6
22-bit register : 1
24-bit register : 3
26-bit register : 2
3-bit register : 4
31-bit register : 1
32-bit register : 15
4-bit register : 1
4-bit register : 3
7-bit register : 1
8-bit register : 3
9-bit register : 1
......@@ -653,7 +655,7 @@ Macro Statistics
1-bit tristate buffer : 65
# FSMs : 2
# Xors : 4
1-bit xor3 : 2
1-bit xor2 : 2
1-bit xor6 : 2
=========================================================================
......@@ -720,13 +722,13 @@ Macro Statistics
3-bit adder : 2
# Counters : 10
16-bit up counter : 1
20-bit up counter : 2
22-bit up counter : 3
24-bit up counter : 3
26-bit up counter : 2
3-bit up counter : 2
4-bit updown counter : 1
9-bit up counter : 1
# Registers : 680
Flip-Flops : 680
# Registers : 682
Flip-Flops : 682
# Comparators : 9
1-bit comparator equal : 1
12-bit comparator equal : 1
......@@ -747,7 +749,7 @@ Macro Statistics
7-bit 2-to-1 multiplexer : 1
# FSMs : 2
# Xors : 4
1-bit xor3 : 2
1-bit xor2 : 2
1-bit xor6 : 2
=========================================================================
......@@ -832,6 +834,8 @@ Final Macro Processing ...
Processing Unit <SFpga> :
Found 2-bit shift register for signal <i_Core/VmeSysReset_dx_1>.
Found 3-bit shift register for signal <i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2>.
Found 3-bit shift register for signal <i_Core/i_ClearMonostable/AsynchInAX_db4_2>.
Found 3-bit shift register for signal <i_Core/i_Debouncer/BouncingSignal_x_2>.
Found 2-bit shift register for signal <i_Core/i_Slv2SerWB/AckI_xb3_0>.
Unit <SFpga> processed.
......@@ -840,11 +844,11 @@ Unit <SFpga> processed.
Final Register Report
Macro Statistics
# Registers : 793
Flip-Flops : 793
# Shift Registers : 3
# Registers : 807
Flip-Flops : 807
# Shift Registers : 5
2-bit shift register : 2
3-bit shift register : 1
3-bit shift register : 3
=========================================================================
......@@ -867,32 +871,32 @@ Top Level Output File Name : SFpga.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1430
# BELS : 1497
# GND : 1
# INV : 29
# LUT1 : 163
# LUT2 : 163
# LUT3 : 121
# LUT4 : 112
# LUT5 : 148
# LUT6 : 307
# MUXCY : 186
# MUXF7 : 18
# LUT1 : 181
# LUT2 : 166
# LUT3 : 130
# LUT4 : 113
# LUT5 : 146
# LUT6 : 299
# MUXCY : 204
# MUXF7 : 28
# VCC : 1
# XORCY : 181
# FlipFlops/Latches : 796
# FD : 189
# FDE : 99
# XORCY : 199
# FlipFlops/Latches : 812
# FD : 191
# FDE : 101
# FDPE : 1
# FDR : 135
# FDRE : 313
# FDRE : 325
# FDS : 26
# FDSE : 33
# RAMS : 3
# RAM16X1D : 2
# RAM32M : 1
# Shift Registers : 3
# SRLC16E : 3
# Shift Registers : 5
# SRLC16E : 5
# Clock Buffers : 4
# BUFG : 1
# BUFGP : 3
......@@ -912,18 +916,18 @@ Selected Device : 6slx150tfgg676-3
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184304 0%
Number of Slice LUTs: 1054 out of 92152 1%
Number used as Logic: 1043 out of 92152 1%
Number used as Memory: 11 out of 21680 0%
Number of Slice Registers: 812 out of 184304 0%
Number of Slice LUTs: 1077 out of 92152 1%
Number used as Logic: 1064 out of 92152 1%
Number used as Memory: 13 out of 21680 0%
Number used as RAM: 8
Number used as SRL: 3
Number used as SRL: 5
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1274
Number with an unused Flip Flop: 478 out of 1274 37%
Number with an unused LUT: 220 out of 1274 17%
Number of fully used LUT-FF pairs: 576 out of 1274 45%
Number of LUT Flip Flop pairs used: 1293
Number with an unused Flip Flop: 481 out of 1293 37%
Number with an unused LUT: 216 out of 1293 16%
Number of fully used LUT-FF pairs: 596 out of 1293 46%
Number of unique control sets: 32
IO Utilization:
......@@ -954,9 +958,9 @@ Clock Information:
-----------------------------------+-----------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+-----------------------------------------------+-------+
Si57x_ik | IBUFGDS+BUFG | 688 |
VcTcXo_ik | BUFGP | 22 |
VmeSysClk_ik | BUFGP | 22 |
Si57x_ik | IBUFGDS+BUFG | 702 |
VcTcXo_ik | BUFGP | 24 |
VmeSysClk_ik | BUFGP | 24 |
i_Core/i_VmeInterface/stb_o | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax)| 1 |
i_Core/Rst_rq | NONE(i_Core/i_ClearMonostable/AsynchIn_ax) | 1 |
SysAppClk_ik | BUFGP | 68 |
......@@ -983,7 +987,7 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'Si57x_ik'
Clock period: 8.328ns (frequency: 120.083MHz)
Total number of paths / destination ports: 44586 / 1579
Total number of paths / destination ports: 45452 / 1617
-------------------------------------------------------------------------
Delay: 8.328ns (Levels of Logic = 5)
Source: i_Core/i_VmeInterface/adr_o_21_1 (FF)
......@@ -1000,7 +1004,7 @@ Delay: 8.328ns (Levels of Logic = 5)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1)
LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster)
LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster)
LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o)
LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_33_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_33_o)
FDSE:CE 0.302 i_Core/i_VmeInterface/DataReg_0
----------------------------------------
Total 8.328ns (2.074ns logic, 6.254ns route)
......@@ -1008,16 +1012,16 @@ Delay: 8.328ns (Levels of Logic = 5)
=========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 2.319ns (frequency: 431.248MHz)
Total number of paths / destination ports: 253 / 22
Clock period: 2.365ns (frequency: 422.770MHz)
Total number of paths / destination ports: 300 / 24
-------------------------------------------------------------------------
Delay: 2.319ns (Levels of Logic = 23)
Delay: 2.365ns (Levels of Logic = 25)
Source: i_Core/VcTcXoDivider_c_0 (FF)
Destination: i_Core/VcTcXoDivider_c_21 (FF)
Destination: i_Core/VcTcXoDivider_c_23 (FF)
Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising
Data Path: i_Core/VcTcXoDivider_c_0 to i_Core/VcTcXoDivider_c_21
Data Path: i_Core/VcTcXoDivider_c_0 to i_Core/VcTcXoDivider_c_23
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
......@@ -1043,25 +1047,27 @@ Delay: 2.319ns (Levels of Logic = 23)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<17> (i_Core/Mcount_VcTcXoDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<18> (i_Core/Mcount_VcTcXoDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<19> (i_Core/Mcount_VcTcXoDivider_c_cy<19>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<20> (i_Core/Mcount_VcTcXoDivider_c_cy<20>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VcTcXoDivider_c_xor<21> (i_Core/Result<21>1)
FD:D 0.074 i_Core/VcTcXoDivider_c_21
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<20> (i_Core/Mcount_VcTcXoDivider_c_cy<20>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<21> (i_Core/Mcount_VcTcXoDivider_c_cy<21>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<22> (i_Core/Mcount_VcTcXoDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VcTcXoDivider_c_xor<23> (i_Core/Result<23>1)
FD:D 0.074 i_Core/VcTcXoDivider_c_23
----------------------------------------
Total 2.319ns (1.740ns logic, 0.579ns route)
(75.0% logic, 25.0% route)
Total 2.365ns (1.787ns logic, 0.579ns route)
(75.5% logic, 24.5% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'VmeSysClk_ik'
Clock period: 2.319ns (frequency: 431.248MHz)
Total number of paths / destination ports: 253 / 22
Clock period: 2.365ns (frequency: 422.770MHz)
Total number of paths / destination ports: 300 / 24
-------------------------------------------------------------------------
Delay: 2.319ns (Levels of Logic = 23)
Delay: 2.365ns (Levels of Logic = 25)
Source: i_Core/VmeSysClkDivider_c_0 (FF)
Destination: i_Core/VmeSysClkDivider_c_21 (FF)
Destination: i_Core/VmeSysClkDivider_c_23 (FF)
Source Clock: VmeSysClk_ik rising
Destination Clock: VmeSysClk_ik rising
Data Path: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_21
Data Path: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_23
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
......@@ -1087,12 +1093,14 @@ Delay: 2.319ns (Levels of Logic = 23)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<17> (i_Core/Mcount_VmeSysClkDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<18> (i_Core/Mcount_VmeSysClkDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<19> (i_Core/Mcount_VmeSysClkDivider_c_cy<19>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<20> (i_Core/Mcount_VmeSysClkDivider_c_cy<20>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VmeSysClkDivider_c_xor<21> (i_Core/Result<21>)
FD:D 0.074 i_Core/VmeSysClkDivider_c_21
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<20> (i_Core/Mcount_VmeSysClkDivider_c_cy<20>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<21> (i_Core/Mcount_VmeSysClkDivider_c_cy<21>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<22> (i_Core/Mcount_VmeSysClkDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VmeSysClkDivider_c_xor<23> (i_Core/Result<23>)
FD:D 0.074 i_Core/VmeSysClkDivider_c_23
----------------------------------------
Total 2.319ns (1.740ns logic, 0.579ns route)
(75.0% logic, 25.0% route)
Total 2.365ns (1.787ns logic, 0.579ns route)
(75.5% logic, 24.5% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/i_VmeInterface/stb_o'
......@@ -1176,7 +1184,7 @@ Offset: 8.362ns (Levels of Logic = 6)
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N5)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N259)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N263)
LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected)
LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv)
FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0
......@@ -1228,15 +1236,15 @@ Timing constraint: Default OFFSET OUT AFTER for Clock 'VmeSysClk_ik'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 4.828ns (Levels of Logic = 2)
Source: i_Core/VmeSysClkDivider_c_21 (FF)
Source: i_Core/VmeSysClkDivider_c_23 (FF)
Destination: FpLed_onb8<7> (PAD)
Source Clock: VmeSysClk_ik rising
Data Path: i_Core/VmeSysClkDivider_c_21 to FpLed_onb8<7>
Data Path: i_Core/VmeSysClkDivider_c_23 to FpLed_onb8<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 3 0.525 0.759 i_Core/VmeSysClkDivider_c_21 (i_Core/VmeSysClkDivider_c_21)
FD:C->Q 3 0.525 0.759 i_Core/VmeSysClkDivider_c_23 (i_Core/VmeSysClkDivider_c_23)
LUT5:I3->O 1 0.250 0.579 i_Core/Mmux_a_FpLed711 (i_Core/a_FpLed7)
OBUFT:T->O 2.715 FpLed_onb8_7_OBUFT (FpLed_onb8<7>)
----------------------------------------
......@@ -1248,15 +1256,15 @@ Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 4.724ns (Levels of Logic = 2)
Source: i_Core/VcTcXoDivider_c_21 (FF)
Source: i_Core/VcTcXoDivider_c_23 (FF)
Destination: FpLed_onb8<7> (PAD)
Source Clock: VcTcXo_ik rising
Data Path: i_Core/VcTcXoDivider_c_21 to FpLed_onb8<7>
Data Path: i_Core/VcTcXoDivider_c_23 to FpLed_onb8<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 3 0.525 0.651 i_Core/VcTcXoDivider_c_21 (i_Core/VcTcXoDivider_c_21)
FD:C->Q 3 0.525 0.651 i_Core/VcTcXoDivider_c_23 (i_Core/VcTcXoDivider_c_23)
LUT5:I4->O 1 0.254 0.579 i_Core/Mmux_a_FpLed711 (i_Core/a_FpLed7)
OBUFT:T->O 2.715 FpLed_onb8_7_OBUFT (FpLed_onb8<7>)
----------------------------------------
......@@ -1277,7 +1285,7 @@ Delay: 6.896ns (Levels of Logic = 4)
---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.823 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT2:I0->O 1 0.250 0.579 i_Core/VmeGa_ib5n[4]_UseGa_i_OR_1_o_inv1 (i_Core/VmeGa_ib5n[4]_UseGa_i_OR_1_o_inv)
LUT2:I0->O 1 0.250 0.579 i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv1 (i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv)
OBUFT:T->O 2.715 FpLed_onb8_2_OBUFT (FpLed_onb8<2>)
----------------------------------------
Total 6.896ns (4.447ns logic, 2.449ns route)
......@@ -1295,8 +1303,8 @@ Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+
Si57x_ik | 8.328| | | |
SysAppClk_ik | 1.178| | | |
i_Core/Rst_rq | 1.215| | | |
i_Core/i_VmeInterface/stb_o| 1.215| | | |
i_Core/Rst_rq | 1.141| | | |
i_Core/i_VmeInterface/stb_o| 1.141| | | |
---------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik
......@@ -1313,7 +1321,7 @@ Clock to Setup on destination clock VcTcXo_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VcTcXo_ik | 2.319| | | |
VcTcXo_ik | 2.365| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VmeSysClk_ik
......@@ -1321,7 +1329,7 @@ Clock to Setup on destination clock VmeSysClk_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
VmeSysClk_ik | 2.319| | | |
VmeSysClk_ik | 2.365| | | |