Commit 265c6bd0 authored by Andrea Boccardi's avatar Andrea Boccardi

added a doc, recompiled the system FPGA

parent cd70b752
This diff is collapsed.
...@@ -15,8 +15,8 @@ Checking Constraint Associations... ...@@ -15,8 +15,8 @@ Checking Constraint Associations...
Done... Done...
Checking expanded design ... Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N450' has no driver WARNING:NgdBuild:452 - logical net 'N456' has no driver
WARNING:NgdBuild:452 - logical net 'N452' has no driver WARNING:NgdBuild:452 - logical net 'N458' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
...@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary: ...@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary:
Total memory usage is 155980 kilobytes Total memory usage is 155980 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 4 sec Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 3 sec Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"... Writing NGDBUILD log file "SFpga.bld"...
...@@ -75,3 +75,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -75,3 +75,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010 Mon Dec 20 08:27:29 2010
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 par M.70d (nt64) Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Fri Dec 17 11:12:22 2010 PCBE13225:: Mon Dec 20 08:26:58 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
...@@ -21,38 +21,38 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15". ...@@ -21,38 +21,38 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary: Device Utilization Summary:
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 812
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1% Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 573
Number using O5 output only: 154 Number using O5 output only: 172
Number using O5 and O6: 166 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 3 Number used as Shift Register: 5
Number using O6 output only: 3 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 32 Number used exclusively as route-thrus: 30
Number with same-slice register load: 23 Number with same-slice register load: 21
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1% Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101 Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 386 out of 1,101 35% Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 167 out of 1,101 15% Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 548 out of 1,101 49% Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0% to control set restrictions: 0 out of 184,304 0%
...@@ -99,8 +99,8 @@ Specific Feature Utilization: ...@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High Overall effort level (-ol): High
Router effort level (-rl): High Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 10 secs Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
...@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O ...@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router Starting Router
Phase 1 : 5227 unrouted; REAL time: 12 secs Phase 1 : 5256 unrouted; REAL time: 11 secs
Phase 2 : 4601 unrouted; REAL time: 15 secs Phase 2 : 4603 unrouted; REAL time: 15 secs
Phase 3 : 1750 unrouted; REAL time: 21 secs Phase 3 : 1808 unrouted; REAL time: 20 secs
Phase 4 : 1750 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs Phase 4 : 1808 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Updating file: SFpga.ncd with current fully routed design. Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 30 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Total REAL time to Router completion: 30 secs Total REAL time to Router completion: 29 secs
Total CPU time to Router completion: 29 secs Total CPU time to Router completion: 28 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -192,18 +192,18 @@ Generating Clock Report ...@@ -192,18 +192,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 229 | 0.260 | 1.710 | | Si57x_BUFG | BUFGMUX_X2Y4| No | 220 | 0.242 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.009 | 1.640 | | VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.008 | 1.643 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 | | VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.186 | 1.693 | | SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.189 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 223 | 0.000 | 7.868 | | i_Core/Rst_rq | Local| | 211 | 0.000 | 3.873 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | | |i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.686 | | e/stb_o | Local| | 19 | 0.000 | 4.113 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
...@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met. ...@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.435ns| 7.898ns| 0| 0 TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.429ns| 7.904ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0 20 MHz HIGH 50% | HOLD | 0.225ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.464ns| 3.869ns| 0| 0 TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.826ns| 3.507ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.442ns| | 0| 0 lk_ik" 120 MHz HIGH 50% | HOLD | 0.468ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
...@@ -237,10 +237,10 @@ All signals are completely routed. ...@@ -237,10 +237,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 32 secs Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 32 secs Total CPU time to PAR completion: 31 secs
Peak Memory Usage: 546 MB Peak Memory Usage: 545 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
......
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Fri Dec 17 11:12:18 2010 // Written by: Map M.70d on Mon Dec 20 08:26:52 2010
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
...@@ -333,7 +333,8 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1; ...@@ -333,7 +333,8 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1; COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1; COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1; COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL "i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL "i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL "i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
...@@ -435,6 +436,12 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -435,6 +436,12 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL "i_Core/i_VmeInterface/DataReg_2" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL "i_Core/i_VmeInterface/DataReg_1" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL "i_Core/i_VmeInterface/DataReg_0" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_24" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_19" BEL "i_Core/i_VmeAccessMonostable/Counter_c_19" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_18" BEL "i_Core/i_VmeAccessMonostable/Counter_c_18" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_17" BEL "i_Core/i_VmeAccessMonostable/Counter_c_17" BEL
...@@ -455,9 +462,13 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -455,9 +462,13 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_2" BEL "i_Core/i_VmeAccessMonostable/Counter_c_2" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL "i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL "i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_2" BEL "i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_1" BEL "i_Core/i_ClearMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_0" BEL "i_Core/i_ClearMonostable/Counter_c_24" BEL
"i_Core/i_ClearMonostable/Counter_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_22" BEL
"i_Core/i_ClearMonostable/Counter_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_20" BEL
"i_Core/i_ClearMonostable/Counter_c_19" BEL "i_Core/i_ClearMonostable/Counter_c_19" BEL
"i_Core/i_ClearMonostable/Counter_c_18" BEL "i_Core/i_ClearMonostable/Counter_c_18" BEL
"i_Core/i_ClearMonostable/Counter_c_17" BEL "i_Core/i_ClearMonostable/Counter_c_17" BEL
...@@ -478,9 +489,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -478,9 +489,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_2" BEL "i_Core/i_ClearMonostable/Counter_c_2" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL "i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL "i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_2" BEL "i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_1" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_0" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL "i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL "i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL "i_Core/i_Debouncer/Counter_c_13" BEL
...@@ -959,11 +968,15 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -959,11 +968,15 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL "i_Core/i_VmeInterface/AckTimeout_c_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL "i_Core/i_VmeInterface/AckTimeout_c_3" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL "i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL "i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "i_Core/Mshreg_VmeSysReset_dx_1" "i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL
BEL "i_Core/VmeSysReset_dx_1" BEL "i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL "i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL "PllSysRef12_ok" BEL "i_Core/i_Debouncer/BouncingSignal_x_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL "PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL "PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL "i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
......
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.435" best="7.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.464" best="3.869" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.442" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.429" best="7.904" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.225" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.826" best="3.507" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.468" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
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Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010 Mon Dec 20 08:27:29 2010
All signals are completely routed. All signals are completely routed.
......
...@@ -22,10 +22,10 @@ ...@@ -22,10 +22,10 @@
</tr> </tr>
<tr> <tr>
<td>Path</td> <td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
</tr> </tr>
<tr> <tr>
<td>XILINX</td> <td>XILINX</td>
......
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 11:11:25 2010 Mapped Date : Mon Dec 20 08:25:44 2010
Mapping design into LUTs... Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
...@@ -89,20 +89,20 @@ Updating timing models... ...@@ -89,20 +89,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 16 secs Total REAL time at the beginning of Placer: 30 secs
Total CPU time at the beginning of Placer: 12 secs Total CPU time at the beginning of Placer: 13 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:fbd9bf1c) REAL time: 21 secs Phase 1.1 Initial Placement Analysis (Checksum:ee27935a) REAL time: 36 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:fbd9bf1c) REAL time: 22 secs Phase 2.7 Design Feasibility Check (Checksum:ee27935a) REAL time: 36 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:fbd9bf1c) REAL time: 22 secs Phase 3.31 Local Placement Optimization (Checksum:ee27935a) REAL time: 36 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
... ...
...@@ -120,42 +120,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found ...@@ -120,42 +120,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design. that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:b9a90c54) REAL time: 29 secs (Checksum:d3736e22) REAL time: 44 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:b9a90c54) REAL time: 29 secs Phase 5.36 Local Placement Optimization (Checksum:d3736e22) REAL time: 44 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:b9a90c54) REAL time: 29 secs Phase 6.30 Global Clock Region Assignment (Checksum:d3736e22) REAL time: 44 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
... ...
Phase 7.3 Local Placement Optimization (Checksum:5a4374ed) REAL time: 30 secs Phase 7.3 Local Placement Optimization (Checksum:d47075b5) REAL time: 45 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b9b9c566) REAL time: 30 secs Phase 8.5 Local Placement Optimization (Checksum:d384eabe) REAL time: 45 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
... ........
....................... .......................
................ .....................................
...... ....
Phase 9.8 Global Placement (Checksum:94595592) REAL time: 36 secs Phase 9.8 Global Placement (Checksum:7253f7a8) REAL time: 52 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:94595592) REAL time: 36 secs Phase 10.5 Local Placement Optimization (Checksum:7253f7a8) REAL time: 52 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:df505277) REAL time: 47 secs Phase 11.18 Placement Optimization (Checksum:85580283) REAL time: 1 mins 2 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:df505277) REAL time: 47 secs Phase 12.5 Local Placement Optimization (Checksum:85580283) REAL time: 1 mins 2 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:967c17e4) REAL time: 47 secs Phase 13.34 Placement Validation (Checksum:8244a4e2) REAL time: 1 mins 3 secs
Total REAL time to Placer completion: 52 secs Total REAL time to Placer completion: 1 mins 7 secs
Total CPU time to Placer completion: 47 secs Total CPU time to Placer completion: 48 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
...@@ -261,41 +261,41 @@ Design Summary: ...@@ -261,41 +261,41 @@ Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 83 Number of warnings: 83
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 812
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1% Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 573
Number using O5 output only: 154 Number using O5 output only: 172
Number using O5 and O6: 166 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 3 Number used as Shift Register: 5
Number using O6 output only: 3 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 32 Number used exclusively as route-thrus: 30
Number with same-slice register load: 23 Number with same-slice register load: 21
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1% Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101 Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 386 out of 1,101 35% Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 167 out of 1,101 15% Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 548 out of 1,101 49% Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of unique control sets: 32 Number of unique control sets: 32
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1% to control set restrictions: 83 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -336,11 +336,11 @@ Specific Feature Utilization: ...@@ -336,11 +336,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02 Average Fanout of Non-Clock Nets: 3.01
Peak Memory Usage: 629 MB Peak Memory Usage: 630 MB
Total REAL time to MAP completion: 54 secs Total REAL time to MAP completion: 1 mins 10 secs
Total CPU time to MAP completion: 49 secs Total CPU time to MAP completion: 50 secs
Mapping completed. Mapping completed.
See MAP report file "SFpga_map.mrp" for details. See MAP report file "SFpga_map.mrp" for details.
...@@ -10,48 +10,48 @@ Target Device : xc6slx150t ...@@ -10,48 +10,48 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 11:11:25 2010 Mapped Date : Mon Dec 20 08:25:44 2010
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 83 Number of warnings: 83
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 812
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1% Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 573
Number using O5 output only: 154 Number using O5 output only: 172
Number using O5 and O6: 166 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 3