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VME FMC Carrier VFC
Commits
33c447a0
Commit
33c447a0
authored
Dec 21, 2010
by
Andrea Boccardi
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parent
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2 changed files
with
60 additions
and
59 deletions
+60
-59
AddrDecoderWBSys.v
trunk/hdl/design/AddrDecoderWBSys.v
+21
-20
SystemFpga.v
trunk/hdl/design/SystemFpga.v
+39
-39
No files found.
trunk/hdl/design/AddrDecoderWBSys.v
View file @
33c447a0
module
AddressDecoderWBSys
(
module
AddressDecoderWBSys
(
input
Clk_ik
,
input
[
21
:
0
]
Adr_ib22
,
input
[
21
:
0
]
Adr_ib22
,
input
Stb_i
,
input
Stb_i
,
output
reg
[
31
:
0
]
Dat_ob32
,
output
reg
[
31
:
0
]
Dat_ob32
,
output
Ack_o
,
output
reg
Ack_o
,
input
[
31
:
0
]
DatIntManager_ib32
,
input
[
31
:
0
]
DatIntManager_ib32
,
input
AckIntMAnager_i
,
input
AckIntMAnager_i
,
...
@@ -25,30 +26,30 @@ module AddressDecoderWBSys(
...
@@ -25,30 +26,30 @@ module AddressDecoderWBSys(
output
reg
StbSpiMaster_o
output
reg
StbSpiMaster_o
)
;
)
;
assign
Ack_o
=
AckIntMAnager_i
||
AckGenericOutputRegs_i
||
AckGenericOutputRegs_i
||
AckSlv2SerWB_i
||
AckSpiMaster_i
;
always
@*
begin
always
@
(
posedge
Clk_ik
)
begin
Dat_ob32
=
32'h0
;
Ack_o
<=
AckIntMAnager_i
||
AckGenericOutputRegs_i
||
AckGenericOutputRegs_i
||
AckSlv2SerWB_i
||
AckSpiMaster_i
;
StbIntManager_o
=
1'b0
;
Dat_ob32
<=
32'h0
;
StbGenericOutputRegs_o
=
1'b0
;
StbIntManager_o
<=
1'b0
;
StbGenericInputRegs_o
=
1'b0
;
StbGenericOutputRegs_o
<=
1'b0
;
StbSlv2SerWB_o
=
1'b0
;
StbGenericInputRegs_o
<=
1'b0
;
StbSpiMaster_o
=
1'b0
;
StbSlv2SerWB_o
<=
1'b0
;
StbSpiMaster_o
<=
1'b0
;
if
(
Adr_ib22
[
21
:
2
]
==
20'h0
)
begin
// FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
if
(
Adr_ib22
[
21
:
2
]
==
20'h0
)
begin
// FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
StbIntManager_o
=
Stb_i
;
StbIntManager_o
<
=
Stb_i
;
Dat_ob32
=
DatIntManager_ib32
;
Dat_ob32
<
=
DatIntManager_ib32
;
end
else
if
(
Adr_ib22
[
21
:
2
]
==
20'h1
)
begin
// FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
end
else
if
(
Adr_ib22
[
21
:
2
]
==
20'h1
)
begin
// FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
StbGenericOutputRegs_o
=
Stb_i
;
StbGenericOutputRegs_o
<
=
Stb_i
;
Dat_ob32
=
DatGenericOutputRegs_ib32
;
Dat_ob32
<
=
DatGenericOutputRegs_ib32
;
end
else
if
(
Adr_ib22
[
21
:
2
]
==
20'h2
)
begin
// FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
end
else
if
(
Adr_ib22
[
21
:
2
]
==
20'h2
)
begin
// FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
StbGenericInputRegs_o
=
Stb_i
;
StbGenericInputRegs_o
<
=
Stb_i
;
Dat_ob32
=
DatGenericInputRegs_ib32
;
Dat_ob32
<
=
DatGenericInputRegs_ib32
;
end
else
if
(
Adr_ib22
[
21
:
3
]
==
19'h2
)
begin
// FROM 00_0010 TO 00_0017 (WB) == FROM 00_0040 TO 00_005C (VME) <- 8 regs (32B)
end
else
if
(
Adr_ib22
[
21
:
3
]
==
19'h2
)
begin
// FROM 00_0010 TO 00_0017 (WB) == FROM 00_0040 TO 00_005C (VME) <- 8 regs (32B)
StbSpiMaster_o
=
Stb_i
;
StbSpiMaster_o
<
=
Stb_i
;
Dat_ob32
=
DatSpiMaster_ib32
;
Dat_ob32
<
=
DatSpiMaster_ib32
;
end
else
if
(
Adr_ib22
[
21
]
==
1'b1
)
begin
// FROM 20_0000 TO 3F_FFFF (WB) == FROM 80_0000 TO FF_FFFC (VME) <- 2M regs (8MB)
end
else
if
(
Adr_ib22
[
21
]
==
1'b1
)
begin
// FROM 20_0000 TO 3F_FFFF (WB) == FROM 80_0000 TO FF_FFFC (VME) <- 2M regs (8MB)
StbSlv2SerWB_o
=
Stb_i
;
StbSlv2SerWB_o
<
=
Stb_i
;
Dat_ob32
=
DatSlv2SerWB_ib32
;
Dat_ob32
<
=
DatSlv2SerWB_ib32
;
end
end
end
end
...
...
trunk/hdl/design/SystemFpga.v
View file @
33c447a0
...
@@ -274,15 +274,13 @@ wire [31:0] SpiSS_nb32, SpiMiSo_b32;
...
@@ -274,15 +274,13 @@ wire [31:0] SpiSS_nb32, SpiMiSo_b32;
wire
SpiMoSi
,
SpiSClk_k
;
wire
SpiMoSi
,
SpiSClk_k
;
wire
StbSpiMaster
,
AckSpiMaster
;
wire
StbSpiMaster
,
AckSpiMaster
;
wire
[
31
:
0
]
DatSpiMaster_b32
;
wire
[
31
:
0
]
DatSpiMaster_b32
;
wire
Si57xDivided
,
VcTcXoDivided
,
VmeSysClkDivided
;
wire
Si57xDivided
;
wire
Clk_k
;
wire
Clk_k
;
wire
a_VmeSysReset_nq
;
wire
a_VmeSysReset_nq
;
wire
[
7
:
0
]
IntSource_b8
;
wire
[
7
:
0
]
IntSource_b8
;
wire
[
2
:
0
]
InterrupLevel
;
wire
[
2
:
0
]
InterrupLevel
;
wire
[
7
:
0
]
IntVector_b8
;
wire
[
7
:
0
]
IntVector_b8
;
reg
[
23
:
0
]
Si57xDivider_c
=
'd0
;
reg
[
23
:
0
]
Si57xDivider_c
=
'd0
;
reg
[
23
:
0
]
VcTcXoDivider_c
=
'd0
;
reg
[
23
:
0
]
VmeSysClkDivider_c
=
'd0
;
reg
a_FpLed7
;
reg
a_FpLed7
;
reg
Rst_rq
;
reg
Rst_rq
;
reg
[
1
:
0
]
VmeSysReset_dx
;
reg
[
1
:
0
]
VmeSysReset_dx
;
...
@@ -374,23 +372,12 @@ Monostable i_ClearMonostable(
...
@@ -374,23 +372,12 @@ Monostable i_ClearMonostable(
assign
Si57xDivided
=
Si57xDivider_c
[
23
]
;
assign
Si57xDivided
=
Si57xDivider_c
[
23
]
;
always
@
(
posedge
Si57x_ik
)
Si57xDivider_c
<=
#
`dly
Si57xDivider_c
+
1'b1
;
always
@
(
posedge
Si57x_ik
)
Si57xDivider_c
<=
#
`dly
Si57xDivider_c
+
1'b1
;
assign
VcTcXoDivided
=
VcTcXoDivider_c
[
23
]
;
always
@
(
posedge
VcTcXo_ik
)
VcTcXoDivider_c
<=
#
`dly
VcTcXoDivider_c
+
1'b1
;
assign
VmeSysClkDivided
=
VmeSysClkDivider_c
[
23
]
;
always
@
(
posedge
Clk_k
)
<=
We
&&
Cyc
;
always
@
(
posedge
VmeSysClk_ik
)
VmeSysClkDivider_c
<=
#
`dly
VmeSysClkDivider_c
+
1'b1
;
reg
WriteCycle
;
reg
Debug1
,
Debug2
,
Debug3
Debug4
;
always
@
(
posedge
Clk_k
)
WriteCycle
<=
We
&&
Cyc
;
Monostable
i_Debug1Monostable
(
Monostable
i_WriteCycleMonostable
(
.
AsynchIn_ia
(
WriteCycle
)
,
.
Clk_ik
(
Clk_k
)
,
.
SynchOutput_oq
(
WriteCycleLed
))
;
/*Monostable i_Debug1Monostable(
.
AsynchIn_ia
(
Debug1
)
,
.
AsynchIn_ia
(
Debug1
)
,
.
Clk_ik
(
Clk_k
)
,
.
Clk_ik
(
Clk_k
)
,
.
SynchOutput_oq
(
DebugForLed1
))
;
.
SynchOutput_oq
(
DebugForLed1
))
;
...
@@ -403,19 +390,31 @@ Monostable i_Debug2Monostable(
...
@@ -403,19 +390,31 @@ Monostable i_Debug2Monostable(
Monostable
i_Debug3Monostable
(
Monostable
i_Debug3Monostable
(
.
AsynchIn_ia
(
Debug3
)
,
.
AsynchIn_ia
(
Debug3
)
,
.
Clk_ik
(
Clk_k
)
,
.
Clk_ik
(
Clk_k
)
,
.SynchOutput_oq(DebugForLed3));*/
.
SynchOutput_oq
(
DebugForLed3
))
;
Monostable
i_Debug3Monostable
(
.
AsynchIn_ia
(
Debug4
)
,
.
Clk_ik
(
Clk_k
)
,
.
SynchOutput_oq
(
DebugForLed4
))
;
assign
FpLed_onb8
[
0
]
=
VmeAccessForLed
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
0
]
=
VmeAccessForLed
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
1
]
=
(
|
VmeIrq_ob7
)
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
1
]
=
(
|
VmeIrq_ob7
)
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
2
]
=
(
^{
VmeGa_ib5n
,
~
VmeGaP_in
}
|
~
UseGa_i
)
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
2
]
=
(
^{
VmeGa_ib5n
,
~
VmeGaP_in
}
|
~
UseGa_i
)
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
3
]
=
RstForLed
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
3
]
=
(
Si57xDivided
||
RstForLed
)
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
4
]
=
Si57xDivided
?
1'bz
:
1'b0
;
assign
FpLed_onb8
[
5
]
=
VcTcXoDivided
?
1'bz
:
1'b0
;
assign
FpLed_onb8
[
4
]
=
DebugForLed1
?
1'b0
:
1'bz
;
assign
FpLed_onb8
[
6
]
=
VmeSysClkDivided
?
1'bz
:
1'b0
;
assign
FpLed_onb8
[
5
]
=
DebugForLed2
?
1'b0
:
1'bz
;
//assign FpLed_onb8[4] = DebugForLed1 ? 1'b0 : 1'bz;
assign
FpLed_onb8
[
6
]
=
DebugForLed3
?
1'b0
:
1'bz
;
//assign FpLed_onb8[5] = DebugForLed1 ? 1'b0 : 1'bz;
assign
FpLed_onb8
[
7
]
=
DebugForLed4
?
1'b0
:
1'bz
;
//assign FpLed_onb8[6] = DebugForLed1 ? 1'b0 : 1'bz;
assign
FpLed_onb8
[
7
]
=
WriteCycleLed
?
1'b0
:
1'bz
;
always
@
(
posedge
Clk_k
)
begin
Debug1
<=
Cyc
&&
StbGenericOutputRegs
&&
We
;
Debug2
<=
Cyc
&&
StbGenericOutputRegs
&&
We
;
Debug3
<=
Cyc
&&
StbGenericOutputRegs
&&
We
&&
DatMasterO_b32
==
32'habcd1234
;
Debug4
<=
Cyc
&&
StbGenericOutputRegs
&&
We
&&
Adr_b22
[
1
:
0
]
==
2'b00
&&
DatMasterO_b32
!=
32'h0
;
end
//####################################
//####################################
// FP GP IO
// FP GP IO
...
@@ -429,8 +428,8 @@ assign FpGpIo34OutputMode_o = 1'b1;
...
@@ -429,8 +428,8 @@ assign FpGpIo34OutputMode_o = 1'b1;
// Clock
// Clock
//####################################
//####################################
//
assign Clk_k= Si57x_ik;
assign
Clk_k
=
Si57x_ik
;
assign
Clk_k
=
VcTcXo_ik
;
//
assign Clk_k= VcTcXo_ik;
//#####################################
//#####################################
...
@@ -471,17 +470,17 @@ assign IntSource_b8[1] = SpiIdle;
...
@@ -471,17 +470,17 @@ assign IntSource_b8[1] = SpiIdle;
assign
IntSource_b8
[
0
]
=
SpiWaitingData
;
assign
IntSource_b8
[
0
]
=
SpiWaitingData
;
VmeInterfaceWB
i_VmeInterface
(
VmeInterfaceWB
i_VmeInterface
(
.
rst_i
(
Rst_rq
)
,
.
rst_i
(
Rst_rq
)
,
.
clk_i
(
Clk_k
)
,
.
clk_i
(
Clk_k
)
,
.
adr_o
(
Adr_b22
)
,
.
adr_o
(
Adr_b22
)
,
.
dat_o
(
DatMasterO_b32
)
,
.
dat_o
(
DatMasterO_b32
)
,
.
dat_i
(
DatMasterI_b32
)
,
.
dat_i
(
DatMasterI_b32
)
,
.
we_o
(
We
)
,
.
we_o
(
We
)
,
.
stb_o
(
StbMaster
)
,
.
stb_o
(
StbMaster
)
,
.
ack_i
(
AckMaster
)
,
.
ack_i
(
AckMaster
)
,
.
cyc_o
(
Cyc
)
,
.
cyc_o
(
Cyc
)
,
.
UseGa_i
(
UseGa_i
)
,
.
UseGa_i
(
UseGa_i
)
,
.
ManualAddress_i
(
ManualAddress_ib5
)
,
.
ManualAddress_i
(
ManualAddress_ib5
)
,
.
vme_ga
(
VmeGa_ib5n
)
,
.
vme_ga
(
VmeGa_ib5n
)
,
.
vme_gap
(
VmeGaP_in
)
,
.
vme_gap
(
VmeGaP_in
)
,
.
vme_as
(
VmeAs_in
)
,
.
vme_as
(
VmeAs_in
)
,
...
@@ -523,6 +522,7 @@ InterruptManagerWB i_InterruptManager(
...
@@ -523,6 +522,7 @@ InterruptManagerWB i_InterruptManager(
.
assert_interrupt
(
AssertInterrupt
))
;
.
assert_interrupt
(
AssertInterrupt
))
;
AddressDecoderWBSys
i_AddressDecoderWB
(
AddressDecoderWBSys
i_AddressDecoderWB
(
.
Clk_ik
(
Clk_k
)
,
.
Adr_ib22
(
Adr_b22
)
,
.
Adr_ib22
(
Adr_b22
)
,
.
Stb_i
(
StbMaster
)
,
.
Stb_i
(
StbMaster
)
,
.
Dat_ob32
(
DatMasterI_b32
)
,
.
Dat_ob32
(
DatMasterI_b32
)
,
...
...
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