Commit 393b47b8 authored by Andrea Boccardi's avatar Andrea Boccardi

Updated the simulation and added some Verilog models

parent e10d9b2b
Change the custom interface of the VMEInterface for a wishbone one
Si57x:
model
interface
AD9516 (PLL):
model
AD5666 (DAC):
model
AD9910 (DDS):
model
interface
AD7888 (ADC):
model
MT41J128M16 (DDR):
model
interface <= Xilinx with wishbone by Mathieu
CY7C1470 (SRAM):
model <= from Cypress but probably with excessive reolution (10ps)
interface
M25P128 (E2PROM):
model <= from numonix, but to be reworked
interface <= SPI one is enough?
DS18B20U+ (Temp + UniqueID):
model
Interface <= 1-wire from KK?
Xilinx-MGT
Xilinx-IOSerializer
module AddressDecoderWBApp(
input [20:0] Adr_ib21,
input Stb_i,
output reg [31:0] Dat_ob32,
output Ack_o,
input [31:0] DatDebugRegs_ib32,
input AckDebugRegs_i,
output reg StbDebugRegs_o);
assign Ack_o = AckDebugRegs_i;
always @* begin
StbDebugRegs_o = 1'b0;
Dat_ob32 = 32'h0;
if (Adr_ib21[20:2]=='h0) begin // FROM 0_0000 TO 0_0003 (WB) == FROM 80_0000 TO 80_000C (VME) <- 4 regs (16B)
StbDebugRegs_o = Stb_i;
Dat_ob32 =DatDebugRegs_ib32;
end
end
endmodule
module AddressDecoderWBSys(
input [21:0] Adr_ib22,
input Stb_i,
output reg [31:0] Dat_ob32,
output Ack_o,
input [31:0] DatIntManager_ib32,
input AckIntMAnager_i,
output reg StbIntManager_o,
input [31:0] DatDebugRegs_ib32,
input AckDebugRegs_i,
output reg StbDebugRegs_o,
input [31:0] DatSlv2SerWB_ib32,
input AckSlv2SerWB_i,
output reg StbSlv2SerWB_o,
input [31:0] DatSpiMaster_ib32,
input AckSpiMaster_i,
output reg StbSpiMaster_o
);
assign Ack_o = AckIntMAnager_i || AckDebugRegs_i || AckSlv2SerWB_i || AckSpiMaster_i;
always @* begin
Dat_ob32 = 32'h0;
StbIntManager_o = 1'b0;
StbDebugRegs_o = 1'b0;
StbSlv2SerWB_o = 1'b0;
StbSpiMaster_o = 1'b0;
if (Adr_ib22[21:2]==20'h0) begin // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
StbIntManager_o = Stb_i;
Dat_ob32 = DatIntManager_ib32;
end else if (Adr_ib22[21:2]==20'h1) begin // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
StbDebugRegs_o = Stb_i;
Dat_ob32 = DatDebugRegs_ib32;
end else if (Adr_ib22[21:3]==19'h1) begin // FROM 00_0008 TO 00_000F (WB) == FROM 00_0020 TO 00_003C (VME) <- 8 regs (32B)
StbSpiMaster_o = Stb_i;
Dat_ob32 = DatSpiMaster_ib32;
end else if (Adr_ib22[21]==1'b1) begin // FROM 20_0000 TO 3F_FFFF (WB) == FROM 80_0000 TO FF_FFFC (VME) <- 2M regs (8MB)
StbSlv2SerWB_o = Stb_i;
Dat_ob32 = DatSlv2SerWB_ib32;
end
end
endmodule
`timescale 1ns/1ns
module ApplicationFpga(
input SysAppClk_i,
inout [2:1] SysAppSlow_iob2,
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgClk_io,
inout [1:0] AFpgaProgM_iob2,
inout AFpgaProgCsi_io,
inout AFpgaProgRdWr_io,
inout AFpgaProgInit_io,
inout [4:1] FpGpIo_iob4,
input PushButton_ion);
`define dly #1
//#####################################
// Clock
//#####################################
wire Clk_k = SysAppClk_i;
//#####################################
// Reset Signal Generation
//#####################################
wire DeboucedPushButton_q;
Debouncer #(.g_CounterWidth(16), .g_SynchDepth(3)) i_Debouncer (
.Clk_ik(Clk_k),
.BouncingSignal_ia(PushButton_ion),
.DebouncedSignal_oq(DeboucedPushButton_q));
reg Rst_rq;
always @(posedge Clk_k) Rst_rq <= `dly ~DeboucedPushButton_q || RstWB;
//#####################################
// Front Panel Signals
//#####################################
assign FpGpIo_iob4[4] = Clk_k;
assign FpGpIo_iob4[3] = FpGpIo_iob4[1];
assign FpGpIo_iob4[2] = Clk_k;
//#####################################
// WishBone Serial Interface
//#####################################
wire [20:0] Adr_b21;
wire Cyc, We, StbMaster, AckMaster;
wire [31:0] DatMasterO_b32, DatMasterI_b32;
Ser2MstWB i_Ser2MstWB(
.Rst_orq(RstWB),
.Clk_ik(Clk_k),
.Cyc_o(Cyc),
.We_o(We),
.Adr_ob21(Adr_b21),
.Dat_ob32(DatMasterO_b32),
.Stb_o(StbMaster),
.Dat_ib32(DatMasterI_b32),
.Ack_i(AckMaster),
.SerClk_ik(SysAppClk_i),
.SerDat_i(SysAppSlow_iob2[1]),
.SerCntrl_i(SysAppSlow_iob2[2]),
.Stb_i(AFpgaProgD_iob8[7]),
.SerClk_ok(AFpgaProgD_iob8[6]),
.SerDat_o(AFpgaProgD_iob8[5]),
.Ack_o(AFpgaProgD_iob8[4]));
AddressDecoderWBApp i_AddressDecoderWB(
.Adr_ib21(Adr_b21),
.Stb_i(StbMaster),
.Dat_ob32(DatMasterI_b32),
.Ack_o(AckMaster),
.DatDebugRegs_ib32(DatDebugRegsrO_b32),
.AckDebugRegs_i(AckDebugRegs),
.StbDebugRegs_o(StbDebugRegs));
//#####################################
// Debug Registers
//#####################################
wire [31:0] DebugReg0, DebugReg1, DebugReg2, DebugReg3;
wire [31:0] DatDebugRegsrO_b32;
wire StbDebugRegs, AckDebugRegs;
Generic4RegsWB i_DebugRegs(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.Stb_i(StbDebugRegs),
.We_i(We),
.Adr_ib2(Adr_b21[1:0]),
.Dat_ib32(DatMasterO_b32),
.Dat_oab32(DatDebugRegsrO_b32),
.Ack_oa(AckDebugRegs),
.Reg0Value_ob32(DebugReg0),
.Reg1Value_ob32(DebugReg1),
.Reg2Value_ob32(DebugReg2),
.Reg3Value_ob32(DebugReg3));
endmodule
module Generic4RegsWB (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output Ack_oa,
output reg [31:0] Reg0Value_ob32,
output reg [31:0] Reg1Value_ob32,
output reg [31:0] Reg2Value_ob32,
output reg [31:0] Reg3Value_ob32);
always @(posedge Clk_ik)
if (Rst_irq) Reg0Value_ob32 <= #1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b00) Reg0Value_ob32 <= #1 Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg1Value_ob32 <= #1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b01) Reg1Value_ob32 <= #1 Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg2Value_ob32 <= #1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b10) Reg2Value_ob32 <= #1 Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg3Value_ob32 <= #1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==(2'b11)) Reg3Value_ob32 <= #1 Dat_ib32;
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ob32;
2'b01: Dat_oab32 = Reg1Value_ob32;
2'b10: Dat_oab32 = Reg2Value_ob32;
2'b11: Dat_oab32 = Reg3Value_ob32;
default: Dat_oab32 = Reg0Value_ob32;
endcase
endmodule
`timescale 1 ns/ 1 ns
module InterruptManagerWB (
input int_enable,
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output Ack_oa,
input [7:0] interrupt_in,
output reg osc_clk,
input int_acknowledged,
input clear_all,
output assert_interrupt);
parameter dly = 1;
parameter int_reg_addr = 2'b00;
parameter mask_reg_addr = 2'b01;
parameter fpga_status_reg_addr = 2'b10;
parameter new_int_mode_addr = 2'b11;
reg [7:0] mask_reg, int_masked_old; //if a 1 is in position i than the i_th interrupt is masked
wire [7:0] int_masked, interrupt;
reg [2:0] int_pointer_r, int_pointer_w;
wire clear_int;
reg [7:0] int_fifo [7:0];
reg fifo_full, fifo_empty;
wire asynch_clk_change;
reg hs_int_mode;
wire int_in_fifo;
reg rora_roak;
reg ready4int;
reg [3:0] int_counter;
reg Stb_d;
always @(posedge Clk_ik)
if (Rst_irq) Stb_d <= # dly 1'b0;
else Stb_d <= # dly Stb_i;
wire NewStb_a = Stb_i && ~Stb_d;
assign clear_int = Cyc_i && ~We_i && NewStb_a && Adr_ib2==int_reg_addr;
always @(posedge Clk_ik) begin
if (Rst_irq) begin
{hs_int_mode, ready4int, rora_roak, mask_reg} <= # dly 11'h2ff;
end else if (Cyc_i && We_i && Stb_i && Adr_ib2==mask_reg_addr) begin
{hs_int_mode, ready4int, rora_roak, mask_reg} <= # dly Dat_ib32[10:0];
end else if (hs_int_mode && ((rora_roak && Cyc_i && ~We_i && Stb_i && Adr_ib2==int_reg_addr) || (~rora_roak && int_acknowledged))) begin
ready4int <= # dly 1'b0;
end
end
assign asynch_clk_change = clrn && ~interrupt_in[6];
initial osc_clk = 1;
always @(posedge Clk_ik or negedge asynch_clk_change) begin
if (~asynch_clk_change) begin
osc_clk <= # dly 1'b1;
end else if (Cyc_i && We_i && Stb_i && Adr_ib2==mask_reg_addr) begin
osc_clk <= # dly Dat_ib32[31];
end
end
assign int_masked = interrupt_in & ~mask_reg;
always @(posedge Clk_ik) begin
if (Rst_irq) begin
int_masked_old <= # dly 8'hff;
end else if (~int_enable) begin
int_masked_old <= # dly 8'hff;
end else begin
int_masked_old <= # dly int_masked;
end
end
assign interrupt = int_masked & ~int_masked_old;
assign new_interrupt = |interrupt;
always @(posedge Clk_ik) begin
if (Rst_irq) begin
int_counter <= # dly 4'h0;
end else if (~int_enable || clear_all) begin
int_counter <= # dly 4'h0;
end else begin
if (new_interrupt && ~fifo_full && ~int_acknowledged && ~&int_counter) begin
int_counter <= # dly int_counter + 1'b1;
end else if (int_acknowledged && ~(new_interrupt && ~fifo_full) && |int_counter) begin
int_counter <= # dly int_counter - 1'b1;
end
end
end
always @(posedge Clk_ik) begin
if (Rst_irq) begin
int_pointer_r <= # dly 3'h0;
int_pointer_w <= # dly 3'h0;
end else if (~int_enable || clear_all) begin
int_pointer_r <= # dly 3'h0;
int_pointer_w <= # dly 3'h0;
end else begin
if (new_interrupt && ~fifo_full) begin
int_pointer_w <= # dly int_pointer_w + 1'b1;
end
if (clear_int && ~fifo_empty) begin
int_pointer_r <= # dly int_pointer_r + 1'b1;
end
end
end
always @(posedge Clk_ik) begin
if (Rst_irq) begin
fifo_full <= # dly 1'b0;
fifo_empty <= # dly 1'b1;
end else if (~int_enable || clear_all) begin
fifo_full <= # dly 1'b0;
fifo_empty <= # dly 1'b1;
end else begin
if ((int_pointer_w+1'b1)==int_pointer_r && new_interrupt && ~clear_int) begin
fifo_full <= # dly 1'b1;
end else if (int_pointer_w!=int_pointer_r) begin
fifo_full <= # dly 1'b0;
end
if ((int_pointer_r+1'b1)==int_pointer_w && clear_int && ~new_interrupt) begin
fifo_empty <= # dly 1'b1;
end else if (int_pointer_w!=int_pointer_r) begin
fifo_empty <= # dly 1'b0;
end
end
end
assign int_in_fifo = ~fifo_empty;
always @(posedge Clk_ik) begin
if (new_interrupt && ~fifo_full) begin
int_fifo[int_pointer_w] <= # dly interrupt;
end
end
assign assert_interrupt = int_enable && ready4int && ((|int_counter && ~rora_roak) || (int_in_fifo && rora_roak));
wire [7:0] fpga_version;
wire [7:0] fpga_revision;
wire [15:0] date;
assign fpga_version = 8'h00;
assign fpga_revision = 8'h01;
assign date = {8'd6, 4'd10,4'd10};
assign Ack_oa = Stb_i&&Cyc_i;
always @* case(Adr_ib2)
int_reg_addr : Dat_oab32 <= # dly fifo_empty ? 32'h0000_0000 : {24'h0, int_fifo[int_pointer_r]};
mask_reg_addr : Dat_oab32 <= # dly {osc_clk, int_enable, 2'h0, 1'b0, int_pointer_r, 1'b0, int_pointer_w, int_counter, 5'h0, hs_int_mode, ready4int, rora_roak, mask_reg};
fpga_status_reg_addr: Dat_oab32 <= # dly {date, fpga_version, fpga_revision};
default: Dat_oab32 <= # dly 32'hdead_beef;
endcase
endmodule
`timescale 1ns/1ns
module MAX5483Manager (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output Ack_oa,
output reg SPIUD_o,
output CS_oqn,
output reg SclkInc_oqk,
output reg Din_oq);
reg [31:0] MAX5483Reg_qb32;
reg [31:0] ClockDivider;
reg [31:0] SetBusyTime; //1200000 steps @ 100MHz = 12ms as requested in datasheet
reg FlagMAX5483SPI_q; //1 clok flag for SPI cycle
reg FlagMAX5483UD_q; //1 clock flag for UD cycle
reg [31:0] CounterClockStep_q; //Counter used for Clk divider setting -> gets out SlowClck_e
reg [31:0] Counter24Clock; //For SPI full cycle
reg [31:0] CounterXClock; //For UD -> x number of step defined by MAX5483Reg[17:8]
reg SlowClk_e; //is out of clock divider setting
reg CSspi_oqn, CSud_oqn; //CS for SPI and UD cycle
reg CSudD0_oqn, CSudD1_oqn, CSudD2_oqn; //CS with delays
reg DinSPI_oq, DinUD_oq; //Data when SPI and UD mode
reg [9:0] CounterUDStepClock; //will keep CSud down for x steps
reg MAX5483Busy_s;
reg [23:0] CounterBusy_q;
parameter dly = 1;
//#############################################
//Register ClockDivider == clock divider
//#############################################
always @(posedge Clk_ik or posedge Rst_irq)
if (Rst_irq) ClockDivider <= #dly 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b01) ClockDivider <= #dly Dat_ib32;
//#############################################
//Register SetBusyTime == 12ms fonction of the clk
//#############################################
always @(posedge Clk_ik or posedge Rst_irq)
if (Rst_irq) SetBusyTime <= #dly 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b10) SetBusyTime <= #dly Dat_ib32;
//############################################
//Reg MAX5483
//############################################
always @(posedge Clk_ik or posedge Rst_irq) begin
if (Rst_irq) MAX5483Reg_qb32 <= #dly 32'h0;
else if (Cyc_i && We_i && Stb_i && (Adr_ib2==2'b00) && Dat_ib32[24]) begin
MAX5483Reg_qb32 <= #dly Dat_ib32;
FlagMAX5483SPI_q <= #dly 1'b1;
end
else if (Cyc_i && We_i && Stb_i && (Adr_ib2==2'b00) && (Dat_ib32[24]==1'b0)) begin
MAX5483Reg_qb32 <= #dly Dat_ib32;
FlagMAX5483UD_q <= #dly 1'b1;
end
else begin
FlagMAX5483SPI_q <= #dly 1'b0;
FlagMAX5483UD_q <= #dly 1'b0;
end
end
//#############################################
//MAX5483 control pins settings SPI
//#############################################
always @(posedge Clk_ik) begin
if (MAX5483Reg_qb32[24]) SPIUD_o <= #dly 1'b1;
else SPIUD_o <= #dly 1'b0;
end
//always @(posedge Clk_ik) SclkInc_oqk <= #dly SlowClk_e;
//#############################################
//Assign Acknowledge
//#############################################
assign Ack_oa = Stb_i && Cyc_i;
//#############################################
//Read registers
//#############################################
always @* case (Adr_ib2)
2'b00: Dat_oab32 = MAX5483Reg_qb32;
2'b01: Dat_oab32 = ClockDivider;
2'b10: Dat_oab32 = SetBusyTime;
2'b11: begin Dat_oab32[0] = MAX5483Busy_s;
Dat_oab32[31:1] = 31'b0;
end
default: Dat_oab32 = 32'hDEADBEEF;
endcase
//#############################################
//Enable 'Slow' Clock generated from ClockDivider number
//#############################################
always @(posedge Clk_ik or posedge Rst_irq) begin
if ((CounterClockStep_q == ClockDivider - 1'b1) || Rst_irq) begin
SlowClk_e <= #dly 1'b1;
CounterClockStep_q <= #dly 1'b0;
end
else if (~CSspi_oqn || ~CSudD0_oqn) begin
CounterClockStep_q <= #dly CounterClockStep_q + 1'b1;
SlowClk_e <= #dly 1'b0;
end
end
//#############################################
//24 clocks cycle manager for SPI mode
//#############################################
always @(posedge Clk_ik or posedge Rst_irq) begin
if (Counter24Clock == 5'd25*ClockDivider || Rst_irq) Counter24Clock <= #dly 32'b0;
else if (|Counter24Clock || FlagMAX5483SPI_q) Counter24Clock <= #dly Counter24Clock + 1'b1;
end
always @(posedge Clk_ik or posedge Rst_irq)
if (Rst_irq) CSspi_oqn <= #dly 1'b1;
else if (MAX5483Reg_qb32[24]) CSspi_oqn <= #dly ~|Counter24Clock;
//#############################################
//X clocks cycle manager for UD mode
//#############################################
always @(posedge Clk_ik or posedge Rst_irq) begin
if (CounterXClock == (CounterUDStepClock)*ClockDivider || Rst_irq) CounterXClock <= #dly 32'b0;
else if (|CounterXClock || FlagMAX5483UD_q) CounterXClock <= #dly CounterXClock + 1'b1;
end
always @(posedge Clk_ik or posedge Rst_irq)
if (Rst_irq) CSudD0_oqn <= #dly 1'b1;
else if (MAX5483Reg_qb32[24] == 1'b0) CSudD0_oqn <= #dly ~|CounterXClock;
//#############################################
//Parallel to serial
//#############################################
reg [23:0] ParallelData;
always @(posedge Clk_ik or posedge Rst_irq) begin
if (Rst_irq) begin
ParallelData <= #dly 24'b0;
DinSPI_oq <= #dly 1'b0;
end
else if (FlagMAX5483SPI_q) ParallelData <= #dly MAX5483Reg_qb32[23:0];
else if (SlowClk_e && ~CSspi_oqn)begin
ParallelData <= #dly {ParallelData[22:0], 1'b0};
DinSPI_oq <= #dly ParallelData[23];
end
end
//#############################################
//Register MAX5483Busy_s == flag saying in use = wiper store cycle time (12ms)
//#############################################
always @(posedge Clk_ik or posedge Rst_irq)
if (CounterBusy_q == SetBusyTime || Rst_irq) CounterBusy_q <= #dly 24'b0;
else if ((MAX5483Reg_qb32[2] == 1'b1 && MAX5483Reg_qb32[3] == 1'b0) && FlagMAX5483SPI_q || |CounterBusy_q) CounterBusy_q <= #dly CounterBusy_q + 1'b1;
always @(posedge Clk_ik) MAX5483Busy_s <= #dly |CounterBusy_q;
//#############################################
//MAX5483 control pins settings
//#############################################
always @(posedge Clk_ik) begin
CounterUDStepClock <= #dly MAX5483Reg_qb32[17:8];
if (MAX5483Reg_qb32[25] == 1'b1) DinUD_oq <= #dly 1'b1; //Count up in UD mode
else if (MAX5483Reg_qb32[25] == 1'b0) DinUD_oq <= #dly 1'b0; //Count down in UD mode
end
always @(posedge Clk_ik) SclkInc_oqk <= #dly SlowClk_e;
always @(posedge Clk_ik) CSudD1_oqn <= #dly CSudD0_oqn;
always @(posedge Clk_ik) CSudD2_oqn <= #dly CSudD1_oqn;
always @* if (MAX5483Reg_qb32[26]) CSud_oqn <= ~(~CSudD0_oqn || ~CSudD2_oqn); //Store in NV in UD mode
else if (~MAX5483Reg_qb32[26]) CSud_oqn <= #dly CSudD0_oqn; //Don't store in NV in UD mode
always @(posedge Clk_ik)
if (~CSspi_oqn) Din_oq <= #dly DinSPI_oq;
else if (~CSud_oqn) Din_oq <= #dly DinUD_oq;
assign CS_oqn = ~(~CSspi_oqn || ~CSud_oqn);
endmodule
\ No newline at end of file
<
module Ser2MstWB (
output Rst_orq,
output Clk_ik,
output reg Cyc_o,
output reg We_o,
output reg [20:0] Adr_ob21,
output reg [31:0] Dat_ob32,
output Stb_o,
input [31:0] Dat_ib32,
input Ack_i,
input SerClk_ik,
input SerDat_i,
input SerCntrl_i, //We, Cyc and Adr Rst are serialized on this line
input Stb_i,
output SerClk_ok,
output SerDat_o,
output reg Ack_o);
`define dly #1
reg [31:0] SerDatIShReg_b32,
SerCntrlIShReg_b32;
reg [2:0] StbI_d3;
always @(posedge SerClk_ik) StbI_d3 <= `dly {StbI_d3[1:0], Stb_i};
wire NewStbI_a = StbI_d3[2:1]==2'b01;
always @(posedge SerClk_ik) SerDatIShReg_b32 <= `dly {SerDat_i, SerDatIShReg_b32[31:1]};
always @(posedge SerClk_ik) if (NewStbI_a) Dat_ob32 <= `dly SerDatIShReg_b32;
always @(posedge SerClk_ik) SerCntrlIShReg_b32 <= `dly {SerCntrl_i, SerCntrlIShReg_b32[31:1]};
always @(posedge SerClk_ik) if (NewStbI_a) Cyc_o <= `dly SerCntrlIShReg_b32[30];
always @(posedge SerClk_ik) if (NewStbI_a) We_o <= `dly SerCntrlIShReg_b32[29];
always @(posedge SerClk_ik) if (NewStbI_a) Adr_ob21 <= `dly SerCntrlIShReg_b32[20:0];
reg [2:0] Rst_xb3;
always @(posedge SerClk_ik or posedge Rst_orq)
if (Rst_orq) Rst_xb3[0] <= `dly 1'b0;
else if (NewStbI_a) Rst_xb3[0] <= `dly SerCntrlIShReg_b32[31];
always @(posedge Clk_ik) Rst_xb3[2:1] <= `dly Rst_xb3[1:0];
assign Rst_orq = Rst_xb3[2];
reg [1:0] StbI_xb2;
always @(posedge Clk_ik) begin
if (Rst_orq) StbI_xb2 <= `dly 2'b0;
else StbI_xb2 <= `dly {StbI_xb2[0], StbI_d3[1]};
end
assign Stb_o = StbI_xb2[1];
reg [30:0] AckI_d31;
always @(posedge Clk_ik)
if (Rst_orq) AckI_d31 <= `dly 'b0;
else AckI_d31 <= `dly {AckI_d31[29:0], Ack_i};
always @(posedge Clk_ik)
if (Rst_orq) Ack_o <= `dly 1'b0;
else Ack_o <= `dly AckI_d31[30] && Ack_i;
wire NewAckI_a = ~AckI_d31[1] && Ack_i;
reg [31:0] DatInShReg_b32;
always @(posedge Clk_ik)
if (NewAckI_a) DatInShReg_b32 <= `dly Dat_ib32;
else DatInShReg_b32 <= `dly {1'b0, DatInShReg_b32[31:1]};
assign SerDat_o = DatInShReg_b32[0];
assign SerClk_ok = ~Clk_ik;