Commit 52f1c4f3 authored by Andrea Boccardi's avatar Andrea Boccardi

clock changed to VCTXO and timeout for the VME accesses reduced

parent 3887fd24
Release 12.3 ngdbuild M.70d (nt64)
Release 12.3 ngdbuild M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3
SFpga.ngc SFpga.ngd
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc
SFpga.ngd
Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ...
Gathering constraint information from source properties...
......@@ -12,18 +12,10 @@ Done.
Annotating constraints to design from ucf file "SFpga.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:137 - Constraint <NET "VcTcXo_ik" TNM_NET = VcTcXo_ik;>
[SFpga.ucf(701)]: No appropriate instances for the TNM constraint are driven
by "VcTcXo_ik".
WARNING:ConstraintSystem:137 - Constraint <NET "VmeSysClk_ik" TNM_NET =
VmeSysClk_ik;> [SFpga.ucf(702)]: No appropriate instances for the TNM
constraint are driven by "VmeSysClk_ik".
WARNING:ConstraintSystem:194 - The TNM 'VcTcXo_ik', does not directly or
indirectly drive any flip-flops, latches and/or RAMs and is not actively used
by any referencing constraint.
WARNING:ConstraintSystem:194 - The TNM 'VmeSysClk_ik', does not directly or
indirectly drive any flip-flops, latches and/or RAMs and is not actively used
by any referencing constraint.
......@@ -55,12 +47,12 @@ Partition Implementation Status
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 18
Number of warnings: 16
Total memory usage is 155280 kilobytes
Total memory usage is 87012 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 5 sec
Writing NGDBUILD log file "SFpga.bld"...
......@@ -199,3 +199,14 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
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Release 12.3 - par M.70d (nt64)
Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Wed Jan 12 08:59:35 2011
Fri Jan 28 11:55:01 2011
# NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 par M.70d (nt64)
Release 12.3 par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Wed Jan 12 08:59:04 2011
BQPLV2:: Fri Jan 28 11:49:02 2011
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -21,16 +21,16 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 784 out of 184,304 1%
Number used as Flip Flops: 784
Number of Slice Registers: 765 out of 184,304 1%
Number used as Flip Flops: 765
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 878 out of 92,152 1%
Number used as logic: 850 out of 92,152 1%
Number using O6 output only: 621
Number of Slice LUTs: 851 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
Number using O5 and O6: 146
Number using O5 and O6: 124
Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -48,11 +48,11 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 370 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,037
Number with an unused Flip Flop: 327 out of 1,037 31%
Number with an unused LUT: 159 out of 1,037 15%
Number of fully used LUT-FF pairs: 551 out of 1,037 53%
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -73,8 +73,8 @@ Specific Feature Utilization:
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
......@@ -99,10 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 20 secs
WARNING:Par:288 - The signal DdsRamSwpOvr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<0>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -143,7 +141,6 @@ WARNING:Par:288 - The signal DdsDrOver_i_IBUF has no load. PAR will not attempt
WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsPdClk_ik_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VcTcXo_ik_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal WRLoS_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DdsSyncSmpErr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeTdi_i_IBUF has no load. PAR will not attempt to route this signal.
......@@ -157,29 +154,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 4890 unrouted; REAL time: 11 secs
Phase 1 : 4748 unrouted; REAL time: 23 secs
Phase 2 : 4350 unrouted; REAL time: 15 secs
Phase 2 : 4243 unrouted; REAL time: 30 secs
Phase 3 : 1593 unrouted; REAL time: 20 secs
Phase 3 : 1611 unrouted; REAL time: 5 mins 41 secs
Phase 4 : 1593 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Phase 4 : 1611 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 52 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Total REAL time to Router completion: 28 secs
Total CPU time to Router completion: 28 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Total REAL time to Router completion: 5 mins 56 secs
Total CPU time to Router completion: 5 mins 54 secs
Partition Implementation Status
-------------------------------
......@@ -197,12 +194,14 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 226 | 0.326 | 1.695 |
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 203 | 0.325 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.320 | 1.693 |
| Si57x_BUFG | BUFGMUX_X2Y4| No | 6 | 0.009 | 1.690 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.189 | 1.692 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/Stb_oq | Local| | 18 | 0.000 | 2.559 |
| e/Stb_oq | Local| | 17 | 0.000 | 2.404 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -221,15 +220,16 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" | SETUP | 0.479ns| 7.854ns| 0| 0
120 MHz HIGH 50% | HOLD | 0.418ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.164ns| 5.169ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.496ns| | 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.649ns| 4.684ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.439ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 5.833ns| 2.500ns| 0| 0
20 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" | SETUP | 6.152ns| 2.181ns| 0| 0
120 MHz HIGH 50% | HOLD | 0.464ns| | 0| 0
| MINPERIOD | 5.833ns| 2.500ns| 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
......@@ -239,20 +239,20 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 50 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 49 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 31 secs
Total REAL time to PAR completion: 5 mins 59 secs
Total CPU time to PAR completion: 5 mins 58 secs
Peak Memory Usage: 549 MB
Peak Memory Usage: 366 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 52
Number of info messages: 1
Number of warning messages: 51
Number of info messages: 0
Writing design to file SFpga.ncd
......
//! **************************************************************************
// Written by: Map M.70d on Wed Jan 12 08:59:01 2011
// Written by: Map M.70d on Fri Jan 28 11:48:58 2011
//! **************************************************************************
SCHEMATIC START;
......@@ -280,8 +280,8 @@ COMP "WRTxDisable_o" LOCATE = SITE "K5" LEVEL 1;
COMP "ManualAddress_ib5<4>" LOCATE = SITE "P10" LEVEL 1;
COMP "PllFmc2RefSel_o" LOCATE = SITE "V13" LEVEL 1;
COMP "FlashAFpgaQ_i" LOCATE = SITE "AA18" LEVEL 1;
COMP "VcTcXo_ik" LOCATE = SITE "AF14" LEVEL 1;
COMP "PllFmc1Reset_orn" LOCATE = SITE "AC5" LEVEL 1;
COMP "VcTcXo_ik" LOCATE = SITE "AF14" LEVEL 1;
COMP "SysAppClk_ok" LOCATE = SITE "R7" LEVEL 1;
COMP "WRLoS_i" LOCATE = SITE "L6" LEVEL 1;
COMP "PllSysRefMon_i" LOCATE = SITE "AD14" LEVEL 1;
......@@ -346,698 +346,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "i_Core/Rst_rq" BEL
"i_Core/i_VmeInterface/State_q_FSM_FFd2" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_29" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_28" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_27" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_26" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_25" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_24" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_23" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_22" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_21" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_20" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_19" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_18" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_17" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_16" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_15" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_14" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_13" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_12" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_11" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_10" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_9" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_8" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_7" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_6" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_5" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_4" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_3" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_2" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_1" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_0" BEL
"i_Core/i_VmeInterface/State_q_FSM_FFd1" BEL
"i_Core/i_VmeInterface/Dat_obq32_31" BEL
"i_Core/i_VmeInterface/Dat_obq32_30" BEL
"i_Core/i_VmeInterface/Dat_obq32_29" BEL
"i_Core/i_VmeInterface/Dat_obq32_28" BEL
"i_Core/i_VmeInterface/Dat_obq32_27" BEL
"i_Core/i_VmeInterface/Dat_obq32_26" BEL
"i_Core/i_VmeInterface/Dat_obq32_25" BEL
"i_Core/i_VmeInterface/Dat_obq32_24" BEL
"i_Core/i_VmeInterface/Dat_obq32_23" BEL
"i_Core/i_VmeInterface/Dat_obq32_22" BEL
"i_Core/i_VmeInterface/Dat_obq32_21" BEL
"i_Core/i_VmeInterface/Dat_obq32_20" BEL
"i_Core/i_VmeInterface/Dat_obq32_19" BEL
"i_Core/i_VmeInterface/Dat_obq32_18" BEL
"i_Core/i_VmeInterface/Dat_obq32_17" BEL
"i_Core/i_VmeInterface/Dat_obq32_16" BEL
"i_Core/i_VmeInterface/Dat_obq32_15" BEL
"i_Core/i_VmeInterface/Dat_obq32_14" BEL
"i_Core/i_VmeInterface/Dat_obq32_13" BEL
"i_Core/i_VmeInterface/Dat_obq32_12" BEL
"i_Core/i_VmeInterface/Dat_obq32_11" BEL
"i_Core/i_VmeInterface/Dat_obq32_10" BEL
"i_Core/i_VmeInterface/Dat_obq32_9" BEL
"i_Core/i_VmeInterface/Dat_obq32_8" BEL
"i_Core/i_VmeInterface/Dat_obq32_7" BEL
"i_Core/i_VmeInterface/Dat_obq32_6" BEL
"i_Core/i_VmeInterface/Dat_obq32_5" BEL
"i_Core/i_VmeInterface/Dat_obq32_4" BEL
"i_Core/i_VmeInterface/Dat_obq32_3" BEL
"i_Core/i_VmeInterface/Dat_obq32_2" BEL
"i_Core/i_VmeInterface/Dat_obq32_1" BEL
"i_Core/i_VmeInterface/Dat_obq32_0" BEL
"i_Core/i_VmeInterface/VmeDtAck_oqn" BEL
"i_Core/i_VmeInterface/Adr_obq22_21" BEL
"i_Core/i_VmeInterface/Adr_obq22_20" BEL
"i_Core/i_VmeInterface/Adr_obq22_19" BEL
"i_Core/i_VmeInterface/Adr_obq22_18" BEL
"i_Core/i_VmeInterface/Adr_obq22_17" BEL
"i_Core/i_VmeInterface/Adr_obq22_16" BEL
"i_Core/i_VmeInterface/Adr_obq22_15" BEL
"i_Core/i_VmeInterface/Adr_obq22_14" BEL
"i_Core/i_VmeInterface/Adr_obq22_13" BEL
"i_Core/i_VmeInterface/Adr_obq22_12" BEL
"i_Core/i_VmeInterface/Adr_obq22_11" BEL
"i_Core/i_VmeInterface/Adr_obq22_10" BEL
"i_Core/i_VmeInterface/Adr_obq22_9" BEL
"i_Core/i_VmeInterface/Adr_obq22_8" BEL
"i_Core/i_VmeInterface/Adr_obq22_7" BEL
"i_Core/i_VmeInterface/Adr_obq22_6" BEL
"i_Core/i_VmeInterface/Adr_obq22_5" BEL
"i_Core/i_VmeInterface/Adr_obq22_4" BEL
"i_Core/i_VmeInterface/Adr_obq22_3" BEL
"i_Core/i_VmeInterface/Adr_obq22_2" BEL
"i_Core/i_VmeInterface/Adr_obq22_1" BEL
"i_Core/i_VmeInterface/Adr_obq22_0" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_7" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_6" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_5" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_4" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_3" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_2" BEL
"i_Core/i_VmeInterface/VmeIrqn_oqnb7_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_19" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_18" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_17" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_16" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_15" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_14" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_13" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_12" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_11" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_10" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_9" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_8" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_7" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_6" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_5" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_4" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_3" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_2" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL
"i_Core/i_Debouncer/Counter_c_12" BEL
"i_Core/i_Debouncer/Counter_c_11" BEL
"i_Core/i_Debouncer/Counter_c_10" BEL "i_Core/i_Debouncer/Counter_c_9"
BEL "i_Core/i_Debouncer/Counter_c_8" BEL
"i_Core/i_Debouncer/Counter_c_7" BEL "i_Core/i_Debouncer/Counter_c_6"
BEL "i_Core/i_Debouncer/Counter_c_5" BEL
"i_Core/i_Debouncer/Counter_c_4" BEL "i_Core/i_Debouncer/Counter_c_3"
BEL "i_Core/i_Debouncer/Counter_c_2" BEL
"i_Core/i_Debouncer/Counter_c_1" BEL "i_Core/i_Debouncer/Counter_c_0"
BEL "i_Core/i_InterruptManager/int_pointer_w_2" BEL
"i_Core/i_InterruptManager/int_pointer_w_1" BEL
"i_Core/i_InterruptManager/int_pointer_w_0" BEL
"i_Core/i_InterruptManager/int_pointer_r_2" BEL
"i_Core/i_InterruptManager/int_pointer_r_1" BEL
"i_Core/i_InterruptManager/int_pointer_r_0" BEL
"i_Core/i_InterruptManager/osc_clk" BEL
"i_Core/i_InterruptManager/mask_reg_7" BEL
"i_Core/i_InterruptManager/mask_reg_6" BEL
"i_Core/i_InterruptManager/mask_reg_5" BEL
"i_Core/i_InterruptManager/mask_reg_4" BEL
"i_Core/i_InterruptManager/mask_reg_3" BEL
"i_Core/i_InterruptManager/mask_reg_2" BEL
"i_Core/i_InterruptManager/mask_reg_1" BEL
"i_Core/i_InterruptManager/mask_reg_0" BEL
"i_Core/i_InterruptManager/hs_int_mode" BEL
"i_Core/i_InterruptManager/int_masked_old_7" BEL
"i_Core/i_InterruptManager/int_masked_old_6" BEL
"i_Core/i_InterruptManager/int_masked_old_5" BEL
"i_Core/i_InterruptManager/int_masked_old_4" BEL
"i_Core/i_InterruptManager/int_masked_old_3" BEL
"i_Core/i_InterruptManager/int_masked_old_2" BEL
"i_Core/i_InterruptManager/int_masked_old_1" BEL
"i_Core/i_InterruptManager/int_masked_old_0" BEL
"i_Core/i_InterruptManager/Stb_d" BEL
"i_Core/i_InterruptManager/rora_roak" BEL
"i_Core/i_AddressDecoderWB/StbSlv2SerWB_o" BEL
"i_Core/i_AddressDecoderWB/StbSpiMaster_o" BEL
"i_Core/i_AddressDecoderWB/Ack_o" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_31" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_30" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_29" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_28" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_27" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_26" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_25" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_24" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_23" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_22" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_21" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_20" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_19" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_18" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_17" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_16" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_15" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_14" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_13" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_12" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_11" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_10" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_9" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_8" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_7" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_6" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_5" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_4" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_3" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_2" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_1" BEL
"i_Core/i_AddressDecoderWB/Dat_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg2Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg3Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg1Value_ob32_0" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_31" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_30" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_29" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_28" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_27" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_26" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_25" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_24" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_23" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_22" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_21" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_20" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_19" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_18" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_17" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_16" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_15" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_14" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_13" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_12" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_11" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_10" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_9" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_8" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_7" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_6" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_5" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_4" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_3" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_2" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_1" BEL
"i_Core/i_Generic4OutputRegs/Reg0Value_ob32_0" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_31" BEL "i_Core/i_Slv2SerWB/Dat_ob32_30"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_29" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_28" BEL "i_Core/i_Slv2SerWB/Dat_ob32_27"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_26" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_25" BEL "i_Core/i_Slv2SerWB/Dat_ob32_24"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_23" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_22" BEL "i_Core/i_Slv2SerWB/Dat_ob32_21"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_20" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_19" BEL "i_Core/i_Slv2SerWB/Dat_ob32_18"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_17" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_16" BEL "i_Core/i_Slv2SerWB/Dat_ob32_15"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_14" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_13" BEL "i_Core/i_Slv2SerWB/Dat_ob32_12"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_11" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_10" BEL "i_Core/i_Slv2SerWB/Dat_ob32_9"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_8" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_7" BEL "i_Core/i_Slv2SerWB/Dat_ob32_6"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_5" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_4" BEL "i_Core/i_Slv2SerWB/Dat_ob32_3"
BEL "i_Core/i_Slv2SerWB/Dat_ob32_2" BEL
"i_Core/i_Slv2SerWB/Dat_ob32_1" BEL "i_Core/i_Slv2SerWB/Dat_ob32_0"
BEL "i_Core/i_Slv2SerWB/Ack_o" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/StbShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/CntrlShReg_b32_0" BEL "i_Core/i_Slv2SerWB/StbI_d"
BEL "i_Core/i_Slv2SerWB/DatOutShReg_b32_31" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/DatOutShReg_b32_0" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd2" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd3" BEL
"i_Core/i_SpiMasterWB/WriteAck_q" BEL
"i_Core/i_SpiMasterWB/WaitingNewData_o" BEL
"i_Core/i_SpiMasterWB/ModuleIdle_o" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_15" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_14" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_13" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_12" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_11" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_10" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_9" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_8" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_7" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_6" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_5" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_4" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_3" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_2" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_1" BEL
"i_Core/i_SpiMasterWB/TimeCounter_cb16_0" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_11" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_10" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_9" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_8" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_7" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_6" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_5" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_4" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_3" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_2" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_1" BEL
"i_Core/i_SpiMasterWB/TxCounter_cb12_0" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_31" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_30" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_29" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_28" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_27" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_26" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_25" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_24" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_23" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_22" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_21" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_20" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_19" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_18" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_17" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_16" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_15" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_14" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_13" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_12" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_11" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_10" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_9" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_8" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_7" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_6" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_5" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_4" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_3" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_2" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_1" BEL
"i_Core/i_SpiMasterWB/Config2_qb32_0" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_31" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_30" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_29" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_28" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_27" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_26" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_25" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_24" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_23" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_22" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_21" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_20" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_19" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_18" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_17" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_16" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_15" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_14" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_13" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_12" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_11" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_10" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_9" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_8" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_7" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_6" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_5" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_4" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_3" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_2" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_1" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_0" BEL
"i_Core/i_VmeInterface/VmeDataDir_oq" BEL
"i_Core/i_VmeInterface/VmeDataOe_oq" BEL
"i_Core/i_InterruptManager/fifo_full" BEL
"i_Core/i_VmeInterface/VmeDataRegOe" BEL
"i_Core/i_VmeInterface/Stb_oq" BEL "i_Core/i_VmeInterface/ClearInt_op"
BEL "i_Core/i_VmeInterface/We_oq" BEL
"i_Core/i_VmeInterface/VmeIAckOutn_oqn" BEL
"i_Core/i_SpiMasterWB/SClk_o" BEL "i_Core/i_SpiMasterWB/SS_onb32_1"
BEL "i_Core/i_SpiMasterWB/SS_onb32_2" BEL
"i_Core/i_SpiMasterWB/SS_onb32_0" BEL
"i_Core/i_SpiMasterWB/SS_onb32_4" BEL
"i_Core/i_SpiMasterWB/SS_onb32_5" BEL
"i_Core/i_SpiMasterWB/SS_onb32_3" BEL
"i_Core/i_SpiMasterWB/SS_onb32_6" BEL
"i_Core/i_SpiMasterWB/SS_onb32_7" BEL
"i_Core/i_SpiMasterWB/SS_onb32_8" BEL "i_Core/i_SpiMasterWB/StartTx_q"
BEL "i_Core/i_VmeAccessMonostable/SynchOutput_oq" BEL
"i_Core/i_Debouncer/DebouncedSignal_oq" BEL
"i_Core/i_AddressDecoderWB/StbGenericOutputRegs_o" BEL
"i_Core/i_AddressDecoderWB/StbIntManager_o" BEL
"i_Core/i_Debouncer/State_q" BEL "i_Core/i_InterruptManager/ready4int"
BEL "i_Core/i_InterruptManager/fifo_empty" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_31" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_30" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_29" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_28" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_27" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_26" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_25" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_24" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_23" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_22" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_21" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_20" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_19" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_18" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_17" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_16" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_15" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_14" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_13" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_12" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_11" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_10" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_9" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_8" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_7" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_6" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_5" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_4" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_3" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_2" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_1" BEL
"i_Core/i_SpiMasterWB/ShiftIn_qb32_0" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_31" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_30" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_29" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_28" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_27" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_26" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_25" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_24" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_23" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_22" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_21" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_20" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_19" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_18" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_17" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_16" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_15" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_14" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_13" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_12" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_11" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_10" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_9" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_8" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_7" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_6" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_5" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_4" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_3" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_2" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_1" BEL
"i_Core/i_SpiMasterWB/ShiftOut_qb32_0" BEL
"i_Core/i_InterruptManager/int_counter_3" BEL
"i_Core/i_InterruptManager/int_counter_1" BEL
"i_Core/i_InterruptManager/int_counter_0" BEL
"i_Core/i_InterruptManager/int_counter_2" BEL
"i_Core/i_VmeInterface/Adr_obq22_0_1" BEL
"i_Core/i_VmeInterface/Adr_obq22_2_1" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_29_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd1_1" BEL
"i_Core/i_VmeInterface/Adr_obq22_1_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd2_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd3_1" BEL "Si57x_BUFG" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_31" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_30" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_29" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_28" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_27" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_26" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_25" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_24" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_23" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_22" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_21" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_20" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_19" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_18" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_17" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_16" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_15" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_14" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_13" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_12" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_11" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_10" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_9" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_8" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_7" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_6" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_5" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_4" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_3" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_2" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_1" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_0" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_VmeInterface/Mshreg_Ds1Shr_dq_2" BEL
"i_Core/i_VmeInterface/Ds1Shr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_IAckInShr_dq_2" BEL
"i_Core/i_VmeInterface/IAckInShr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_AsShr_dq_2" BEL
"i_Core/i_VmeInterface/AsShr_dq_2" BEL
"i_Core/i_VmeInterface/Mshreg_Ds2Shr_dq_2" BEL
"i_Core/i_VmeInterface/Ds2Shr_dq_2" BEL
"i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/SP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo22/DP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo22/SP" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMA" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMB_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMB" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
......@@ -1050,38 +359,17 @@ TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_6" BEL "i_Core/Si57xDivider_c_5" BEL
"i_Core/Si57xDivider_c_4" BEL "i_Core/Si57xDivider_c_3" BEL
"i_Core/Si57xDivider_c_2" BEL "i_Core/Si57xDivider_c_1" BEL
"i_Core/Si57xDivider_c_0" BEL "i_Core/Rst_rq" BEL
"i_Core/Si57xDivider_c_0" BEL "Si57x_BUFG";
TIMEGRP VcTcXo_ik = BEL "i_Core/Rst_rq" BEL
"i_Core/i_VmeInterface/State_q_FSM_FFd2" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_29" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_28" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_27" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_26" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_25" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_24" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_23" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_22" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_21" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_20" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_19" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_18" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_17" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_16" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_15" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_14" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_13" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_12" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_11" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_10" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_9" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_8" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_7" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_6" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_5" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_4" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_3" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_2" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_1" BEL
"i_Core/i_VmeInterface/TimoutCounter_cb30_0" BEL
"i_Core/i_VmeInterface/TimeoutCounter_cb8_7" BEL
"i_Core/i_VmeInterface/TimeoutCounter_cb8_6" BEL
"i_Core/i_VmeInterface/TimeoutCounter_cb8_5" BEL
"i_Core/i_VmeInterface/TimeoutCounter_cb8_4" BEL
"i_Core/i_VmeInterface/TimeoutCounter_cb8_3" BEL
"i_Core/i_VmeInterface/TimeoutCounter_cb8_2" BEL
"i_Core/i_VmeInterface/TimeoutCounter_cb8_1" BEL
"i_Core/i_VmeInterface/TimeoutCounter_cb8_0" BEL
"i_Core/i_VmeInterface/State_q_FSM_FFd1" BEL
"i_Core/i_VmeInterface/Dat_obq32_31" BEL
"i_Core/i_VmeInterface/Dat_obq32_30" BEL
......@@ -1602,6 +890,7 @@ TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_SpiMasterWB/SS_onb32_8" BEL "i_Core/i_SpiMasterWB/StartTx_q"
BEL "i_Core/i_VmeAccessMonostable/SynchOutput_oq" BEL
"i_Core/i_Debouncer/DebouncedSignal_oq" BEL
"i_Core/i_AddressDecoderWB/StbGenericInputRegs_o" BEL
"i_Core/i_AddressDecoderWB/StbGenericOutputRegs_o" BEL
"i_Core/i_AddressDecoderWB/StbIntManager_o" BEL
"i_Core/i_Debouncer/State_q" BEL "i_Core/i_InterruptManager/ready4int"
......@@ -1677,11 +966,13 @@ TIMEGRP Si57x_ikn = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_VmeInterface/Adr_obq22_0_1" BEL
"i_Core/i_VmeInterface/Adr_obq22_2_1" BEL
"i_Core/i_SpiMasterWB/Config1_qb32_29_1" BEL
"i_Core/i_VmeInterface/Stb_oq_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd1_1" BEL
"i_Core/i_VmeInterface/Adr_obq22_0_2" BEL
"i_Core/i_VmeInterface/Adr_obq22_1_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd2_1" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd3_1" BEL "Si57x_BUFG" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_31" BEL
"i_Core/i_SpiMasterWB/State_q_FSM_FFd3_1" BEL "VcTcXo_ik_IBUF_BUFG"
BEL "i_Core/i_VmeInterface/VmeDataReg_qb32_31" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_30" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_29" BEL
"i_Core/i_VmeInterface/VmeDataReg_qb32_28" BEL
......
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.479" best="7.854" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.418" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.164" best="5.169" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.496" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.649" best="4.684" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.439" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="6.152" best="2.181" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.464" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
Release 12.3 - xst M.70d (nt64)
Release 12.3 - xst M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
--> Reading design: SFpga.prj
......@@ -235,7 +235,6 @@ WARNING:Xst:647 - Input <VmeTck_i> is never used. This port will be preserved an
WARNING:Xst:647 - Input <VmeTrst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTdi_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VmeTms_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VcTcXo_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AFpgaProgDone_io> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllFmc12SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PllFmc22SFpga_ik> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
......@@ -380,7 +379,7 @@ Synthesizing Unit <VmeToWishBone>.
Found 1-bit register for signal <VmeDataDir_oq>.
Found 1-bit register for signal <ClearInt_op>.
Found 1-bit register for signal <VmeIAckOutn_oqn>.
Found 30-bit register for signal <TimoutCounter_cb30>.
Found 8-bit register for signal <TimeoutCounter_cb8>.
Found 3-bit register for signal <Ds1Shr_dq>.
Found finite state machine <FSM_0> for signal <State_q>.
-----------------------------------------------------------------------
......@@ -395,7 +394,7 @@ Synthesizing Unit <VmeToWishBone>.
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 30-bit adder for signal <TimoutCounter_cb30[29]_GND_35_o_add_49_OUT> created at line 184.
Found 8-bit adder for signal <TimeoutCounter_cb8[7]_GND_35_o_add_49_OUT> created at line 184.
Found 1-bit 4-to-1 multiplexer for signal <State_q[1]_VmeDataRegOe_Mux_54_o> created at line 126.
Found 1-bit tristate buffer for signal <VmeData_iozb32<31>> created at line 109
Found 1-bit tristate buffer for signal <VmeData_iozb32<30>> created at line 109
......@@ -433,7 +432,7 @@ Synthesizing Unit <VmeToWishBone>.
Found 3-bit comparator equal for signal <ValidIntAckBA_a> created at line 63
Summary:
inferred 1 Adder/Subtractor(s).
inferred 144 D-type flip-flop(s).
inferred 122 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 21 Multiplexer(s).
inferred 32 Tristate(s).
......@@ -480,7 +479,6 @@ Unit <InterruptManagerWB> synthesized.
Synthesizing Unit <AddressDecoderWBSys>.
Related source file is "/vfc_svn/hdl/design/addrdecoderwbsys.v".
WARNING:Xst:647 - Input <Adr_ib22<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AckGenericInputRegs_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 32-bit register for signal <Dat_ob32>.
Found 1-bit register for signal <StbIntManager_o>.
Found 1-bit register for signal <StbGenericOutputRegs_o>.
......@@ -622,8 +620,8 @@ Macro Statistics
23-bit adder : 1
24-bit adder : 1
3-bit adder : 2
30-bit adder : 1
4-bit addsub : 1
8-bit adder : 1
# Registers : 107
1-bit register : 69
12-bit register : 1
......@@ -633,12 +631,11 @@ Macro Statistics
23-bit register : 1
24-bit register : 1
3-bit register : 8
30-bit register : 1
31-bit register : 1
32-bit register : 16
4-bit register : 2
7-bit register : 1
8-bit register : 2
8-bit register : 3
# Comparators : 9
1-bit comparator equal : 1
12-bit comparator equal : 1
......@@ -652,11 +649,11 @@ Macro Statistics
12-bit 2-to-1 multiplexer : 2
16-bit 2-to-1 multiplexer : 8
22-bit 2-to-1 multiplexer : 3
30-bit 2-to-1 multiplexer : 1
32-bit 2-to-1 multiplexer : 21
32-bit 4-to-1 multiplexer : 3
32-bit 7-to-1 multiplexer : 1
5-bit 2-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 1
# Tristates : 64
1-bit tristate buffer : 64
# FSMs : 2
......@@ -706,7 +703,7 @@ The following registers are absorbed into counter <Si57xDivider_c>: 1 register o
Unit <SystemFpga> synthesized (advanced).
Synthesizing (advanced) Unit <VmeToWishBone>.
The following registers are absorbed into counter <TimoutCounter_cb30>: 1 register on signal <TimoutCounter_cb30>.
The following registers are absorbed into counter <TimeoutCounter_cb8>: 1 register on signal <TimeoutCounter_cb8>.
Unit <VmeToWishBone> synthesized (advanced).
=========================================================================
......@@ -724,8 +721,8 @@ Macro Statistics
23-bit up counter : 1
24-bit up counter : 1
3-bit up counter : 2
30-bit up counter : 1
4-bit updown counter : 1
8-bit up counter : 1
# Registers : 709
Flip-Flops : 709
# Comparators : 9
......@@ -795,7 +792,6 @@ Optimizing unit <Generic4OutputRegs> ...
Optimizing unit <Slv2SerWB> ...
Optimizing unit <SpiMasterWB> ...
WARNING:Xst:2677 - Node <i_Core/i_AddressDecoderWB/StbGenericInputRegs_o> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_9> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_10> of sequential type is unconnected in block <SFpga>.
WARNING:Xst:2677 - Node <i_Core/i_SpiMasterWB/SS_onb32_11> of sequential type is unconnected in block <SFpga>.
......@@ -827,9 +823,10 @@ FlipFlop i_Core/i_SpiMasterWB/Config1_qb32_29 has been replicated 1 time(s)
FlipFlop i_Core/i_SpiMasterWB/State_q_FSM_FFd1 has been replicated 1 time(s)
FlipFlop i_Core/i_SpiMasterWB/State_q_FSM_FFd2 has been replicated 1 time(s)
FlipFlop i_Core/i_SpiMasterWB/State_q_FSM_FFd3 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/Adr_obq22_0 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/Adr_obq22_0 has been replicated 2 time(s)
FlipFlop i_Core/i_VmeInterface/Adr_obq22_1 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/Adr_obq22_2 has been replicated 1 time(s)
FlipFlop i_Core/i_VmeInterface/Stb_oq has been replicated 1 time(s)
Final Macro Processing ...
......@@ -848,8 +845,8 @@ Unit <SFpga> processed.
Final Register Report
Macro Statistics
# Registers : 776
Flip-Flops : 776
# Registers : 757
Flip-Flops : 757
# Shift Registers : 8
2-bit shift register : 2
3-bit shift register : 6
......@@ -875,25 +872,25 @@ Top Level Output File Name : SFpga.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1235
# BELS : 1163
# GND : 1
# INV : 22
# LUT1 : 86
# LUT2 : 211
# LUT3 : 149
# LUT4 : 85
# LUT5 : 123
# LUT6 : 284
# MUXCY : 128
# MUXF7 : 24
# LUT3 : 129
# LUT4 : 86
# LUT5 : 121
# LUT6 : 279
# MUXCY : 106
# MUXF7 : 22
# VCC : 1
# XORCY : 121
# FlipFlops/Latches : 784
# FD : 165
# XORCY : 99
# FlipFlops/Latches : 765
# FD : 166
# FDE : 104
# FDPE : 1
# FDR : 170
# FDRE : 310
# FDR : 149
# FDRE : 311
# FDS : 26
# FDSE : 8
# RAMS : 3
......@@ -901,11 +898,11 @@ Primitive and Black Box Usage:
# RAM32M : 1
# Shift Registers : 8
# SRLC16E : 8
# Clock Buffers : 2
# BUFG : 1
# Clock Buffers : 3
# BUFG : 2
# BUFGP : 1
# IO Buffers : 304
# IBUF : 77
# IO Buffers : 305
# IBUF : 78
# IBUFGDS : 6
# IOBUF : 32
# IOBUFDS : 2
......@@ -920,26 +917,26 @@ Selected Device : 6slx150tfgg676-3
Slice Logic Utilization:
Number of Slice Registers: 784 out of 184304 0%
Number of Slice LUTs: 976 out of 92152 1%
Number used as Logic: 960 out of 92152 1%
Number of Slice Registers: 765 out of 184304 0%
Number of Slice LUTs: 950 out of 92152 1%
Number used as Logic: 934 out of 92152 1%
Number used as Memory: 16 out of 21680 0%
Number used as RAM: 8
Number used as SRL: 8
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1206
Number with an unused Flip Flop: 422 out of 1206 34%
Number with an unused LUT: 230 out of 1206 19%
Number of fully used LUT-FF pairs: 554 out of 1206 45%
Number of unique control sets: 25
Number of LUT Flip Flop pairs used: 1182
Number with an unused Flip Flop: 417 out of 1182 35%
Number with an unused LUT: 232 out of 1182 19%
Number of fully used LUT-FF pairs: 533 out of 1182 45%
Number of unique control sets: 26
IO Utilization:
Number of IOs: 365
Number of bonded IOBs: 316 out of 396 79%
Number of bonded IOBs: 317 out of 396 80%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
Number of BUFG/BUFGCTRLs: 3 out of 16 18%
---------------------------
Partition Resource Summary:
......@@ -962,7 +959,8 @@ Clock Information:
-----------------------------------+-----------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+-----------------------------------------------+-------+
Si57x_ik | IBUFGDS+BUFG | 726 |
Si57x_ik | IBUFGDS+BUFG | 24 |
VcTcXo_ik | IBUF+BUFG | 683 |
i_Core/i_VmeInterface/Stb_oq | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax)| 1 |
SysAppClk_ik | BUFGP | 68 |
-----------------------------------+-----------------------------------------------+-------+
......@@ -977,8 +975,8 @@ Timing Summary:
Speed Grade: -3
Minimum period: 6.551ns (Maximum Frequency: 152.654MHz)
Minimum input arrival time before clock: 12.165ns
Maximum output required time after clock: 6.177ns
Minimum input arrival time before clock: 12.206ns
Maximum output required time after clock: 6.172ns
Maximum combinational path delay: 6.926ns
Timing Details:
......@@ -987,14 +985,60 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'Si57x_ik'
Clock period: 2.365ns (frequency: 422.770MHz)
Total number of paths / destination ports: 300 / 24
-------------------------------------------------------------------------
Delay: 2.365ns (Levels of Logic = 25)
Source: i_Core/Si57xDivider_c_0 (FF)
Destination: i_Core/Si57xDivider_c_23 (FF)
Source Clock: Si57x_ik rising
Destination Clock: Si57x_ik rising
Data Path: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_23
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.525 0.579 i_Core/Si57xDivider_c_0 (i_Core/Si57xDivider_c_0)
INV:I->O 1 0.255 0.000 i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0 (i_Core/Mcount_Si57xDivider_c_lut<0>)
MUXCY:S->O 1 0.215 0.000 i_Core/Mcount_Si57xDivider_c_cy<0> (i_Core/Mcount_Si57xDivider_c_cy<0>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<1> (i_Core/Mcount_Si57xDivider_c_cy<1>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<2> (i_Core/Mcount_Si57xDivider_c_cy<2>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<3> (i_Core/Mcount_Si57xDivider_c_cy<3>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<4> (i_Core/Mcount_Si57xDivider_c_cy<4>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<5> (i_Core/Mcount_Si57xDivider_c_cy<5>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<6> (i_Core/Mcount_Si57xDivider_c_cy<6>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<7> (i_Core/Mcount_Si57xDivider_c_cy<7>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<8> (i_Core/Mcount_Si57xDivider_c_cy<8>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<9> (i_Core/Mcount_Si57xDivider_c_cy<9>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<10> (i_Core/Mcount_Si57xDivider_c_cy<10>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<11> (i_Core/Mcount_Si57xDivider_c_cy<11>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<12> (i_Core/Mcount_Si57xDivider_c_cy<12>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<13> (i_Core/Mcount_Si57xDivider_c_cy<13>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<14> (i_Core/Mcount_Si57xDivider_c_cy<14>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<15> (i_Core/Mcount_Si57xDivider_c_cy<15>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<16> (i_Core/Mcount_Si57xDivider_c_cy<16>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<17> (i_Core/Mcount_Si57xDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<18> (i_Core/Mcount_Si57xDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<19> (i_Core/Mcount_Si57xDivider_c_cy<19>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<20> (i_Core/Mcount_Si57xDivider_c_cy<20>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<21> (i_Core/Mcount_Si57xDivider_c_cy<21>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_Si57xDivider_c_cy<22> (i_Core/Mcount_Si57xDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_Si57xDivider_c_xor<23> (i_Core/Result<23>)
FD:D 0.074 i_Core/Si57xDivider_c_23
----------------------------------------
Total 2.365ns (1.787ns logic, 0.579ns route)
(75.5% logic, 24.5% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 6.551ns (frequency: 152.654MHz)
Total number of paths / destination ports: 30716 / 1604
Total number of paths / destination ports: 26774 / 1542
-------------------------------------------------------------------------
Delay: 6.551ns (Levels of Logic = 10)
Source: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_31 (FF)
Source Clock: Si57x_ik rising
Destination Clock: Si57x_ik rising
Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising
Data Path: i_Core/i_SpiMasterWB/Config2_qb32_2 to i_Core/i_SpiMasterWB/ShiftIn_qb32_31
Gate Net
......@@ -1061,15 +1105,15 @@ Delay: 3.056ns (Levels of Logic = 1)
(35.2% logic, 64.8% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Si57x_ik'
Total number of paths / destination ports: 8529 / 94
Timing constraint: Default OFFSET IN BEFORE for Clock 'VcTcXo_ik'
Total number of paths / destination ports: 9238 / 96
-------------------------------------------------------------------------
Offset: 12.165ns (Levels of Logic = 11)
Offset: 12.206ns (Levels of Logic = 10)
Source: VmeGa_ib5n<0> (PAD)
Destination: i_Core/i_VmeInterface/VmeIAckOutn_oqn (FF)
Destination Clock: Si57x_ik rising
Destination: i_Core/i_VmeInterface/Dat_obq32_31 (FF)
Destination Clock: VcTcXo_ik rising
Data Path: VmeGa_ib5n<0> to i_Core/i_VmeInterface/VmeIAckOutn_oqn
Data Path: VmeGa_ib5n<0> to i_Core/i_VmeInterface/Dat_obq32_31
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
......@@ -1077,17 +1121,16 @@ Offset: 12.165ns (Levels of Logic = 11)
LUT6:I1->O 6 0.254 0.973 i_Core/i_VmeInterface/GapError1 (i_Core/i_VmeInterface/GapError)
LUT4:I1->O 1 0.235 1.035 i_Core/i_VmeInterface/Mmux_BoardBaseAddr_b521 (i_Core/i_VmeInterface/BoardBaseAddr_b5<1>)
LUT6:I0->O 1 0.254 0.808 i_Core/i_VmeInterface/ValidRWBA_a81 (i_Core/i_VmeInterface/ValidRWBA_a8)
LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N292)
LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N294)
LUT6:I0->O 3 0.254 0.879 i_Core/i_VmeInterface/ValidRWBA_a83 (i_Core/i_VmeInterface/ValidRWBA_a)
LUT4:I1->O 1 0.235 0.580 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1_SW0 (N40)
LUT6:I5->O 9 0.254 1.285 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1 (N3)
LUT6:I0->O 1 0.254 0.000 i_Core/i_VmeInterface/State_q_NextState_a[1]_PWR_5_o_equal_44_o1_F (N398)
MUXF7:I0->O 9 0.163 0.830 i_Core/i_VmeInterface/State_q_NextState_a[1]_PWR_5_o_equal_44_o1 (i_Core/i_VmeInterface/NextState_a[1]_PWR_5_o_equal_44_o)
LUT4:I3->O 1 0.254 0.000 i_Core/i_VmeInterface/Mmux_State_q[1]_VmeDataReg_qb32[31]_wide_mux_57_OUT110 (i_Core/i_VmeInterface/State_q[1]_VmeDataReg_qb32[31]_wide_mux_57_OUT<0>)
FDRE:D 0.074 i_Core/i_VmeInterface/VmeDataReg_qb32_0
LUT4:I1->O 1 0.235 0.580 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1_SW0 (N42)
LUT6:I5->O 8 0.254 1.031 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1 (N3)
LUT6:I3->O 33 0.235 1.306 i_Core/i_VmeInterface/State_q_NextState_a[1]_GND_35_o_equal_39_o1 (i_Core/i_VmeInterface/NextState_a[1]_GND_35_o_equal_39_o)
LUT5:I4->O 1 0.254 0.000 i_Core/i_VmeInterface/We_oq_rstpot (i_Core/i_VmeInterface/We_oq_rstpot)
FDR:D 0.074 i_Core/i_VmeInterface/We_oq
----------------------------------------
Total 12.165ns (3.694ns logic, 8.471ns route)
(30.4% logic, 69.6% route)
Total 12.206ns (3.512ns logic, 8.694ns route)
(28.8% logic, 71.2% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SysAppClk_ik'
......@@ -1109,28 +1152,48 @@ Offset: 1.918ns (Levels of Logic = 1)
(67.9% logic, 32.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Si57x_ik'
Total number of paths / destination ports: 149 / 92
Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik'
Total number of paths / destination ports: 148 / 92
-------------------------------------------------------------------------
Offset: 6.177ns (Levels of Logic = 2)
Offset: 6.172ns (Levels of Logic = 2)
Source: i_Core/Rst_rq (FF)
Destination: FpLed_onb8<3> (PAD)
Source Clock: Si57x_ik rising
Source Clock: VcTcXo_ik rising
Data Path: i_Core/Rst_rq to FpLed_onb8<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 569 0.525 2.104 i_Core/Rst_rq (i_Core/Rst_rq)
FD:C->Q 549 0.525 2.100 i_Core/Rst_rq (i_Core/Rst_rq)
LUT2:I1->O 1 0.254 0.579 i_Core/Si57xDivided_Rst_rq_OR_8_o_inv1 (i_Core/Si57xDivided_Rst_rq_OR_8_o_inv)
OBUFT:T->O 2.715 FpLed_onb8_3_OBUFT (FpLed_onb8<3>)
----------------------------------------
Total 6.177ns (3.494ns logic, 2.683ns route)
Total 6.172ns (3.494ns logic, 2.678ns route)
(56.6% logic, 43.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Si57x_ik'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.794ns (Levels of Logic = 2)
Source: i_Core/Si57xDivider_c_23 (FF)
Destination: FpLed_onb8<3> (PAD)
Source Clock: Si57x_ik rising
Data Path: i_Core/Si57xDivider_c_23 to FpLed_onb8<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 0.725 i_Core/Si57xDivider_c_23 (i_Core/Si57xDivider_c_23)
LUT2:I0->O 1 0.250 0.579 i_Core/Si57xDivided_Rst_rq_OR_8_o_inv1 (i_Core/Si57xDivided_Rst_rq_OR_8_o_inv)
OBUFT:T->O 2.715 FpLed_onb8_3_OBUFT (FpLed_onb8<3>)
----------------------------------------
Total 4.794ns (3.490ns logic, 1.304ns route)
(72.8% logic, 27.2% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 21 / 9
Total number of paths / destination ports: 15 / 9
-------------------------------------------------------------------------
Delay: 6.926ns (Levels of Logic = 4)
Source: VmeGa_ib5n<0> (PAD)
......@@ -1154,24 +1217,32 @@ Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock Si57x_ik
----------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------------------+---------+---------+---------+---------+
Si57x_ik | 6.551| | | |
SysAppClk_ik | 1.178| | | |
i_Core/i_VmeInterface/Stb_oq| 1.141| | | |
----------------------------+---------+---------+---------+---------+
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 2.365| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 3.087| | | |
SysAppClk_ik | 3.056| | | |
VcTcXo_ik | 3.083| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VcTcXo_ik
----------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------------------+---------+---------+---------+---------+
SysAppClk_ik | 1.178| | | |
VcTcXo_ik | 6.551| | | |
i_Core/i_VmeInterface/Stb_oq| 1.141| | | |
----------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock i_Core/i_VmeInterface/Stb_oq
----------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
......@@ -1183,14 +1254,14 @@ i_Core/i_VmeInterface/Stb_oq| 2.049| | | |
=========================================================================
Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 17.56 secs
Total REAL time to Xst completion: 28.00 secs
Total CPU time to Xst completion: 27.13 secs
-->
Total memory usage is 280020 kilobytes
Total memory usage is 155300 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 132 ( 0 filtered)
Number of warnings : 129 ( 0 filtered)
Number of infos : 17 ( 0 filtered)
--------------------------------------------------------------------------------
Release 12.3 Trace (nt64)
Release 12.3 Trace (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
Design file: SFpga.ncd
Physical constraint file: SFpga.pcf
......@@ -15,9 +15,6 @@ Environment Variable Effect
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
......@@ -44,39 +41,39 @@ Slack: 5.833ns (period - min period limit)
Location pin: BUFGMUX_X2Y4.I0
Clock network: Si57x
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
Slack: 7.858ns (period - min period limit)
Period: 8.333ns
Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/AckI_xb3_0/CLK
Logical resource: i_Core/Mshreg_VmeSysReset_dx_1/CLK
Location pin: SLICE_X52Y115.CLK
Min period limit: 0.475ns (2105.263MHz) (Tcp)
Physical resource: i_Core/Si57xDivider_c<3>/CLK
Logical resource: i_Core/Si57xDivider_c_0/CK
Location pin: SLICE_X58Y99.CLK
Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
Slack: 7.858ns (period - min period limit)
Period: 8.333ns
Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/AckI_xb3_0/CLK
Logical resource: i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0/CLK
Location pin: SLICE_X52Y115.CLK
Min period limit: 0.475ns (2105.263MHz) (Tcp)
Physical resource: i_Core/Si57xDivider_c<3>/CLK
Logical resource: i_Core/Si57xDivider_c_1/CK
Location pin: SLICE_X58Y99.CLK
Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 120 MHz HIGH 50%;
30978 paths analyzed, 2919 endpoints analyzed, 0 failing endpoints
300 paths analyzed, 80 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 7.854ns.
Minimum period is 2.500ns.
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_4 (SLICE_X75Y52.B5), 363 paths
Paths for end point i_Core/Si57xDivider_c_22 (SLICE_X58Y104.CIN), 20 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.479ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/Stb_oq (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_4 (FF)
Slack (setup path): 6.152ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_0 (FF)
Destination: i_Core/Si57xDivider_c_22 (FF)
Requirement: 8.333ns
Data Path Delay: 7.656ns (Levels of Logic = 5)
Clock Path Skew: -0.163ns (0.639 - 0.802)
Data Path Delay: 2.122ns (Levels of Logic = 6)
Clock Path Skew: -0.024ns (0.244 - 0.268)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -87,40 +84,43 @@ Slack (setup path): 0.479ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/Stb_oq to i_Core/i_SpiMasterWB/ShiftIn_qb32_4
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X72Y82.AMUX Tshcko 0.576 N268
i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B4 net (fanout=18) 1.850 i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B Tilo 0.254 N259
i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o1
SLICE_X74Y62.A6 net (fanout=6) 0.876 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o
SLICE_X74Y62.A Tilo 0.235 N257
i_Core/i_SpiMasterWB/_n0817_inv1_SW0
SLICE_X74Y61.C2 net (fanout=5) 0.822 N232
SLICE_X74Y61.CMUX Tilo 0.403 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_G
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X75Y52.B5 net (fanout=15) 0.924 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X75Y52.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<7>
i_Core/i_SpiMasterWB/ShiftIn_qb32_4_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_4
SLICE_X58Y99.AQ Tcko 0.476 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c_0
SLICE_X58Y99.A5 net (fanout=1) 0.397 i_Core/Si57xDivider_c<0>
SLICE_X58Y99.COUT Topcya 0.472 i_Core/Si57xDivider_c<3>
i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0
i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.COUT Tbyp 0.091 i_Core/Si57xDivider_c<7>
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.319 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_22
------------------------------------------------- ---------------------------
Total 7.656ns (2.100ns logic, 5.556ns route)
(27.4% logic, 72.6% route)
Total 2.122ns (1.631ns logic, 0.491ns route)
(76.9% logic, 23.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.656ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_4 (FF)
Slack (setup path): 6.248ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_4 (FF)
Destination: i_Core/Si57xDivider_c_22 (FF)
Requirement: 8.333ns
Data Path Delay: 7.351ns (Levels of Logic = 5)
Clock Path Skew: -0.291ns (0.639 - 0.930)
Data Path Delay: 2.028ns (Levels of Logic = 5)
Clock Path Skew: -0.022ns (0.244 - 0.266)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -131,40 +131,40 @@ Slack (setup path): 0.656ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_11 to i_Core/i_SpiMasterWB/ShiftIn_qb32_4
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_4 to i_Core/Si57xDivider_c_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X64Y67.BQ Tcko 0.525 i_Core/i_SpiMasterWB/TxCounter_cb12<11>
i_Core/i_SpiMasterWB/TxCounter_cb12_11
SLICE_X67Y63.B4 net (fanout=3) 1.761 i_Core/i_SpiMasterWB/TxCounter_cb12<11>
SLICE_X67Y63.B Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<11>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121
SLICE_X67Y63.D2 net (fanout=4) 0.543 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o12
SLICE_X67Y63.D Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<11>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o125
SLICE_X74Y61.D6 net (fanout=4) 0.962 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o
SLICE_X74Y61.CMUX Topdc 0.402 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_F
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X75Y52.B5 net (fanout=15) 0.924 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X75Y52.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<7>
i_Core/i_SpiMasterWB/ShiftIn_qb32_4_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_4
SLICE_X58Y100.AQ Tcko 0.476 i_Core/Si57xDivider_c<7>
i_Core/Si57xDivider_c_4
SLICE_X58Y100.A5 net (fanout=1) 0.397 i_Core/Si57xDivider_c<4>
SLICE_X58Y100.COUT Topcya 0.472 i_Core/Si57xDivider_c<7>
i_Core/Si57xDivider_c<4>_rt
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.319 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_22
------------------------------------------------- ---------------------------
Total 7.351ns (2.077ns logic, 5.274ns route)
(28.3% logic, 71.7% route)
Total 2.028ns (1.540ns logic, 0.488ns route)
(75.9% logic, 24.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.765ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/Stb_oq (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_4 (FF)
Slack (setup path): 6.279ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_3 (FF)
Destination: i_Core/Si57xDivider_c_22 (FF)
Requirement: 8.333ns
Data Path Delay: 7.370ns (Levels of Logic = 5)
Clock Path Skew: -0.163ns (0.639 - 0.802)
Data Path Delay: 1.995ns (Levels of Logic = 6)
Clock Path Skew: -0.024ns (0.244 - 0.268)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -175,43 +175,46 @@ Slack (setup path): 0.765ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/Stb_oq to i_Core/i_SpiMasterWB/ShiftIn_qb32_4
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_3 to i_Core/Si57xDivider_c_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X72Y82.AMUX Tshcko 0.576 N268
i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B4 net (fanout=18) 1.850 i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B Tilo 0.254 N259
i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o1
SLICE_X74Y62.A6 net (fanout=6) 0.876 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o
SLICE_X74Y62.A Tilo 0.235 N257
i_Core/i_SpiMasterWB/_n0817_inv1_SW0
SLICE_X74Y61.D3 net (fanout=5) 0.537 N232
SLICE_X74Y61.CMUX Topdc 0.402 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_F
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X75Y52.B5 net (fanout=15) 0.924 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X75Y52.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<7>
i_Core/i_SpiMasterWB/ShiftIn_qb32_4_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_4
SLICE_X58Y99.DQ Tcko 0.476 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c_3
SLICE_X58Y99.D5 net (fanout=1) 0.452 i_Core/Si57xDivider_c<3>
SLICE_X58Y99.COUT Topcyd 0.290 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c<3>_rt
i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.COUT Tbyp 0.091 i_Core/Si57xDivider_c<7>
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.319 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_22
------------------------------------------------- ---------------------------
Total 7.370ns (2.099ns logic, 5.271ns route)
(28.5% logic, 71.5% route)
Total 1.995ns (1.449ns logic, 0.546ns route)
(72.6% logic, 27.4% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_11 (SLICE_X79Y54.D6), 363 paths
Paths for end point i_Core/Si57xDivider_c_23 (SLICE_X58Y104.CIN), 20 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.602ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/Stb_oq (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_11 (FF)
Slack (setup path): 6.152ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_0 (FF)
Destination: i_Core/Si57xDivider_c_23 (FF)
Requirement: 8.333ns
Data Path Delay: 7.527ns (Levels of Logic = 5)
Clock Path Skew: -0.169ns (0.633 - 0.802)
Data Path Delay: 2.122ns (Levels of Logic = 6)
Clock Path Skew: -0.024ns (0.244 - 0.268)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -222,40 +225,43 @@ Slack (setup path): 0.602ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/Stb_oq to i_Core/i_SpiMasterWB/ShiftIn_qb32_11
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X72Y82.AMUX Tshcko 0.576 N268
i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B4 net (fanout=18) 1.850 i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B Tilo 0.254 N259
i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o1
SLICE_X74Y62.A6 net (fanout=6) 0.876 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o
SLICE_X74Y62.A Tilo 0.235 N257
i_Core/i_SpiMasterWB/_n0817_inv1_SW0
SLICE_X74Y61.C2 net (fanout=5) 0.822 N232
SLICE_X74Y61.CMUX Tilo 0.403 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_G
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X79Y54.D6 net (fanout=15) 0.795 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X79Y54.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<11>
i_Core/i_SpiMasterWB/ShiftIn_qb32_11_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_11
SLICE_X58Y99.AQ Tcko 0.476 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c_0
SLICE_X58Y99.A5 net (fanout=1) 0.397 i_Core/Si57xDivider_c<0>
SLICE_X58Y99.COUT Topcya 0.472 i_Core/Si57xDivider_c<3>
i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0
i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.COUT Tbyp 0.091 i_Core/Si57xDivider_c<7>
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.319 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_23
------------------------------------------------- ---------------------------
Total 7.527ns (2.100ns logic, 5.427ns route)
(27.9% logic, 72.1% route)
Total 2.122ns (1.631ns logic, 0.491ns route)
(76.9% logic, 23.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.779ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_11 (FF)
Slack (setup path): 6.248ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_4 (FF)
Destination: i_Core/Si57xDivider_c_23 (FF)
Requirement: 8.333ns
Data Path Delay: 7.222ns (Levels of Logic = 5)
Clock Path Skew: -0.297ns (0.633 - 0.930)
Data Path Delay: 2.028ns (Levels of Logic = 5)
Clock Path Skew: -0.022ns (0.244 - 0.266)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -266,40 +272,40 @@ Slack (setup path): 0.779ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_11 to i_Core/i_SpiMasterWB/ShiftIn_qb32_11
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_4 to i_Core/Si57xDivider_c_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X64Y67.BQ Tcko 0.525 i_Core/i_SpiMasterWB/TxCounter_cb12<11>
i_Core/i_SpiMasterWB/TxCounter_cb12_11
SLICE_X67Y63.B4 net (fanout=3) 1.761 i_Core/i_SpiMasterWB/TxCounter_cb12<11>
SLICE_X67Y63.B Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<11>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121
SLICE_X67Y63.D2 net (fanout=4) 0.543 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o12
SLICE_X67Y63.D Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<11>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o125
SLICE_X74Y61.D6 net (fanout=4) 0.962 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o
SLICE_X74Y61.CMUX Topdc 0.402 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_F
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X79Y54.D6 net (fanout=15) 0.795 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X79Y54.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<11>
i_Core/i_SpiMasterWB/ShiftIn_qb32_11_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_11
SLICE_X58Y100.AQ Tcko 0.476 i_Core/Si57xDivider_c<7>
i_Core/Si57xDivider_c_4
SLICE_X58Y100.A5 net (fanout=1) 0.397 i_Core/Si57xDivider_c<4>
SLICE_X58Y100.COUT Topcya 0.472 i_Core/Si57xDivider_c<7>
i_Core/Si57xDivider_c<4>_rt
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.319 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_23
------------------------------------------------- ---------------------------
Total 7.222ns (2.077ns logic, 5.145ns route)
(28.8% logic, 71.2% route)
Total 2.028ns (1.540ns logic, 0.488ns route)
(75.9% logic, 24.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.888ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/Stb_oq (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_11 (FF)
Slack (setup path): 6.279ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_3 (FF)
Destination: i_Core/Si57xDivider_c_23 (FF)
Requirement: 8.333ns
Data Path Delay: 7.241ns (Levels of Logic = 5)
Clock Path Skew: -0.169ns (0.633 - 0.802)
Data Path Delay: 1.995ns (Levels of Logic = 6)
Clock Path Skew: -0.024ns (0.244 - 0.268)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -310,43 +316,46 @@ Slack (setup path): 0.888ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/Stb_oq to i_Core/i_SpiMasterWB/ShiftIn_qb32_11
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_3 to i_Core/Si57xDivider_c_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X72Y82.AMUX Tshcko 0.576 N268
i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B4 net (fanout=18) 1.850 i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B Tilo 0.254 N259
i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o1
SLICE_X74Y62.A6 net (fanout=6) 0.876 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o
SLICE_X74Y62.A Tilo 0.235 N257
i_Core/i_SpiMasterWB/_n0817_inv1_SW0
SLICE_X74Y61.D3 net (fanout=5) 0.537 N232
SLICE_X74Y61.CMUX Topdc 0.402 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_F
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X79Y54.D6 net (fanout=15) 0.795 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X79Y54.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<11>
i_Core/i_SpiMasterWB/ShiftIn_qb32_11_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_11
SLICE_X58Y99.DQ Tcko 0.476 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c_3
SLICE_X58Y99.D5 net (fanout=1) 0.452 i_Core/Si57xDivider_c<3>
SLICE_X58Y99.COUT Topcyd 0.290 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c<3>_rt
i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.COUT Tbyp 0.091 i_Core/Si57xDivider_c<7>
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.319 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_23
------------------------------------------------- ---------------------------
Total 7.241ns (2.099ns logic, 5.142ns route)
(29.0% logic, 71.0% route)
Total 1.995ns (1.449ns logic, 0.546ns route)
(72.6% logic, 27.4% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_5 (SLICE_X76Y53.C6), 363 paths
Paths for end point i_Core/Si57xDivider_c_21 (SLICE_X58Y104.CIN), 20 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.791ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/Stb_oq (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_5 (FF)
Slack (setup path): 6.164ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_0 (FF)
Destination: i_Core/Si57xDivider_c_21 (FF)
Requirement: 8.333ns
Data Path Delay: 7.341ns (Levels of Logic = 5)
Clock Path Skew: -0.166ns (0.636 - 0.802)
Data Path Delay: 2.110ns (Levels of Logic = 6)
Clock Path Skew: -0.024ns (0.244 - 0.268)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -357,40 +366,43 @@ Slack (setup path): 0.791ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/Stb_oq to i_Core/i_SpiMasterWB/ShiftIn_qb32_5
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_0 to i_Core/Si57xDivider_c_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X72Y82.AMUX Tshcko 0.576 N268
i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B4 net (fanout=18) 1.850 i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B Tilo 0.254 N259
i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o1
SLICE_X74Y62.A6 net (fanout=6) 0.876 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o
SLICE_X74Y62.A Tilo 0.235 N257
i_Core/i_SpiMasterWB/_n0817_inv1_SW0
SLICE_X74Y61.C2 net (fanout=5) 0.822 N232
SLICE_X74Y61.CMUX Tilo 0.403 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_G
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X76Y53.C6 net (fanout=15) 0.643 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X76Y53.CLK Tas 0.339 i_Core/i_SpiMasterWB/ShiftIn_qb32<5>
i_Core/i_SpiMasterWB/ShiftIn_qb32_5_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_5
SLICE_X58Y99.AQ Tcko 0.476 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c_0
SLICE_X58Y99.A5 net (fanout=1) 0.397 i_Core/Si57xDivider_c<0>
SLICE_X58Y99.COUT Topcya 0.472 i_Core/Si57xDivider_c<3>
i_Core/Mcount_Si57xDivider_c_lut<0>_INV_0
i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.COUT Tbyp 0.091 i_Core/Si57xDivider_c<7>
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.307 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_21
------------------------------------------------- ---------------------------
Total 7.341ns (2.066ns logic, 5.275ns route)
(28.1% logic, 71.9% route)
Total 2.110ns (1.619ns logic, 0.491ns route)
(76.7% logic, 23.3% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.968ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_5 (FF)
Slack (setup path): 6.260ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_4 (FF)
Destination: i_Core/Si57xDivider_c_21 (FF)
Requirement: 8.333ns
Data Path Delay: 7.036ns (Levels of Logic = 5)
Clock Path Skew: -0.294ns (0.636 - 0.930)
Data Path Delay: 2.016ns (Levels of Logic = 5)
Clock Path Skew: -0.022ns (0.244 - 0.266)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -401,40 +413,40 @@ Slack (setup path): 0.968ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_11 to i_Core/i_SpiMasterWB/ShiftIn_qb32_5
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_4 to i_Core/Si57xDivider_c_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X64Y67.BQ Tcko 0.525 i_Core/i_SpiMasterWB/TxCounter_cb12<11>
i_Core/i_SpiMasterWB/TxCounter_cb12_11
SLICE_X67Y63.B4 net (fanout=3) 1.761 i_Core/i_SpiMasterWB/TxCounter_cb12<11>
SLICE_X67Y63.B Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<11>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121
SLICE_X67Y63.D2 net (fanout=4) 0.543 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o12
SLICE_X67Y63.D Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<11>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o125
SLICE_X74Y61.D6 net (fanout=4) 0.962 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o
SLICE_X74Y61.CMUX Topdc 0.402 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_F
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X76Y53.C6 net (fanout=15) 0.643 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X76Y53.CLK Tas 0.339 i_Core/i_SpiMasterWB/ShiftIn_qb32<5>
i_Core/i_SpiMasterWB/ShiftIn_qb32_5_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_5
SLICE_X58Y100.AQ Tcko 0.476 i_Core/Si57xDivider_c<7>
i_Core/Si57xDivider_c_4
SLICE_X58Y100.A5 net (fanout=1) 0.397 i_Core/Si57xDivider_c<4>
SLICE_X58Y100.COUT Topcya 0.472 i_Core/Si57xDivider_c<7>
i_Core/Si57xDivider_c<4>_rt
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.307 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_21
------------------------------------------------- ---------------------------
Total 7.036ns (2.043ns logic, 4.993ns route)
(29.0% logic, 71.0% route)
Total 2.016ns (1.528ns logic, 0.488ns route)
(75.8% logic, 24.2% route)
--------------------------------------------------------------------------------
Slack (setup path): 1.077ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/Stb_oq (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_5 (FF)
Slack (setup path): 6.291ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/Si57xDivider_c_3 (FF)
Destination: i_Core/Si57xDivider_c_21 (FF)
Requirement: 8.333ns
Data Path Delay: 7.055ns (Levels of Logic = 5)
Clock Path Skew: -0.166ns (0.636 - 0.802)
Data Path Delay: 1.983ns (Levels of Logic = 6)
Clock Path Skew: -0.024ns (0.244 - 0.268)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -445,119 +457,125 @@ Slack (setup path): 1.077ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/Stb_oq to i_Core/i_SpiMasterWB/ShiftIn_qb32_5
Maximum Data Path at Slow Process Corner: i_Core/Si57xDivider_c_3 to i_Core/Si57xDivider_c_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X72Y82.AMUX Tshcko 0.576 N268
i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B4 net (fanout=18) 1.850 i_Core/i_VmeInterface/Stb_oq
SLICE_X72Y68.B Tilo 0.254 N259
i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o1
SLICE_X74Y62.A6 net (fanout=6) 0.876 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_252_o
SLICE_X74Y62.A Tilo 0.235 N257
i_Core/i_SpiMasterWB/_n0817_inv1_SW0
SLICE_X74Y61.D3 net (fanout=5) 0.537 N232
SLICE_X74Y61.CMUX Topdc 0.402 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0_F
i_Core/i_SpiMasterWB/State_q_FSM_FFd3-In2_SW0
SLICE_X73Y54.C6 net (fanout=2) 1.084 N254
SLICE_X73Y54.C Tilo 0.259 i_Core/i_SpiMasterWB/ShiftIn_qb32<14>
i_Core/i_SpiMasterWB/_n0817_inv2_1
SLICE_X76Y53.C6 net (fanout=15) 0.643 i_Core/i_SpiMasterWB/_n0817_inv2
SLICE_X76Y53.CLK Tas 0.339 i_Core/i_SpiMasterWB/ShiftIn_qb32<5>
i_Core/i_SpiMasterWB/ShiftIn_qb32_5_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_5
SLICE_X58Y99.DQ Tcko 0.476 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c_3
SLICE_X58Y99.D5 net (fanout=1) 0.452 i_Core/Si57xDivider_c<3>
SLICE_X58Y99.COUT Topcyd 0.290 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c<3>_rt
i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<3>
SLICE_X58Y100.COUT Tbyp 0.091 i_Core/Si57xDivider_c<7>
i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<7>
SLICE_X58Y101.COUT Tbyp 0.091 i_Core/Si57xDivider_c<11>
i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<11>
SLICE_X58Y102.COUT Tbyp 0.091 i_Core/Si57xDivider_c<15>
i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.CIN net (fanout=1) 0.003 i_Core/Mcount_Si57xDivider_c_cy<15>
SLICE_X58Y103.COUT Tbyp 0.091 i_Core/Si57xDivider_c<19>
i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CIN net (fanout=1) 0.082 i_Core/Mcount_Si57xDivider_c_cy<19>
SLICE_X58Y104.CLK Tcinck 0.307 i_Core/Si57xDivider_c<23>
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_21
------------------------------------------------- ---------------------------
Total 7.055ns (2.065ns logic, 4.990ns route)
(29.3% logic, 70.7% route)
Total 1.983ns (1.437ns logic, 0.546ns route)
(72.5% logic, 27.5% route)
--------------------------------------------------------------------------------
Hold Paths: TS_Si57x_ikn = PERIOD TIMEGRP "Si57x_ikn" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/SS_onb32_7 (SLICE_X62Y51.A6), 1 path
Paths for end point i_Core/Si57xDivider_c_23 (SLICE_X58Y104.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.418ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_SpiMasterWB/SS_onb32_7 (FF)
Destination: i_Core/i_SpiMasterWB/SS_onb32_7 (FF)
Slack (hold path): 0.464ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/Si57xDivider_c_23 (FF)
Destination: i_Core/Si57xDivider_c_23 (FF)
Requirement: 0.000ns
Data Path Delay: 0.418ns (Levels of Logic = 1)
Data Path Delay: 0.464ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_SpiMasterWB/SS_onb32_7 to i_Core/i_SpiMasterWB/SS_onb32_7
Minimum Data Path at Fast Process Corner: i_Core/Si57xDivider_c_23 to i_Core/Si57xDivider_c_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y51.AQ Tcko 0.200 i_Core/i_SpiMasterWB/SS_onb32<8>
i_Core/i_SpiMasterWB/SS_onb32_7
SLICE_X62Y51.A6 net (fanout=2) 0.028 i_Core/i_SpiMasterWB/SS_onb32<7>
SLICE_X62Y51.CLK Tah (-Th) -0.190 i_Core/i_SpiMasterWB/SS_onb32<8>
i_Core/i_SpiMasterWB/SS_onb32_7_rstpot
i_Core/i_SpiMasterWB/SS_onb32_7
SLICE_X58Y104.DQ Tcko 0.200 i_Core/Si57xDivider_c<23>
i_Core/Si57xDivider_c_23
SLICE_X58Y104.D6 net (fanout=2) 0.027 i_Core/Si57xDivider_c<23>
SLICE_X58Y104.CLK Tah (-Th) -0.237 i_Core/Si57xDivider_c<23>
i_Core/Si57xDivider_c<23>_rt
i_Core/Mcount_Si57xDivider_c_xor<23>
i_Core/Si57xDivider_c_23
------------------------------------------------- ---------------------------
Total 0.418ns (0.390ns logic, 0.028ns route)
(93.3% logic, 6.7% route)
Total 0.464ns (0.437ns logic, 0.027ns route)
(94.2% logic, 5.8% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftOut_qb32_31 (SLICE_X70Y68.D6), 1 path
Paths for end point i_Core/Si57xDivider_c_1 (SLICE_X58Y99.B5), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.422ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_SpiMasterWB/ShiftOut_qb32_31 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftOut_qb32_31 (FF)
Slack (hold path): 0.505ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/Si57xDivider_c_1 (FF)
Destination: i_Core/Si57xDivider_c_1 (FF)
Requirement: 0.000ns
Data Path Delay: 0.422ns (Levels of Logic = 1)
Data Path Delay: 0.505ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_SpiMasterWB/ShiftOut_qb32_31 to i_Core/i_SpiMasterWB/ShiftOut_qb32_31
Minimum Data Path at Fast Process Corner: i_Core/Si57xDivider_c_1 to i_Core/Si57xDivider_c_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X70Y68.DQ Tcko 0.200 i_Core/i_SpiMasterWB/ShiftOut_qb32<31>
i_Core/i_SpiMasterWB/ShiftOut_qb32_31
SLICE_X70Y68.D6 net (fanout=5) 0.032 i_Core/i_SpiMasterWB/ShiftOut_qb32<31>
SLICE_X70Y68.CLK Tah (-Th) -0.190 i_Core/i_SpiMasterWB/ShiftOut_qb32<31>
i_Core/i_SpiMasterWB/ShiftOut_qb32_31_rstpot
i_Core/i_SpiMasterWB/ShiftOut_qb32_31
SLICE_X58Y99.BQ Tcko 0.200 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c_1
SLICE_X58Y99.B5 net (fanout=1) 0.071 i_Core/Si57xDivider_c<1>
SLICE_X58Y99.CLK Tah (-Th) -0.234 i_Core/Si57xDivider_c<3>
i_Core/Si57xDivider_c<1>_rt
i_Core/Mcount_Si57xDivider_c_cy<3>
i_Core/Si57xDivider_c_1
------------------------------------------------- ---------------------------
Total 0.422ns (0.390ns logic, 0.032ns route)
(92.4% logic, 7.6% route)
Total 0.505ns (0.434ns logic, 0.071ns route)
(85.9% logic, 14.1% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftOut_qb32_7 (SLICE_X62Y74.D6), 1 path
Paths for end point i_Core/Si57xDivider_c_5 (SLICE_X58Y100.B5), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.424ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_SpiMasterWB/ShiftOut_qb32_7 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftOut_qb32_7 (FF)
Slack (hold path): 0.505ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/Si57xDivider_c_5 (FF)
Destination: i_Core/Si57xDivider_c_5 (FF)
Requirement: 0.000ns
Data Path Delay: 0.424ns (Levels of Logic = 1)
Data Path Delay: 0.505ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_SpiMasterWB/ShiftOut_qb32_7 to i_Core/i_SpiMasterWB/ShiftOut_qb32_7
Minimum Data Path at Fast Process Corner: i_Core/Si57xDivider_c_5 to i_Core/Si57xDivider_c_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y74.DQ Tcko 0.200 i_Core/i_SpiMasterWB/ShiftOut_qb32<7>
i_Core/i_SpiMasterWB/ShiftOut_qb32_7
SLICE_X62Y74.D6 net (fanout=4) 0.034 i_Core/i_SpiMasterWB/ShiftOut_qb32<7>
SLICE_X62Y74.CLK Tah (-Th) -0.190 i_Core/i_SpiMasterWB/ShiftOut_qb32<7>
i_Core/i_SpiMasterWB/ShiftOut_qb32_7_rstpot
i_Core/i_SpiMasterWB/ShiftOut_qb32_7
SLICE_X58Y100.BQ Tcko 0.200 i_Core/Si57xDivider_c<7>
i_Core/Si57xDivider_c_5
SLICE_X58Y100.B5 net (fanout=1) 0.071 i_Core/Si57xDivider_c<5>
SLICE_X58Y100.CLK Tah (-Th) -0.234 i_Core/Si57xDivider_c<7>
i_Core/Si57xDivider_c<5>_rt
i_Core/Mcount_Si57xDivider_c_cy<7>
i_Core/Si57xDivider_c_5
------------------------------------------------- ---------------------------
Total 0.424ns (0.390ns logic, 0.034ns route)
(92.0% logic, 8.0% route)
Total 0.505ns (0.434ns logic, 0.071ns route)
(85.9% logic, 14.1% route)
--------------------------------------------------------------------------------
......@@ -571,20 +589,20 @@ Slack: 5.833ns (period - min period limit)
Location pin: BUFGMUX_X2Y4.I0
Clock network: Si57x
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
Slack: 7.858ns (period - min period limit)
Period: 8.333ns
Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/AckI_xb3_0/CLK
Logical resource: i_Core/Mshreg_VmeSysReset_dx_1/CLK
Location pin: SLICE_X52Y115.CLK
Min period limit: 0.475ns (2105.263MHz) (Tcp)
Physical resource: i_Core/Si57xDivider_c<3>/CLK
Logical resource: i_Core/Si57xDivider_c_0/CK
Location pin: SLICE_X58Y99.CLK
Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
Slack: 7.858ns (period - min period limit)
Period: 8.333ns
Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/AckI_xb3_0/CLK
Logical resource: i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0/CLK
Location pin: SLICE_X52Y115.CLK
Min period limit: 0.475ns (2105.263MHz) (Tcp)
Physical resource: i_Core/Si57xDivider_c<3>/CLK
Logical resource: i_Core/Si57xDivider_c_1/CK
Location pin: SLICE_X58Y99.CLK
Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
......@@ -594,17 +612,17 @@ Timing constraint: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH
129 paths analyzed, 97 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 5.169ns.
Minimum period is 4.684ns.
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_18 (SLICE_X75Y128.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_20 (SLICE_X82Y89.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.164ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.649ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_18 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_20 (FF)
Requirement: 8.333ns
Data Path Delay: 4.794ns (Levels of Logic = 1)
Clock Path Skew: -0.340ns (0.643 - 0.983)
Data Path Delay: 4.435ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -615,29 +633,29 @@ Slack (setup path): 3.164ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_18
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_20
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y110.CQ Tcko 0.430 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X46Y109.A3 net (fanout=1) 0.529 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X46Y109.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X71Y99.A4 net (fanout=1) 1.569 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X75Y128.CE net (fanout=7) 3.192 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X75Y128.CLK Tceck 0.408 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_18
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.314 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_20
------------------------------------------------- ---------------------------
Total 4.794ns (1.073ns logic, 3.721ns route)
(22.4% logic, 77.6% route)
Total 4.435ns (1.049ns logic, 3.386ns route)
(23.7% logic, 76.3% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.218ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.710ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_18 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_20 (FF)
Requirement: 8.333ns
Data Path Delay: 4.740ns (Levels of Logic = 1)
Clock Path Skew: -0.340ns (0.643 - 0.983)
Data Path Delay: 4.374ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -648,32 +666,32 @@ Slack (setup path): 3.218ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_18
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_20
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y110.BQ Tcko 0.430 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X46Y109.A4 net (fanout=2) 0.475 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X46Y109.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X71Y99.A5 net (fanout=2) 1.508 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X75Y128.CE net (fanout=7) 3.192 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X75Y128.CLK Tceck 0.408 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_18
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.314 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_20
------------------------------------------------- ---------------------------
Total 4.740ns (1.073ns logic, 3.667ns route)
(22.6% logic, 77.4% route)
Total 4.374ns (1.049ns logic, 3.325ns route)
(24.0% logic, 76.0% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_17 (SLICE_X75Y128.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_23 (SLICE_X82Y89.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.182ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.672ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_17 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_23 (FF)
Requirement: 8.333ns
Data Path Delay: 4.776ns (Levels of Logic = 1)
Clock Path Skew: -0.340ns (0.643 - 0.983)
Data Path Delay: 4.412ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -684,29 +702,29 @@ Slack (setup path): 3.182ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_17
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y110.CQ Tcko 0.430 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X46Y109.A3 net (fanout=1) 0.529 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X46Y109.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X71Y99.A4 net (fanout=1) 1.569 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X75Y128.CE net (fanout=7) 3.192 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X75Y128.CLK Tceck 0.390 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_17
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.291 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_23
------------------------------------------------- ---------------------------
Total 4.776ns (1.055ns logic, 3.721ns route)
(22.1% logic, 77.9% route)
Total 4.412ns (1.026ns logic, 3.386ns route)
(23.3% logic, 76.7% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.236ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.733ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_17 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_23 (FF)
Requirement: 8.333ns
Data Path Delay: 4.722ns (Levels of Logic = 1)
Clock Path Skew: -0.340ns (0.643 - 0.983)
Data Path Delay: 4.351ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -717,32 +735,32 @@ Slack (setup path): 3.236ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_17
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y110.BQ Tcko 0.430 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X46Y109.A4 net (fanout=2) 0.475 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X46Y109.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X71Y99.A5 net (fanout=2) 1.508 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X75Y128.CE net (fanout=7) 3.192 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X75Y128.CLK Tceck 0.390 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_17
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.291 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_23
------------------------------------------------- ---------------------------
Total 4.722ns (1.055ns logic, 3.667ns route)
(22.3% logic, 77.7% route)
Total 4.351ns (1.026ns logic, 3.325ns route)
(23.6% logic, 76.4% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_19 (SLICE_X75Y128.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_22 (SLICE_X82Y89.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.190ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.674ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_19 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
Requirement: 8.333ns
Data Path Delay: 4.768ns (Levels of Logic = 1)
Clock Path Skew: -0.340ns (0.643 - 0.983)
Data Path Delay: 4.410ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -753,29 +771,29 @@ Slack (setup path): 3.190ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_19
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y110.CQ Tcko 0.430 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X46Y109.A3 net (fanout=1) 0.529 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X46Y109.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X71Y99.A4 net (fanout=1) 1.569 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X75Y128.CE net (fanout=7) 3.192 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X75Y128.CLK Tceck 0.382 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_19
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.289 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_22
------------------------------------------------- ---------------------------
Total 4.768ns (1.047ns logic, 3.721ns route)
(22.0% logic, 78.0% route)
Total 4.410ns (1.024ns logic, 3.386ns route)
(23.2% logic, 76.8% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.244ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.735ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_19 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
Requirement: 8.333ns
Data Path Delay: 4.714ns (Levels of Logic = 1)
Clock Path Skew: -0.340ns (0.643 - 0.983)
Data Path Delay: 4.349ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -786,106 +804,105 @@ Slack (setup path): 3.244ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_19
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y110.BQ Tcko 0.430 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X46Y109.A4 net (fanout=2) 0.475 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X46Y109.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X71Y99.A5 net (fanout=2) 1.508 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X75Y128.CE net (fanout=7) 3.192 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X75Y128.CLK Tceck 0.382 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_19
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.289 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_22
------------------------------------------------- ---------------------------
Total 4.714ns (1.047ns logic, 3.667ns route)
(22.2% logic, 77.8% route)
Total 4.349ns (1.024ns logic, 3.325ns route)
(23.5% logic, 76.5% route)
--------------------------------------------------------------------------------
Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/DatInShReg_b32_2 (SLICE_X47Y109.C4), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_14 (SLICE_X78Y92.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.496ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_3 (FF)
Destination: i_Core/i_Slv2SerWB/DatInShReg_b32_2 (FF)
Slack (hold path): 0.439ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_14 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_14 (FF)
Requirement: 0.000ns
Data Path Delay: 0.496ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Data Path Delay: 0.440ns (Levels of Logic = 0)
Clock Path Skew: 0.001ns (0.041 - 0.040)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_3 to i_Core/i_Slv2SerWB/DatInShReg_b32_2
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_14 to i_Core/i_Slv2SerWB/Dat_xb32_14
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y109.DMUX Tshcko 0.244 i_Core/i_Slv2SerWB/DatInShReg_b32<7>
i_Core/i_Slv2SerWB/DatInShReg_b32_3
SLICE_X47Y109.C4 net (fanout=2) 0.097 i_Core/i_Slv2SerWB/DatInShReg_b32<3>
SLICE_X47Y109.CLK Tah (-Th) -0.155 i_Core/i_Slv2SerWB/DatInShReg_b32<7>
i_Core/i_Slv2SerWB/DatInShReg_b32<3>_rt
i_Core/i_Slv2SerWB/DatInShReg_b32_2
SLICE_X79Y93.CQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<15>
i_Core/i_Slv2SerWB/DatInShReg_b32_14
SLICE_X78Y92.CX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<14>
SLICE_X78Y92.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<15>
i_Core/i_Slv2SerWB/Dat_xb32_14
------------------------------------------------- ---------------------------
Total 0.496ns (0.399ns logic, 0.097ns route)
(80.4% logic, 19.6% route)
Total 0.440ns (0.246ns logic, 0.194ns route)
(55.9% logic, 44.1% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_0 (SLICE_X46Y109.AX), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_10 (SLICE_X78Y97.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.518ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_0 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_0 (FF)
Slack (hold path): 0.441ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_10 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_10 (FF)
Requirement: 0.000ns
Data Path Delay: 0.520ns (Levels of Logic = 0)
Clock Path Skew: 0.002ns (0.043 - 0.041)
Data Path Delay: 0.442ns (Levels of Logic = 0)
Clock Path Skew: 0.001ns (0.043 - 0.042)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_0 to i_Core/i_Slv2SerWB/Dat_xb32_0
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_10 to i_Core/i_Slv2SerWB/Dat_xb32_10
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y109.AMUX Tshcko 0.244 i_Core/i_Slv2SerWB/DatInShReg_b32<7>
i_Core/i_Slv2SerWB/DatInShReg_b32_0
SLICE_X46Y109.AX net (fanout=1) 0.228 i_Core/i_Slv2SerWB/DatInShReg_b32<0>
SLICE_X46Y109.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/Dat_xb32_0
SLICE_X78Y96.CQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_10
SLICE_X78Y97.CX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<10>
SLICE_X78Y97.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<11>
i_Core/i_Slv2SerWB/Dat_xb32_10
------------------------------------------------- ---------------------------
Total 0.520ns (0.292ns logic, 0.228ns route)
(56.2% logic, 43.8% route)
Total 0.442ns (0.248ns logic, 0.194ns route)
(56.1% logic, 43.9% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/DatInShReg_b32_18 (SLICE_X74Y133.CX), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_11 (SLICE_X78Y97.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.523ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_19 (FF)
Destination: i_Core/i_Slv2SerWB/DatInShReg_b32_18 (FF)
Slack (hold path): 0.441ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_11 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_11 (FF)
Requirement: 0.000ns
Data Path Delay: 0.523ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Data Path Delay: 0.442ns (Levels of Logic = 0)
Clock Path Skew: 0.001ns (0.043 - 0.042)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_19 to i_Core/i_Slv2SerWB/DatInShReg_b32_18
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_11 to i_Core/i_Slv2SerWB/Dat_xb32_11
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X74Y133.DQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<19>
i_Core/i_Slv2SerWB/DatInShReg_b32_19
SLICE_X74Y133.CX net (fanout=2) 0.275 i_Core/i_Slv2SerWB/DatInShReg_b32<19>
SLICE_X74Y133.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/DatInShReg_b32<19>
i_Core/i_Slv2SerWB/DatInShReg_b32_18
SLICE_X78Y96.DQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_11
SLICE_X78Y97.DX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
SLICE_X78Y97.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<11>
i_Core/i_Slv2SerWB/Dat_xb32_11
------------------------------------------------- ---------------------------
Total 0.523ns (0.248ns logic, 0.275ns route)
(47.4% logic, 52.6% route)
Total 0.442ns (0.248ns logic, 0.194ns route)
(56.1% logic, 43.9% route)
--------------------------------------------------------------------------------
......@@ -904,7 +921,7 @@ Slack: 7.853ns (period - min period limit)
Min period limit: 0.480ns (2083.333MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<31>/CLK
Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_28/CK
Location pin: SLICE_X52Y92.CLK
Location pin: SLICE_X56Y84.CLK
Clock network: SysAppClk_ik_BUFGP
--------------------------------------------------------------------------------
Slack: 7.853ns (period - min period limit)
......@@ -912,7 +929,7 @@ Slack: 7.853ns (period - min period limit)
Min period limit: 0.480ns (2083.333MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<31>/CLK
Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_29/CK
Location pin: SLICE_X52Y92.CLK
Location pin: SLICE_X56Y84.CLK
Clock network: SysAppClk_ik_BUFGP
--------------------------------------------------------------------------------
......@@ -929,8 +946,8 @@ Clock to Setup on destination clock Si57x_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 7.854| | | |
Si57x_ikn | 7.854| | | |
Si57x_ik | 2.181| | | |
Si57x_ikn | 2.181| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock Si57x_ikn
......@@ -938,8 +955,8 @@ Clock to Setup on destination clock Si57x_ikn
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 7.854| | | |
Si57x_ikn | 7.854| | | |
Si57x_ik | 2.181| | | |
Si57x_ikn | 2.181| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik
......@@ -947,7 +964,7 @@ Clock to Setup on destination clock SysAppClk_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SysAppClk_ik | 5.169| | | |
SysAppClk_ik | 4.684| | | |
---------------+---------+---------+---------+---------+
......@@ -956,23 +973,23 @@ Timing summary:
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 31107 paths, 0 nets, and 4144 connections
Constraints cover 429 paths, 0 nets, and 127 connections
Design statistics:
Minimum period: 7.854ns{1} (Maximum frequency: 127.324MHz)
Minimum period: 4.684ns{1} (Maximum frequency: 213.493MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Wed Jan 12 08:59:48 2011
Analysis completed Fri Jan 28 11:55:25 2011
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 398 MB
Peak Memory Usage: 268 MB
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 12.3 - par M.70d (nt64)
Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Wed Jan 12 08:59:35 2011
Fri Jan 28 11:55:02 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 50 loadless signals in this design. This design will cause Bitgen to issue DRC
WARNING:ParHelpers:361 - There are 49 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
AFpgaProgClk_io_IBUF
......@@ -44,7 +44,6 @@ WARNING:ParHelpers:361 - There are 50 loadless signals in this design. This desi
Switch_ib2<0>_IBUF
Switch_ib2<1>_IBUF
TempIdDQ_io_IBUF
VcTcXo_ik_IBUF
VmeAm_ib6<1>_IBUF
VmeAm_ib6<2>_IBUF
VmeP0LvdsBunchClkIn_i_IBUF
......
......@@ -15,17 +15,17 @@
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
</tr>
<tr>
<td>XILINX</td>
......@@ -35,6 +35,13 @@
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
......@@ -508,31 +515,31 @@
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
</tr>
<tr>
<td>OS Release</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
</tr>
</TABLE>
</BODY> </HTML>
\ No newline at end of file
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 12.3 Map M.70d (nt64)
Release 12.3 Map M.70d (nt)
Xilinx Map Application Log File for Design 'SFpga'
Design Information
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Wed Jan 12 08:58:19 2011
Mapped Date : Fri Jan 28 11:48:01 2011
Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
......@@ -87,66 +87,60 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 13 secs
Total CPU time at the beginning of Placer: 12 secs
Total REAL time at the beginning of Placer: 25 secs
Total CPU time at the beginning of Placer: 24 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:efb082b3) REAL time: 17 secs
Phase 1.1 Initial Placement Analysis (Checksum:cc31257e) REAL time: 32 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:efb082b3) REAL time: 18 secs
Phase 2.7 Design Feasibility Check (Checksum:cc31257e) REAL time: 33 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:efb082b3) REAL time: 18 secs
Phase 3.31 Local Placement Optimization (Checksum:cc31257e) REAL time: 33 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:f9255233) REAL time: 24 secs
(Checksum:aaca966e) REAL time: 40 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:f9255233) REAL time: 24 secs
Phase 5.36 Local Placement Optimization (Checksum:aaca966e) REAL time: 40 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:f9255233) REAL time: 24 secs
Phase 6.30 Global Clock Region Assignment (Checksum:aaca966e) REAL time: 40 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:8dab73e2) REAL time: 25 secs
Phase 7.3 Local Placement Optimization (Checksum:98519d88) REAL time: 41 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:f947297e) REAL time: 25 secs
Phase 8.5 Local Placement Optimization (Checksum:aaea37e3) REAL time: 41 secs
Phase 9.8 Global Placement
....
.......................
...............................................................................
...............
Phase 9.8 Global Placement (Checksum:ba1f4ae6) REAL time: 31 secs
....................
Phase 9.8 Global Placement (Checksum:f9eafb45) REAL time: 44 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:ba1f4ae6) REAL time: 31 secs
Phase 10.5 Local Placement Optimization (Checksum:f9eafb45) REAL time: 44 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:8d70e2d) REAL time: 36 secs
Phase 11.18 Placement Optimization (Checksum:af7d4423) REAL time: 45 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:8d70e2d) REAL time: 37 secs
Phase 12.5 Local Placement Optimization (Checksum:af7d4423) REAL time: 45 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:b900aef2) REAL time: 37 secs
Phase 13.34 Placement Validation (Checksum:1a6c36bd) REAL time: 46 secs
Total REAL time to Placer completion: 42 secs
Total CPU time to Placer completion: 40 secs
Total REAL time to Placer completion: 55 secs
Total CPU time to Placer completion: 55 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
......@@ -225,8 +219,6 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
......@@ -254,18 +246,18 @@ Design Summary
Design Summary:
Number of errors: 0
Number of warnings: 85
Number of warnings: 83
Slice Logic Utilization:
Number of Slice Registers: 784 out of 184,304 1%
Number used as Flip Flops: 784
Number of Slice Registers: 765 out of 184,304 1%
Number used as Flip Flops: 765
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 878 out of 92,152 1%
Number used as logic: 850 out of 92,152 1%
Number using O6 output only: 621
Number of Slice LUTs: 851 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
Number using O5 and O6: 146
Number using O5 and O6: 124
Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -283,14 +275,14 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 370 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,037
Number with an unused Flip Flop: 327 out of 1,037 31%
Number with an unused LUT: 159 out of 1,037 15%
Number of fully used LUT-FF pairs: 551 out of 1,037 53%
Number of unique control sets: 26
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of unique control sets: 27
Number of slice register sites lost
to control set restrictions: 76 out of 184,304 1%
to control set restrictions: 71 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -309,8 +301,8 @@ Specific Feature Utilization:
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
......@@ -333,9 +325,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 631 MB
Total REAL time to MAP completion: 43 secs
Total CPU time to MAP completion: 42 secs
Peak Memory Usage: 396 MB
Total REAL time to MAP completion: 58 secs
Total CPU time to MAP completion: 58 secs
Mapping completed.
See MAP report file "SFpga_map.mrp" for details.
Release 12.3 Map M.70d (nt64)
Release 12.3 Map M.70d (nt)
Xilinx Mapping Report File for Design 'SFpga'
Design Information
......@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Wed Jan 12 08:58:19 2011
Mapped Date : Fri Jan 28 11:48:01 2011
Design Summary
--------------
Number of errors: 0
Number of warnings: 85
Number of warnings: 83
Slice Logic Utilization:
Number of Slice Registers: 784 out of 184,304 1%
Number used as Flip Flops: 784
Number of Slice Registers: 765 out of 184,304 1%
Number used as Flip Flops: 765
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 878 out of 92,152 1%
Number used as logic: 850 out of 92,152 1%
Number using O6 output only: 621
Number of Slice LUTs: 851 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
Number using O5 and O6: 146
Number using O5 and O6: 124
Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -44,14 +44,14 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 370 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,037
Number with an unused Flip Flop: 327 out of 1,037 31%
Number with an unused LUT: 159 out of 1,037 15%
Number of fully used LUT-FF pairs: 551 out of 1,037 53%
Number of unique control sets: 26
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of unique control sets: 27
Number of slice register sites lost
to control set restrictions: 76 out of 184,304 1%
to control set restrictions: 71 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -70,8 +70,8 @@ Specific Feature Utilization:
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
......@@ -94,9 +94,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 631 MB
Total REAL time to MAP completion: 43 secs
Total CPU time to MAP completion: 42 secs
Peak Memory Usage: 396 MB
Total REAL time to MAP completion: 58 secs
Total CPU time to MAP completion: 58 secs
Table of Contents
-----------------
......@@ -187,10 +187,6 @@ WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
VAdjInhibit_ozn has been removed.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
......@@ -269,8 +265,6 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
......@@ -296,7 +290,7 @@ WARNING:PhysDesignRules:367 - The signal
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network N504 has no load.
INFO:LIT:395 - The above info message is repeated 54 more times for the
INFO:LIT:395 - The above info message is repeated 53 more times for the
following (max. 5 shown):
N506,
VmeAm_ib6<2>_IBUF,
......@@ -312,8 +306,6 @@ INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
......
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="12.3">
<document OS="nt" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Wed Jan 12 08:59:02 2011">
<application stringID="Map" timeStamp="Fri Jan 28 11:49:00 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="4">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
</item>
<item stringID="User_EnvHost" value="PCBE13225"/>
<item stringID="User_EnvHost" value="bqplv2"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
</row>
</table>
</section>
......@@ -64,16 +68,16 @@
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/>
</section>
<task stringID="MAP_PACK_REPORT">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="784">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="784"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="765">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="765"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="869">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="842">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="621"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="146"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="616"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="124"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
......@@ -115,22 +119,22 @@
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="85"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="646520"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="43 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="42 secs "/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="405884"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="58 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="58 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="784">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="784"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="765">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="765"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="878">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="851">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="621"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="146"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="616"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="124"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
......@@ -150,15 +154,15 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="370">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="59"/>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="392">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="51"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="307"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="337"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1037">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="327"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="159"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="551"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1060">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="372"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="209"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="479"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
......@@ -197,7 +201,7 @@
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="3"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
</section>
......@@ -2552,7 +2556,7 @@
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION">
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="26"/>
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="27"/>
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
<property stringID="MAP_CLOCK_SIGNAL"/>
<property stringID="MAP_RESET_SIGNAL"/>
......@@ -2584,7 +2588,7 @@
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="3"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
......
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="12.3">
<document OS="nt" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Wed Jan 12 08:58:17 2011">
<application stringID="NgdBuild" timeStamp="Fri Jan 28 11:47:59 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="4">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
</item>
<item stringID="User_EnvHost" value="PCBE13225"/>
<item stringID="User_EnvHost" value="bqplv2"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
</row>
</table>
</section>
......@@ -61,34 +65,34 @@
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="16"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="165"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="166"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="104"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="170"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="310"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="311"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="77"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="78"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="86"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="211"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="85"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="123"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="284"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="128"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="129"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="86"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="121"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="279"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="106"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="154"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="30"/>
......@@ -96,15 +100,15 @@
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="121"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="99"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="165"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="166"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="104"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="170"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="310"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="311"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
......@@ -115,12 +119,12 @@
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="86"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="211"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="85"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="123"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="284"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="128"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="129"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="86"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="121"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="279"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="106"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="154"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="62"/>
......@@ -129,7 +133,7 @@
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="121"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="99"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
......
#Release 12.3 - par M.70d (nt64)
#Release 12.3 - par M.70d (nt)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Wed Jan 12 08:59:35 2011
#Fri Jan 28 11:55:00 2011
#
## NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 - par M.70d (nt64)
Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Wed Jan 12 08:59:35 2011
Fri Jan 28 11:55:01 2011
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="12.3">
<document OS="nt" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Wed Jan 12 08:59:13 2011">
<application stringID="par" timeStamp="Fri Jan 28 11:49:22 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="4">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
</item>
<item stringID="User_EnvHost" value="PCBE13225"/>
<item stringID="User_EnvHost" value="bqplv2"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
</row>
</table>
</section>
......@@ -59,12 +63,12 @@
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="28 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="28 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="5 mins 56 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="5 mins 54 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="31 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="31 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="5 mins 59 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="5 mins 58 secs "/>
</section>
</task>
<task stringID="PAR_par">
......@@ -79,30 +83,39 @@
<column label="Net Skew(ns)" stringID="NET_SKEW"/>
<column label="Max Delay(ns)" stringID="MAX_DELAY"/>
<row stringID="row" value="1">
<item label="Clock Net" stringID="CLOCK_NET" value="VcTcXo_ik_IBUF_BUFG"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y16"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="203.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.325000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.693000"/>
</row>
<row stringID="row" value="2">
<item label="Clock Net" stringID="CLOCK_NET" value="Si57x_BUFG"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="226.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.326000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.695000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="6.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.009000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.690000"/>
</row>
<row stringID="row" value="2">
<row stringID="row" value="3">
<item label="Clock Net" stringID="CLOCK_NET" value="SysAppClk_ik_BUFGP"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.320000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.693000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.189000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.692000"/>
</row>
<row stringID="row" value="3">
<row stringID="row" value="4">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/Stb_oq"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="18.000000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="17.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.559000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.404000"/>
</row>
</table>
</section>
......@@ -6256,67 +6269,71 @@
<section stringID="PAR_UNROUTES_REPORT">
<item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="50"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="49"/>
</section>
</task>
</application>
<application stringID="Par" timeStamp="Wed Jan 12 08:59:13 2011">
<application stringID="Par" timeStamp="Fri Jan 28 11:49:22 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="4">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
</item>
<item stringID="User_EnvHost" value="PCBE13225"/>
<item stringID="User_EnvHost" value="bqplv2"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
</row>
</table>
</section>
<task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
<section stringID="PAR_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="784">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="784"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="765">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="765"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="878">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="851">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="621"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="146"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="616"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="124"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
......@@ -6336,15 +6353,15 @@
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="370">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="59"/>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="392">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="51"/>
<item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="307"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="337"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1037">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="327"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="159"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="551"/>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1060">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="372"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="209"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="479"/>
</item>
</section>
<section stringID="PAR_IOB_REPORTING">
......@@ -6383,7 +6400,7 @@
<item AVAILABLE="1" dataType="int" stringID="PAR_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="PAR_BUFG_DATA">
<item dataType="int" stringID="PAR_NUM_BUFG" value="2"/>
<item dataType="int" stringID="PAR_NUM_BUFG" value="3"/>
<item dataType="int" stringID="PAR_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="PAR_AVAILABLE" value="16"/>
</section>
......
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (01/12/2011 - 09:00:32)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (01/28/2011 - 11:56:25)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>SystemFpga.xise</TD>
......@@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>339 Warnings (0 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>329 Warnings (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
......@@ -60,13 +60,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>784</TD>
<TD ALIGN=RIGHT>765</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>784</TD>
<TD ALIGN=RIGHT>765</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -90,19 +90,19 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>878</TD>
<TD ALIGN=RIGHT>851</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>850</TD>
<TD ALIGN=RIGHT>823</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>621</TD>
<TD ALIGN=RIGHT>616</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -114,7 +114,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>146</TD>
<TD ALIGN=RIGHT>124</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -210,43 +210,43 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>370</TD>
<TD ALIGN=RIGHT>392</TD>
<TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>1,037</TD>
<TD ALIGN=RIGHT>1,060</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>327</TD>
<TD ALIGN=RIGHT>1,037</TD>
<TD ALIGN=RIGHT>31%</TD>
<TD ALIGN=RIGHT>372</TD>
<TD ALIGN=RIGHT>1,060</TD>
<TD ALIGN=RIGHT>35%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>159</TD>
<TD ALIGN=RIGHT>1,037</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD ALIGN=RIGHT>209</TD>
<TD ALIGN=RIGHT>1,060</TD>
<TD ALIGN=RIGHT>19%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>551</TD>
<TD ALIGN=RIGHT>1,037</TD>
<TD ALIGN=RIGHT>53%</TD>
<TD ALIGN=RIGHT>479</TD>
<TD ALIGN=RIGHT>1,060</TD>
<TD ALIGN=RIGHT>45%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>27</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>76</TD>
<TD ALIGN=RIGHT>71</TD>
<TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -300,13 +300,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD ALIGN=RIGHT>18%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>3</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -463,23 +463,23 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed 12. Jan 08:58:12 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>132 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>17 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed 12. Jan 08:58:17 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>18 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed 12. Jan 08:59:03 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>85 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>10 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed 12. Jan 08:59:36 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:47:53 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>129 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>17 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:47:59 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>16 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:49:00 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:55:02 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>51 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed 12. Jan 08:59:48 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed 12. Jan 09:00:16 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>52 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:55:25 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:56:19 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>50 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu 16. Dec 17:57:34 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 15. Dec 15:16:36 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed 12. Jan 09:00:16 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed 12. Jan 09:00:32 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Dec 20 10:20:47 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Dec 20 10:20:47 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Jan 28 11:56:20 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Jan 28 11:56:25 2011</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 01/12/2011 - 09:00:32</center>
<br><center><b>Date Generated:</b> 01/28/2011 - 11:56:26</center>
</BODY></HTML>
\ No newline at end of file
......@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="55">
<DesignSummary rev="59">
<CmdHistory>
</CmdHistory>
</DesignSummary>
......@@ -4,811 +4,811 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="55">
<DesignStatistics TimeStamp="Wed Jan 12 09:00:15 2011"><group name="NetStatistics">
<item name="NumNets_Active" rev="55">
<attrib name="value" value="1762"/></item>
<item name="NumNets_Gnd" rev="55">
<DeviceUsageSummary rev="59">
<DesignStatistics TimeStamp="Fri Jan 28 11:56:18 2011"><group name="NetStatistics">
<item name="NumNets_Active" rev="59">
<attrib name="value" value="1735"/></item>
<item name="NumNets_Gnd" rev="59">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="55">
<item name="NumNets_Vcc" rev="59">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="55">
<attrib name="value" value="32"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="55">
<attrib name="value" value="163"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="55">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="55">
<attrib name="value" value="18"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="55">
<attrib name="value" value="243"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="55">
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="59">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="59">
<attrib name="value" value="200"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="59">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="59">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="55">
<attrib name="value" value="278"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="55">
<attrib name="value" value="2154"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="55">
<attrib name="value" value="353"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="55">
<attrib name="value" value="167"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="55">
<attrib name="value" value="38"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="55">
<item name="NumNodesOfType_Active_CLKPIN" rev="59">
<attrib name="value" value="226"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="59">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="59">
<attrib name="value" value="253"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="59">
<attrib name="value" value="2317"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="59">
<attrib name="value" value="354"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="59">
<attrib name="value" value="185"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="59">
<attrib name="value" value="33"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="59">
<attrib name="value" value="242"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="55">
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="59">
<attrib name="value" value="242"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="55">
<attrib name="value" value="3494"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="55">
<attrib name="value" value="1460"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="55">
<attrib name="value" value="1303"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="55">
<item name="NumNodesOfType_Active_LUTINPUT" rev="59">
<attrib name="value" value="3401"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="59">
<attrib name="value" value="1440"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="59">
<attrib name="value" value="1281"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="59">
<attrib name="value" value="135"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="55">
<attrib name="value" value="114"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="55">
<attrib name="value" value="772"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="55">
<attrib name="value" value="4039"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="55">
<attrib name="value" value="6103"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="55">
<attrib name="value" value="290"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="55">
<attrib name="value" value="2254"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="55">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="55">
<item name="NumNodesOfType_Active_PADOUTPUT" rev="59">
<attrib name="value" value="115"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="59">
<attrib name="value" value="697"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="59">
<attrib name="value" value="3910"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="59">
<attrib name="value" value="5368"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="59">
<attrib name="value" value="308"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="59">
<attrib name="value" value="2239"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="59">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="59">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="55">
<attrib name="value" value="98"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="55">
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="59">
<attrib name="value" value="102"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="59">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="55">
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="59">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="55">
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="59">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="55">
<attrib name="value" value="257"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="55">
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="59">
<attrib name="value" value="238"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="59">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="55">
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="59">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="55">
<attrib name="value" value="270"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="55">
<attrib name="value" value="2"/></item>
<item name="IOB-IOBM" rev="55">
<attrib name="value" value="162"/></item>
<item name="IOB-IOBS" rev="55">
<attrib name="value" value="165"/></item>
<item name="SLICEL-SLICEM" rev="55">
<attrib name="value" value="32"/></item>
<item name="SLICEX-SLICEL" rev="55">
<attrib name="value" value="61"/></item>
<item name="SLICEX-SLICEM" rev="55">
<attrib name="value" value="80"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="59">
<attrib name="value" value="251"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="54">
<item name="AGG_BONDED_IO" rev="58">
<attrib name="value" value="331"/></item>
<item name="AGG_IO" rev="54">
<item name="AGG_IO" rev="58">
<attrib name="value" value="331"/></item>
<item name="AGG_LOCED_IO" rev="54">
<item name="AGG_LOCED_IO" rev="58">
<attrib name="value" value="329"/></item>
<item name="AGG_SLICE" rev="54">
<attrib name="value" value="370"/></item>
<item name="NUM_BONDED_IOB" rev="54">
<item name="AGG_SLICE" rev="58">
<attrib name="value" value="392"/></item>
<item name="NUM_BONDED_IOB" rev="58">
<attrib name="value" value="327"/></item>
<item name="NUM_BONDED_IOBM" rev="54">
<item name="NUM_BONDED_IOBM" rev="58">
<attrib name="value" value="2"/></item>
<item name="NUM_BONDED_IOBS" rev="54">
<attrib name="value" value="2"/></item>
<item name="NUM_BSFULL" rev="54">
<attrib name="value" value="551"/></item>
<item name="NUM_BSLUTONLY" rev="54">
<attrib name="value" value="327"/></item>
<item name="NUM_BSREGONLY" rev="54">
<attrib name="value" value="159"/></item>
<item name="NUM_BSUSED" rev="54">
<attrib name="value" value="1037"/></item>
<item name="NUM_BUFG" rev="54">
<item name="NUM_BONDED_IOBS" rev="58">
<attrib name="value" value="2"/></item>
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<attrib name="value" value="162"/></item>
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<attrib name="value" value="24"/></item>
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<attrib name="value" value="87"/></item>
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<attrib name="value" value="77"/></item>
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<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
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<item name="FF_SR" rev="55">
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<item name="BUFG_BUFG" rev="59">
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<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBS" rev="55">
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<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
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<item name="IOB_IMUX" rev="59">
<attrib name="total" value="1000000"/><attrib name="used" value="160"/></item>
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<item name="IOB_INBUF" rev="59">
<attrib name="total" value="1000000"/><attrib name="used" value="160"/></item>
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<attrib name="total" value="1000000"/><attrib name="used" value="198"/></item>
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<attrib name="total" value="1000000"/><attrib name="used" value="855"/></item>
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<attrib name="total" value="1000000"/><attrib name="used" value="223"/></item>
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<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
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<item name="REG_SR" rev="55">
<attrib name="total" value="1000000"/><attrib name="used" value="699"/></item>
<item name="SELMUX2_1" rev="55">
<attrib name="total" value="1000000"/><attrib name="used" value="24"/></item>
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<attrib name="total" value="1000000"/><attrib name="used" value="678"/></item>
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<attrib name="FF" value="699"/></item>
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<attrib name="CK" value="678"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="59">
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<item name="SYNC_ATTR" rev="59">
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<item name="CLK" rev="59">
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<item name="LUT_OR_MEM" rev="55">
<item name="LUT_OR_MEM" rev="59">
<attrib name="RAM" value="6"/></item>
<item name="RAMMODE" rev="55">
<item name="RAMMODE" rev="59">
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<group name="LUT_OR_MEM6">
<item name="CLK" rev="55">
<item name="CLK" rev="59">
<attrib name="CLK" value="14"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="55">
<item name="LUT_OR_MEM" rev="59">
<attrib name="RAM" value="14"/></item>
<item name="RAMMODE" rev="55">
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<group name="IOBM_OUTBUF">
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<item name="SUSPEND" rev="59">
<attrib name="3STATE" value="2"/></item>
</group>
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<item name="CLK" rev="55">
<attrib name="CLK" value="33"/><attrib name="CLK_INV" value="0"/></item>
<item name="CLK" rev="59">
<attrib name="CLK" value="25"/><attrib name="CLK_INV" value="0"/></item>
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<group name="SLICEM">
<item name="CLK" rev="55">
<item name="CLK" rev="59">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_OUTBUF">
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<item name="DRIVEATTRBOX" rev="59">
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<item name="SUSPEND" rev="55">
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<item name="CLK" rev="55">
<attrib name="CLK" value="206"/><attrib name="CLK_INV" value="0"/></item>
<item name="CLK" rev="59">
<attrib name="CLK" value="197"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_INBUF">
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<item name="DIFF_TERM" rev="59">
<attrib name="TRUE" value="1"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="55">
<attrib name="CK" value="85"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="55">
<attrib name="SRINIT0" value="74"/><attrib name="SRINIT1" value="11"/></item>
<item name="SYNC_ATTR" rev="55">
<attrib name="ASYNC" value="49"/><attrib name="SYNC" value="36"/></item>
<item name="CK" rev="59">
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<item name="SRINIT" rev="59">
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<item name="SYNC_ATTR" rev="59">
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</group>
</ReportConfigData>
<ReportPinData TimeStamp="Wed Jan 12 09:00:15 2011"><group name="NULLMUX">
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<attrib name="value" value="3"/></item>
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<item name="OUT" rev="59">
<attrib name="value" value="3"/></item>
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<group name="REG_SR">
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<item name="CK" rev="55">
<attrib name="value" value="699"/></item>
<item name="D" rev="55">
<attrib name="value" value="699"/></item>
<item name="Q" rev="55">
<attrib name="value" value="699"/></item>
<item name="SR" rev="55">
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<item name="CE" rev="59">
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<item name="CK" rev="59">
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<item name="D" rev="59">
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<item name="Q" rev="59">
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<item name="SR" rev="59">
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<attrib name="value" value="6"/></item>
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<attrib name="value" value="6"/></item>
<item name="A5" rev="55">
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<attrib name="value" value="6"/></item>
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<attrib name="value" value="6"/></item>
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<attrib name="value" value="4"/></item>
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<attrib name="value" value="4"/></item>
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<attrib name="value" value="4"/></item>
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<group name="LUT_OR_MEM6">
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<item name="AQ" rev="55">
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<item name="B5" rev="59">
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<item name="B6" rev="59">
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<item name="BMUX" rev="59">
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<item name="BQ" rev="59">
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<item name="BX" rev="59">
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<item name="B" rev="55">
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<item name="B1" rev="55">
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<item name="0" rev="55">
<attrib name="value" value="24"/></item>
<item name="1" rev="55">
<attrib name="value" value="24"/></item>
<item name="OUT" rev="55">
<attrib name="value" value="24"/></item>
<item name="S0" rev="55">
<attrib name="value" value="24"/></item>
<item name="0" rev="59">
<attrib name="value" value="22"/></item>
<item name="1" rev="59">
<attrib name="value" value="22"/></item>
<item name="OUT" rev="59">
<attrib name="value" value="22"/></item>
<item name="S0" rev="59">
<attrib name="value" value="22"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="55">
<item name="I" rev="59">
<attrib name="value" value="160"/></item>
<item name="OUT" rev="55">
<item name="OUT" rev="59">
<attrib name="value" value="160"/></item>
</group>
<group name="IOB">
<item name="DIFFI_IN" rev="55">
<item name="DIFFI_IN" rev="59">
<attrib name="value" value="1"/></item>
<item name="I" rev="55">
<item name="I" rev="59">
<attrib name="value" value="160"/></item>
<item name="O" rev="55">
<item name="O" rev="59">
<attrib name="value" value="198"/></item>
<item name="PAD" rev="55">
<item name="PAD" rev="59">
<attrib name="value" value="327"/></item>
<item name="PADOUT" rev="55">
<item name="PADOUT" rev="59">
<attrib name="value" value="1"/></item>
<item name="T" rev="55">
<item name="T" rev="59">
<attrib name="value" value="42"/></item>
</group>
<group name="HARD0">
<item name="0" rev="55">
<item name="0" rev="59">
<attrib name="value" value="5"/></item>
</group>
<group name="HARD1">
<item name="1" rev="55">
<item name="1" rev="59">
<attrib name="value" value="2"/></item>
</group>
<group name="FF_SR">
<item name="CE" rev="55">
<attrib name="value" value="42"/></item>
<item name="CK" rev="55">
<attrib name="value" value="85"/></item>
<item name="D" rev="55">
<attrib name="value" value="85"/></item>
<item name="Q" rev="55">
<attrib name="value" value="85"/></item>
<item name="SR" rev="55">
<attrib name="value" value="36"/></item>
<item name="CE" rev="59">
<attrib name="value" value="41"/></item>
<item name="CK" rev="59">
<attrib name="value" value="87"/></item>
<item name="D" rev="59">
<attrib name="value" value="87"/></item>
<item name="Q" rev="59">
<attrib name="value" value="87"/></item>
<item name="SR" rev="59">
<attrib name="value" value="38"/></item>
</group>
<group name="BUFG">
<item name="I0" rev="55">
<attrib name="value" value="2"/></item>
<item name="O" rev="55">
<attrib name="value" value="2"/></item>
<item name="I0" rev="59">
<attrib name="value" value="3"/></item>
<item name="O" rev="59">
<attrib name="value" value="3"/></item>
</group>
</ReportPinData>
<CmdHistory>
......
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="12.3">
<document OS="nt" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Wed Jan 12 08:57:54 2011">
<application stringID="Xst" timeStamp="Fri Jan 28 11:47:26 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="4">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
</item>
<item stringID="User_EnvHost" value="PCBE13225"/>
<item stringID="User_EnvHost" value="bqplv2"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
</row>
</table>
</section>
......@@ -107,6 +111,7 @@
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="9">
<item dataType="int" stringID="XST_16BIT_ADDER" value="2"/>
<item dataType="int" stringID="XST_3BIT_ADDER" value="2"/>
<item dataType="int" stringID="XST_8BIT_ADDER" value="1"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="107">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="69"/>
......@@ -114,11 +119,10 @@
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_22BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="8"/>
<item dataType="int" stringID="XST_30BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_32BIT_REGISTER" value="16"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_7BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="3"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="9">
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/>
......@@ -131,6 +135,7 @@
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="21"/>
<item dataType="int" stringID="XST_32BIT_4TO1_MULTIPLEXER" value="3"/>
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="1"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="64">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="64"/>
......@@ -172,8 +177,8 @@
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="776">
<item dataType="int" stringID="XST_FLIPFLOPS" value="776"/>
<item dataType="int" stringID="XST_REGISTERS" value="757">
<item dataType="int" stringID="XST_FLIPFLOPS" value="757"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="8">
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="2"/>
......@@ -190,26 +195,26 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SFpga.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="1235">
<item dataType="int" stringID="XST_BELS" value="1163">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="22"/>
<item dataType="int" stringID="XST_LUT1" value="86"/>
<item dataType="int" stringID="XST_LUT2" value="211"/>
<item dataType="int" stringID="XST_LUT3" value="149"/>
<item dataType="int" stringID="XST_LUT4" value="85"/>
<item dataType="int" stringID="XST_LUT5" value="123"/>
<item dataType="int" stringID="XST_LUT6" value="284"/>
<item dataType="int" stringID="XST_MUXCY" value="128"/>
<item dataType="int" stringID="XST_MUXF7" value="24"/>
<item dataType="int" stringID="XST_LUT3" value="129"/>
<item dataType="int" stringID="XST_LUT4" value="86"/>
<item dataType="int" stringID="XST_LUT5" value="121"/>
<item dataType="int" stringID="XST_LUT6" value="279"/>
<item dataType="int" stringID="XST_MUXCY" value="106"/>
<item dataType="int" stringID="XST_MUXF7" value="22"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="121"/>
<item dataType="int" stringID="XST_XORCY" value="99"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="784">
<item dataType="int" stringID="XST_FD" value="165"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="765">
<item dataType="int" stringID="XST_FD" value="166"/>
<item dataType="int" stringID="XST_FDE" value="104"/>
<item dataType="int" stringID="XST_FDPE" value="1"/>
<item dataType="int" stringID="XST_FDR" value="170"/>
<item dataType="int" stringID="XST_FDRE" value="310"/>
<item dataType="int" stringID="XST_FDR" value="149"/>
<item dataType="int" stringID="XST_FDRE" value="311"/>
<item dataType="int" stringID="XST_FDS" value="26"/>
<item dataType="int" stringID="XST_FDSE" value="8"/>
</item>
......@@ -219,12 +224,12 @@
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="8">
<item dataType="int" stringID="XST_SRLC16E" value="8"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="3">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="2"/>
<item dataType="int" stringID="XST_BUFGP" value="1"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="304">
<item dataType="int" stringID="XST_IBUF" value="77"/>
<item dataType="int" stringID="XST_IO_BUFFERS" value="305">
<item dataType="int" stringID="XST_IBUF" value="78"/>
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/>
<item dataType="int" stringID="XST_OBUF" value="154"/>
<item dataType="int" stringID="XST_OBUFT" value="30"/>
......@@ -233,26 +238,26 @@
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx150tfgg676-3"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="784"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="976"/>
<item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="960"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="765"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="950"/>
<item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="934"/>
<item AVAILABLE="21680" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="16"/>
<item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="8"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1206"/>
<item AVAILABLE="1206" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="422"/>
<item AVAILABLE="1206" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="230"/>
<item AVAILABLE="1206" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="554"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="25"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1182"/>
<item AVAILABLE="1182" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="417"/>
<item AVAILABLE="1182" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="232"/>
<item AVAILABLE="1182" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="533"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="26"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="365"/>
<item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="316"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
<item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="317"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="3"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="132"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="129"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="17"/>
</section>
</application>
......
......@@ -111,7 +111,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1294819093" xil_pn:in_ck="-394197636941444327" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1294819073">
<transform xil_pn:end_ts="1296211673" xil_pn:in_ck="-394197636941444327" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1296211644">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -133,7 +133,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1294819098" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1294819093">
<transform xil_pn:end_ts="1296211680" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1296211673">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -143,12 +143,10 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1294819144" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1294819098">
<transform xil_pn:end_ts="1296211741" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1296211680">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SFpga.pcf"/>
<outfile xil_pn:name="SFpga_map.map"/>
<outfile xil_pn:name="SFpga_map.mrp"/>
......@@ -159,7 +157,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1294819188" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1294819144">
<transform xil_pn:end_ts="1296212125" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1296211741">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -174,7 +172,7 @@
<outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1294819232" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-774614059244361160" xil_pn:start_ts="1294819188">
<transform xil_pn:end_ts="1296212185" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-774614059244361160" xil_pn:start_ts="1296212125">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -202,6 +200,8 @@
<transform xil_pn:end_ts="1294819273" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1294819271">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570">
<status xil_pn:value="SuccessfullyRun"/>
......@@ -219,7 +219,7 @@
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1294819188" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1294819177">
<transform xil_pn:end_ts="1296212125" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1296212103">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/>
......
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1294819092
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1296211672
OK
......@@ -8,9 +8,6 @@
<msg type="warning" file="Bitgen" num="244" delta="old" >A StartupClk setting other than JtagClk is being used to generate a bitstream in IEEE1532 format. The IEEE1532 option implies that JTAG configuration will be used. Using a StartupClk setting other than JtagClk could prevent proper device startup.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/i_VmeInterface/Stb_oq</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
......@@ -128,9 +125,6 @@
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VcTcXo_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRLoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
......
......@@ -8,7 +8,7 @@
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N504</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">54</arg> more times for the following (max. 5 shown):
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">53</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N506,
VmeAm_ib6&lt;2&gt;_IBUF,
VmeAm_ib6&lt;1&gt;_IBUF,
......@@ -131,8 +131,6 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
......@@ -142,9 +140,6 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">i_Core/i_VmeInterface/Stb_oq</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
......@@ -262,9 +257,6 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">VcTcXo_ik_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">WRLoS_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
......
......@@ -5,15 +5,9 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="137" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;VcTcXo_ik&quot; TNM_NET = VcTcXo_ik;&gt; [SFpga.ucf(701)]</arg>: No appropriate instances for the TNM constraint are driven by &quot;<arg fmt="%s" index="2">VcTcXo_ik</arg>&quot;.
</msg>
<msg type="warning" file="ConstraintSystem" num="137" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;VmeSysClk_ik&quot; TNM_NET = VmeSysClk_ik;&gt; [SFpga.ucf(702)]</arg>: No appropriate instances for the TNM constraint are driven by &quot;<arg fmt="%s" index="2">VmeSysClk_ik</arg>&quot;.
</msg>
<msg type="warning" file="ConstraintSystem" num="194" delta="old" >The <arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">VcTcXo_ik</arg>&apos;, does not directly or indirectly drive any flip-flops, latches and/or RAMs and is not actively used by any referencing constraint.
</msg>
<msg type="warning" file="ConstraintSystem" num="194" delta="old" >The <arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">VmeSysClk_ik</arg>&apos;, does not directly or indirectly drive any flip-flops, latches and/or RAMs and is not actively used by any referencing constraint.
</msg>
......
......@@ -5,8 +5,6 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsRamSwpOvr_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
......@@ -124,9 +122,6 @@
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">DdsPdClk_ik_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">VcTcXo_ik_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">WRLoS_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
......@@ -157,11 +152,11 @@
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">50</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">49</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">50</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">49</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
......
......@@ -8,38 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/AddrDecoderWBSys.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Debouncer.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4InputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/InterruptManagerWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Monostable.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Slv2SerWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SpiMasterWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/VmeToWishBone.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v\&quot; into library work</arg>
</msg>
</messages>
......@@ -5,8 +5,6 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
......
......@@ -191,9 +191,6 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VmeTms_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">VcTcXo_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">AFpgaProgDone_io</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
......@@ -362,9 +359,6 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Adr_ib22&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">AckGenericInputRegs_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Rst_irq</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
......@@ -377,9 +371,6 @@
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">Stb_oq</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">VmeToWishBone</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;Cyc_oq&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_AddressDecoderWB/StbGenericInputRegs_o</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">i_Core/i_SpiMasterWB/SS_onb32_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">SFpga</arg>&gt;.
</msg>
......
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-01-12T08:57:11</DateModified>
<DateModified>2011-01-28T11:09:00</DateModified>
<ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-20T13:49:08</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......@@ -22,9 +22,9 @@
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SFpga_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SFpga_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SFpga_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SFpga.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SFpga_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SFpga_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SFpga.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SFpga_par.xrpt" showConstraints="0" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SFpga_par.xrpt" showConstraints="0" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SFpga.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SFpga_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SFpga_html/tim/report.htm" label="CPLD Timing Report" />
......@@ -44,7 +44,7 @@
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view program="xst" WrapMessages="true" showErrors="1" contextTags="XST_ONLY,EDK_OFF" showInfos="0" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" showWarnings="1" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
......
......@@ -39,7 +39,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000040101000100000000000000000000000064ffffffff000000810000000000000004000000ac00000001000000000000002400000001000000000000006600000001000000000000006c0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>AddrDecoderWBSys.v</CurrentItem>
</ItemView>
......@@ -50,7 +50,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000010001000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
......@@ -64,13 +64,13 @@
<ClosedNode>Implement Design/Translate</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Generate Target PROM/ACE File</SelectedItem>
<SelectedItem>Design Summary/Reports</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >22</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >20</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000189000000010000000100000000000000000000000064ffffffff000000810000000000000001000001890000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000191000000010000000100000000000000000000000064ffffffff000000810000000000000001000001910000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Target PROM/ACE File</CurrentItem>
<CurrentItem>Design Summary/Reports</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
......
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1381</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4478</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4478</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4144</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>14.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>20.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>28.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>28.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>28.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>28.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>28.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>28.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>18.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>12.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>9.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>12.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>7.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>9.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>6.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1355</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4356</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4356</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>127</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>23.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>29.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>339.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>351.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>354.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>14.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>22.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>14.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>10.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>6.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0603</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0615</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
Release 12.3 - Bitgen M.70d (nt64)
Release 12.3 - Bitgen M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx150t.nph' in environment
C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf.
Wed Jan 12 08:59:53 2011
Fri Jan 28 11:55:36 2011
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:26 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:26 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
WARNING:Bitgen:244 - A StartupClk setting other than JtagClk is being used to
generate a bitstream in IEEE1532 format. The IEEE1532 option implies that
......@@ -126,10 +126,6 @@ There were 0 CONFIG constraint(s) processed from SFpga.pcf.
Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
......@@ -208,8 +204,6 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
......@@ -231,7 +225,7 @@ WARNING:PhysDesignRules:367 - The signal <Fmc2PrsntM2C_in_IBUF> is incomplete.
WARNING:PhysDesignRules:367 - The signal
<i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
DRC detected 0 errors and 51 warnings. Please see the previously displayed
DRC detected 0 errors and 49 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "sfpga.bit".
......
Release 12.3 Drc M.70d (nt64)
Release 12.3 Drc M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Wed Jan 12 08:59:53 2011
Fri Jan 28 11:55:36 2011
drc -z SFpga.ncd SFpga.pcf
WARNING:PhysDesignRules:372 - Gated clock. Clock net
i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
......@@ -87,8 +83,6 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
......@@ -110,5 +104,5 @@ WARNING:PhysDesignRules:367 - The signal <Fmc2PrsntM2C_in_IBUF> is incomplete.
WARNING:PhysDesignRules:367 - The signal
<i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O> is incomplete. The
signal does not drive any load pins in the design.
DRC detected 0 errors and 51 warnings. Please see the previously displayed
DRC detected 0 errors and 49 warnings. Please see the previously displayed
individual error or warning messages for more details.
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -11,13 +11,13 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
<TD><xtag-property name="OSPlatform">NT64</xtag-property></TD>
<TD><xtag-property name="OSPlatform">NT</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD><xtag-property name="TargetDevice">xc6slx150t</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">26</xtag-property></TD>
<TD><xtag-property name="RandomID">d36a4175861f4f48ac5a6ada421762f9</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">28</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD>
</TR>
......@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2011-01-12T09:00:16</xtag-property></TD>
<TD><xtag-property name="Date Generated">2011-01-28T11:56:19</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
......@@ -39,27 +39,27 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft </xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows XP Professional</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>major release (build 7600)</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 3 (build 2600)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value> Intel(R) Pentium(R) D CPU 3.40GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3158 MHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3389 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft </xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows XP Professional</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>major release (build 7600)</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 3 (build 2600)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value> Intel(R) Pentium(R) D CPU 3.40GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3158 MHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3389 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
......@@ -89,8 +89,8 @@
<LI><xtag-item1>23-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>24-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>3-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>30-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>4-bit updown counter=1</xtag-item1></LI>
<LI><xtag-item1>8-bit up counter=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FSMs=2">FSMs=2</xtag-group-name>
......@@ -134,93 +134,93 @@
<LI><xtag-item1>AGG_BONDED_IO=331</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=331</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=329</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=370</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=392</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=327</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=551</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=327</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=159</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1037</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=479</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=372</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=209</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1060</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=3</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=325</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=146</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=124</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=83</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=621</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=616</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=5</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=5</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=83</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=59</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=51</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=307</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=35</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=26</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1124</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_F7MUX=24</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=784</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=127</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=337</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=29</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=27</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1078</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_F7MUX=22</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=765</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=166</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O5ANDO6=2</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=4</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=76</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=71</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=1762</xtag-item1></LI>
<LI><xtag-item1>NumNets_Active=1735</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=32</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=163</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=18</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=243</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=200</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=226</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=278</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2154</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=353</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=167</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=38</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=253</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2317</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=354</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=185</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=33</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=242</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=242</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3494</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1460</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1303</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3401</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1440</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1281</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=135</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=114</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=772</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4039</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=6103</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=290</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2254</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=115</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=697</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=3910</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5368</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=308</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2239</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=98</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=102</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=257</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=238</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=270</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=251</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI>
<LI><xtag-item1>BUFG-BUFGMUX=3</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=162</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=32</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=61</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=80</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=24</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=87</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=77</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
......@@ -229,10 +229,10 @@
<TD>
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
<UL>
<LI><xtag-item2>BUFG=2</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI>
<LI><xtag-item2>CARRY4=35</xtag-item2></LI>
<LI><xtag-item2>FF_SR=85</xtag-item2></LI>
<LI><xtag-item2>BUFG=3</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=3</xtag-item2></LI>
<LI><xtag-item2>CARRY4=29</xtag-item2></LI>
<LI><xtag-item2>FF_SR=87</xtag-item2></LI>
<LI><xtag-item2>HARD0=5</xtag-item2></LI>
<LI><xtag-item2>HARD1=2</xtag-item2></LI>
<LI><xtag-item2>IOB=327</xtag-item2></LI>
......@@ -242,17 +242,17 @@
<LI><xtag-item2>IOB_IMUX=160</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=160</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI>
<LI><xtag-item2>LUT5=242</xtag-item2></LI>
<LI><xtag-item2>LUT6=855</xtag-item2></LI>
<LI><xtag-item2>LUT5=223</xtag-item2></LI>
<LI><xtag-item2>LUT6=828</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM5=6</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM6=14</xtag-item2></LI>
<LI><xtag-item2>NULLMUX=3</xtag-item2></LI>
<LI><xtag-item2>PAD=331</xtag-item2></LI>
<LI><xtag-item2>REG_SR=699</xtag-item2></LI>
<LI><xtag-item2>SELMUX2_1=24</xtag-item2></LI>
<LI><xtag-item2>SLICEL=59</xtag-item2></LI>
<LI><xtag-item2>REG_SR=678</xtag-item2></LI>
<LI><xtag-item2>SELMUX2_1=22</xtag-item2></LI>
<LI><xtag-item2>SLICEL=51</xtag-item2></LI>
<LI><xtag-item2>SLICEM=4</xtag-item2></LI>
<LI><xtag-item2>SLICEX=307</xtag-item2></LI>
<LI><xtag-item2>SLICEX=337</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
......@@ -264,9 +264,9 @@
<TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:85] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:74] [SRINIT1:11]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:49] [SYNC:36]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:87] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:76] [SRINIT1:11]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:49] [SYNC:38]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name>
......@@ -306,17 +306,17 @@
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:699] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:699]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:672] [SRINIT1:27]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:221] [SYNC:478]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:678] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:678]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:651] [SRINIT1:27]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:222] [SYNC:456]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:33] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:25] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
......@@ -326,7 +326,7 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:206] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:197] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
......@@ -338,44 +338,44 @@
<TD>
<xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
<LI><xtag-item1>I0=3</xtag-item1></LI>
<LI><xtag-item1>O=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
<LI><xtag-item1>I0=3</xtag-item1></LI>
<LI><xtag-item1>O=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL>
<LI><xtag-item1>CIN=27</xtag-item1></LI>
<LI><xtag-item1>CIN=21</xtag-item1></LI>
<LI><xtag-item1>CO1=2</xtag-item1></LI>
<LI><xtag-item1>CO2=1</xtag-item1></LI>
<LI><xtag-item1>CO3=27</xtag-item1></LI>
<LI><xtag-item1>CO3=21</xtag-item1></LI>
<LI><xtag-item1>CYINIT=8</xtag-item1></LI>
<LI><xtag-item1>DI0=35</xtag-item1></LI>
<LI><xtag-item1>DI1=34</xtag-item1></LI>
<LI><xtag-item1>DI2=32</xtag-item1></LI>
<LI><xtag-item1>DI3=27</xtag-item1></LI>
<LI><xtag-item1>O0=31</xtag-item1></LI>
<LI><xtag-item1>O1=31</xtag-item1></LI>
<LI><xtag-item1>O2=30</xtag-item1></LI>
<LI><xtag-item1>O3=29</xtag-item1></LI>
<LI><xtag-item1>S0=35</xtag-item1></LI>
<LI><xtag-item1>S1=35</xtag-item1></LI>
<LI><xtag-item1>S2=33</xtag-item1></LI>
<LI><xtag-item1>S3=31</xtag-item1></LI>
<LI><xtag-item1>DI0=29</xtag-item1></LI>
<LI><xtag-item1>DI1=29</xtag-item1></LI>
<LI><xtag-item1>DI2=27</xtag-item1></LI>
<LI><xtag-item1>DI3=21</xtag-item1></LI>
<LI><xtag-item1>O0=25</xtag-item1></LI>
<LI><xtag-item1>O1=25</xtag-item1></LI>
<LI><xtag-item1>O2=25</xtag-item1></LI>
<LI><xtag-item1>O3=24</xtag-item1></LI>
<LI><xtag-item1>S0=29</xtag-item1></LI>
<LI><xtag-item1>S1=29</xtag-item1></LI>
<LI><xtag-item1>S2=28</xtag-item1></LI>
<LI><xtag-item1>S3=26</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=42</xtag-item1></LI>
<LI><xtag-item1>CK=85</xtag-item1></LI>
<LI><xtag-item1>D=85</xtag-item1></LI>
<LI><xtag-item1>Q=85</xtag-item1></LI>
<LI><xtag-item1>SR=36</xtag-item1></LI>
<LI><xtag-item1>CE=41</xtag-item1></LI>
<LI><xtag-item1>CK=87</xtag-item1></LI>
<LI><xtag-item1>D=87</xtag-item1></LI>
<LI><xtag-item1>Q=87</xtag-item1></LI>
<LI><xtag-item1>SR=38</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
......@@ -440,23 +440,23 @@
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A1=21</xtag-item1></LI>
<LI><xtag-item1>A1=26</xtag-item1></LI>
<LI><xtag-item1>A2=27</xtag-item1></LI>
<LI><xtag-item1>A3=98</xtag-item1></LI>
<LI><xtag-item1>A4=101</xtag-item1></LI>
<LI><xtag-item1>A5=57</xtag-item1></LI>
<LI><xtag-item1>O5=242</xtag-item1></LI>
<LI><xtag-item1>A3=96</xtag-item1></LI>
<LI><xtag-item1>A4=102</xtag-item1></LI>
<LI><xtag-item1>A5=56</xtag-item1></LI>
<LI><xtag-item1>O5=223</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=286</xtag-item1></LI>
<LI><xtag-item1>A2=407</xtag-item1></LI>
<LI><xtag-item1>A3=525</xtag-item1></LI>
<LI><xtag-item1>A4=745</xtag-item1></LI>
<LI><xtag-item1>A5=770</xtag-item1></LI>
<LI><xtag-item1>A6=847</xtag-item1></LI>
<LI><xtag-item1>O6=855</xtag-item1></LI>
<LI><xtag-item1>A1=281</xtag-item1></LI>
<LI><xtag-item1>A2=405</xtag-item1></LI>
<LI><xtag-item1>A3=497</xtag-item1></LI>
<LI><xtag-item1>A4=716</xtag-item1></LI>
<LI><xtag-item1>A5=745</xtag-item1></LI>
<LI><xtag-item1>A6=821</xtag-item1></LI>
<LI><xtag-item1>O6=828</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -513,67 +513,67 @@
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=373</xtag-item1></LI>
<LI><xtag-item1>CK=699</xtag-item1></LI>
<LI><xtag-item1>D=699</xtag-item1></LI>
<LI><xtag-item1>Q=699</xtag-item1></LI>
<LI><xtag-item1>SR=479</xtag-item1></LI>
<LI><xtag-item1>CE=375</xtag-item1></LI>
<LI><xtag-item1>CK=678</xtag-item1></LI>
<LI><xtag-item1>D=678</xtag-item1></LI>
<LI><xtag-item1>Q=678</xtag-item1></LI>
<LI><xtag-item1>SR=457</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name>
<UL>
<LI><xtag-item1>0=24</xtag-item1></LI>
<LI><xtag-item1>1=24</xtag-item1></LI>
<LI><xtag-item1>OUT=24</xtag-item1></LI>
<LI><xtag-item1>S0=24</xtag-item1></LI>
<LI><xtag-item1>0=22</xtag-item1></LI>
<LI><xtag-item1>1=22</xtag-item1></LI>
<LI><xtag-item1>OUT=22</xtag-item1></LI>
<LI><xtag-item1>S0=22</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A=6</xtag-item1></LI>
<LI><xtag-item1>A1=5</xtag-item1></LI>
<LI><xtag-item1>A2=6</xtag-item1></LI>
<LI><xtag-item1>A3=17</xtag-item1></LI>
<LI><xtag-item1>A4=33</xtag-item1></LI>
<LI><xtag-item1>A5=26</xtag-item1></LI>
<LI><xtag-item1>A6=42</xtag-item1></LI>
<LI><xtag-item1>AMUX=9</xtag-item1></LI>
<LI><xtag-item1>AQ=29</xtag-item1></LI>
<LI><xtag-item1>AX=6</xtag-item1></LI>
<LI><xtag-item1>B=5</xtag-item1></LI>
<LI><xtag-item1>B1=7</xtag-item1></LI>
<LI><xtag-item1>B2=7</xtag-item1></LI>
<LI><xtag-item1>B3=14</xtag-item1></LI>
<LI><xtag-item1>B4=34</xtag-item1></LI>
<LI><xtag-item1>B5=25</xtag-item1></LI>
<LI><xtag-item1>B6=41</xtag-item1></LI>
<LI><xtag-item1>BMUX=10</xtag-item1></LI>
<LI><xtag-item1>BQ=29</xtag-item1></LI>
<LI><xtag-item1>A=11</xtag-item1></LI>
<LI><xtag-item1>A1=7</xtag-item1></LI>
<LI><xtag-item1>A2=12</xtag-item1></LI>
<LI><xtag-item1>A3=16</xtag-item1></LI>
<LI><xtag-item1>A4=32</xtag-item1></LI>
<LI><xtag-item1>A5=25</xtag-item1></LI>
<LI><xtag-item1>A6=41</xtag-item1></LI>
<LI><xtag-item1>AMUX=10</xtag-item1></LI>
<LI><xtag-item1>AQ=23</xtag-item1></LI>
<LI><xtag-item1>AX=7</xtag-item1></LI>
<LI><xtag-item1>B=8</xtag-item1></LI>
<LI><xtag-item1>B1=6</xtag-item1></LI>
<LI><xtag-item1>B2=9</xtag-item1></LI>
<LI><xtag-item1>B3=12</xtag-item1></LI>
<LI><xtag-item1>B4=31</xtag-item1></LI>
<LI><xtag-item1>B5=22</xtag-item1></LI>
<LI><xtag-item1>B6=38</xtag-item1></LI>
<LI><xtag-item1>BMUX=12</xtag-item1></LI>
<LI><xtag-item1>BQ=23</xtag-item1></LI>
<LI><xtag-item1>BX=6</xtag-item1></LI>
<LI><xtag-item1>C1=8</xtag-item1></LI>
<LI><xtag-item1>C2=13</xtag-item1></LI>
<LI><xtag-item1>C3=33</xtag-item1></LI>
<LI><xtag-item1>C4=49</xtag-item1></LI>
<LI><xtag-item1>C5=40</xtag-item1></LI>
<LI><xtag-item1>C6=55</xtag-item1></LI>
<LI><xtag-item1>C1=10</xtag-item1></LI>
<LI><xtag-item1>C2=14</xtag-item1></LI>
<LI><xtag-item1>C3=25</xtag-item1></LI>
<LI><xtag-item1>C4=41</xtag-item1></LI>
<LI><xtag-item1>C5=34</xtag-item1></LI>
<LI><xtag-item1>C6=49</xtag-item1></LI>
<LI><xtag-item1>CE=10</xtag-item1></LI>
<LI><xtag-item1>CIN=27</xtag-item1></LI>
<LI><xtag-item1>CLK=33</xtag-item1></LI>
<LI><xtag-item1>CMUX=30</xtag-item1></LI>
<LI><xtag-item1>COUT=27</xtag-item1></LI>
<LI><xtag-item1>CQ=28</xtag-item1></LI>
<LI><xtag-item1>CX=26</xtag-item1></LI>
<LI><xtag-item1>CIN=21</xtag-item1></LI>
<LI><xtag-item1>CLK=25</xtag-item1></LI>
<LI><xtag-item1>CMUX=29</xtag-item1></LI>
<LI><xtag-item1>COUT=21</xtag-item1></LI>
<LI><xtag-item1>CQ=23</xtag-item1></LI>
<LI><xtag-item1>CX=25</xtag-item1></LI>
<LI><xtag-item1>D=2</xtag-item1></LI>
<LI><xtag-item1>D1=15</xtag-item1></LI>
<LI><xtag-item1>D2=27</xtag-item1></LI>
<LI><xtag-item1>D3=34</xtag-item1></LI>
<LI><xtag-item1>D4=49</xtag-item1></LI>
<LI><xtag-item1>D5=39</xtag-item1></LI>
<LI><xtag-item1>D6=54</xtag-item1></LI>
<LI><xtag-item1>D1=13</xtag-item1></LI>
<LI><xtag-item1>D2=25</xtag-item1></LI>
<LI><xtag-item1>D3=26</xtag-item1></LI>
<LI><xtag-item1>D4=42</xtag-item1></LI>
<LI><xtag-item1>D5=32</xtag-item1></LI>
<LI><xtag-item1>D6=47</xtag-item1></LI>
<LI><xtag-item1>DMUX=7</xtag-item1></LI>
<LI><xtag-item1>DQ=27</xtag-item1></LI>
<LI><xtag-item1>DX=7</xtag-item1></LI>
<LI><xtag-item1>SR=25</xtag-item1></LI>
<LI><xtag-item1>DQ=21</xtag-item1></LI>
<LI><xtag-item1>DX=6</xtag-item1></LI>
<LI><xtag-item1>SR=16</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -629,49 +629,49 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=108</xtag-item1></LI>
<LI><xtag-item1>A1=81</xtag-item1></LI>
<LI><xtag-item1>A2=109</xtag-item1></LI>
<LI><xtag-item1>A3=146</xtag-item1></LI>
<LI><xtag-item1>A4=164</xtag-item1></LI>
<LI><xtag-item1>A5=179</xtag-item1></LI>
<LI><xtag-item1>A6=180</xtag-item1></LI>
<LI><xtag-item1>AMUX=36</xtag-item1></LI>
<LI><xtag-item1>A=144</xtag-item1></LI>
<LI><xtag-item1>A1=99</xtag-item1></LI>
<LI><xtag-item1>A2=135</xtag-item1></LI>
<LI><xtag-item1>A3=175</xtag-item1></LI>
<LI><xtag-item1>A4=193</xtag-item1></LI>
<LI><xtag-item1>A5=211</xtag-item1></LI>
<LI><xtag-item1>A6=216</xtag-item1></LI>
<LI><xtag-item1>AMUX=38</xtag-item1></LI>
<LI><xtag-item1>AQ=149</xtag-item1></LI>
<LI><xtag-item1>AX=67</xtag-item1></LI>
<LI><xtag-item1>B=52</xtag-item1></LI>
<LI><xtag-item1>B1=53</xtag-item1></LI>
<LI><xtag-item1>B2=75</xtag-item1></LI>
<LI><xtag-item1>B3=106</xtag-item1></LI>
<LI><xtag-item1>B4=124</xtag-item1></LI>
<LI><xtag-item1>B5=141</xtag-item1></LI>
<LI><xtag-item1>B6=139</xtag-item1></LI>
<LI><xtag-item1>BMUX=30</xtag-item1></LI>
<LI><xtag-item1>BQ=150</xtag-item1></LI>
<LI><xtag-item1>BX=59</xtag-item1></LI>
<LI><xtag-item1>C=86</xtag-item1></LI>
<LI><xtag-item1>C1=68</xtag-item1></LI>
<LI><xtag-item1>C2=86</xtag-item1></LI>
<LI><xtag-item1>C3=113</xtag-item1></LI>
<LI><xtag-item1>C4=132</xtag-item1></LI>
<LI><xtag-item1>C5=149</xtag-item1></LI>
<LI><xtag-item1>C6=151</xtag-item1></LI>
<LI><xtag-item1>CE=99</xtag-item1></LI>
<LI><xtag-item1>CLK=206</xtag-item1></LI>
<LI><xtag-item1>CMUX=24</xtag-item1></LI>
<LI><xtag-item1>AX=73</xtag-item1></LI>
<LI><xtag-item1>B=56</xtag-item1></LI>
<LI><xtag-item1>B1=55</xtag-item1></LI>
<LI><xtag-item1>B2=76</xtag-item1></LI>
<LI><xtag-item1>B3=108</xtag-item1></LI>
<LI><xtag-item1>B4=128</xtag-item1></LI>
<LI><xtag-item1>B5=146</xtag-item1></LI>
<LI><xtag-item1>B6=144</xtag-item1></LI>
<LI><xtag-item1>BMUX=29</xtag-item1></LI>
<LI><xtag-item1>BQ=154</xtag-item1></LI>
<LI><xtag-item1>BX=66</xtag-item1></LI>
<LI><xtag-item1>C=60</xtag-item1></LI>
<LI><xtag-item1>C1=55</xtag-item1></LI>
<LI><xtag-item1>C2=70</xtag-item1></LI>
<LI><xtag-item1>C3=93</xtag-item1></LI>
<LI><xtag-item1>C4=111</xtag-item1></LI>
<LI><xtag-item1>C5=126</xtag-item1></LI>
<LI><xtag-item1>C6=126</xtag-item1></LI>
<LI><xtag-item1>CE=93</xtag-item1></LI>
<LI><xtag-item1>CLK=197</xtag-item1></LI>
<LI><xtag-item1>CMUX=23</xtag-item1></LI>
<LI><xtag-item1>CQ=129</xtag-item1></LI>
<LI><xtag-item1>CX=59</xtag-item1></LI>
<LI><xtag-item1>D=98</xtag-item1></LI>
<LI><xtag-item1>D1=69</xtag-item1></LI>
<LI><xtag-item1>D2=104</xtag-item1></LI>
<LI><xtag-item1>D3=136</xtag-item1></LI>
<LI><xtag-item1>D4=160</xtag-item1></LI>
<LI><xtag-item1>D5=180</xtag-item1></LI>
<LI><xtag-item1>D6=185</xtag-item1></LI>
<LI><xtag-item1>CX=63</xtag-item1></LI>
<LI><xtag-item1>D=73</xtag-item1></LI>
<LI><xtag-item1>D1=61</xtag-item1></LI>
<LI><xtag-item1>D2=84</xtag-item1></LI>
<LI><xtag-item1>D3=114</xtag-item1></LI>
<LI><xtag-item1>D4=138</xtag-item1></LI>
<LI><xtag-item1>D5=158</xtag-item1></LI>
<LI><xtag-item1>D6=160</xtag-item1></LI>
<LI><xtag-item1>DMUX=26</xtag-item1></LI>
<LI><xtag-item1>DQ=152</xtag-item1></LI>
<LI><xtag-item1>DX=60</xtag-item1></LI>
<LI><xtag-item1>SR=142</xtag-item1></LI>
<LI><xtag-item1>DQ=150</xtag-item1></LI>
<LI><xtag-item1>DX=62</xtag-item1></LI>
<LI><xtag-item1>SR=132</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -883,13 +883,24 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>27</xtag-total-run-started></td>
<td><xtag-total-run-finished>21</xtag-total-run-finished></td>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>10</xtag-total-run-started></td>
<td><xtag-total-run-finished>10</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -897,9 +908,19 @@
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>31</xtag-total-run-started></td>
<td><xtag-total-run-finished>31</xtag-total-run-finished></td>
<td><xtag-program-name>edif2ngd</xtag-program-name></td>
<td><xtag-total-run-started>5</xtag-total-run-started></td>
<td><xtag-total-run-finished>5</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ibiswriter</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -908,8 +929,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>30</xtag-total-run-started></td>
<td><xtag-total-run-finished>30</xtag-total-run-finished></td>
<td><xtag-total-run-started>25</xtag-total-run-started></td>
<td><xtag-total-run-finished>15</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -918,8 +939,8 @@
</tr>
<tr>
<td><xtag-program-name>ngc2edif</xtag-program-name></td>
<td><xtag-total-run-started>5</xtag-total-run-started></td>
<td><xtag-total-run-finished>5</xtag-total-run-finished></td>
<td><xtag-total-run-started>14</xtag-total-run-started></td>
<td><xtag-total-run-finished>14</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -938,8 +959,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>30</xtag-total-run-started></td>
<td><xtag-total-run-finished>30</xtag-total-run-finished></td>
<td><xtag-total-run-started>15</xtag-total-run-started></td>
<td><xtag-total-run-finished>15</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -948,8 +969,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>30</xtag-total-run-started></td>
<td><xtag-total-run-finished>30</xtag-total-run-finished></td>
<td><xtag-total-run-started>16</xtag-total-run-started></td>
<td><xtag-total-run-finished>16</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -958,8 +979,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>32</xtag-total-run-started></td>
<td><xtag-total-run-finished>32</xtag-total-run-finished></td>
<td><xtag-total-run-started>39</xtag-total-run-started></td>
<td><xtag-total-run-finished>39</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -967,7 +988,35 @@
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISEHelpViewerData">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Help Statistics</B></TD></TR>
<TR ALIGN=LEFT><TD COLSPAN=2><xtag-group><B><xtag-group-name name="SearchFoundList">
Search words with results</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>input standard </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>lvds </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>verilog </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group><TR VALIGN=TOP><TD COLSPAN=2><xtag-group><B><xtag-group-name name="OpenedHelpFiles">
Help files</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>/doc/usenglish/isehelp/cgn_c_df_verilog_flow.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/cgn_c_df_verilog_instantiation_example.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/cgn_p_add_ip_com_flow.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/dsm_c_design_summary_overview.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/gls_r_glossary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_constraints_entry_methods.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_pin_assignment_pace.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ism_r_verlang_expressions.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pn_db_npw_project_summary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/pp_db_hdl_options_syn.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pp_p_process_io_pin_planning_pre_syn.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/sse_p_adding_attr.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="Project Statistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Project Statistics</B></TD></TR>
......@@ -991,7 +1040,7 @@
<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>26</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>28</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
......@@ -1023,21 +1072,21 @@
<xtag-section name="UnisimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>165</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>166</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>104</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDPE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>170</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>310</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>149</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>311</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>26</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDSE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>77</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>78</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD>
</TR>
<TR>
......@@ -1048,14 +1097,14 @@
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>211</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>149</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>85</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>123</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>129</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>86</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>121</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>284</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>128</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>24</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>279</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>106</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>22</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>154</xtag-preunisim-param-value></TD>
</TR>
<TR>
......@@ -1067,16 +1116,16 @@
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>121</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>99</xtag-preunisim-param-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>165</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>166</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>104</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDPE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>170</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>310</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>149</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>311</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>26</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDSE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD>
</TR>
......@@ -1093,14 +1142,14 @@
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>211</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>149</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>85</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>123</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>284</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>129</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>86</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>121</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>279</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>128</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>24</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>106</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>22</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>154</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
</TR>
......@@ -1113,6 +1162,6 @@
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_TS_TIMESPEC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>121</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>99</xtag-postunisim-param-value></TD>
</xtag-section></TABLE>
&nbsp;<BR></BODY></HTML>
......@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=26
ProjectIteration=28
WebTalk Summary
----------------
......@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2011-01-12T09:00:32. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2011-01-28T11:56:25. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Wed Jan 12 08:59:48 2011">
<application name="pn" timeStamp="Fri Jan 28 11:55:26 2011">
<section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="26" type="project"/>
<property name="ProjectIteration" value="28" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section>
......@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="26" type="process"/>
<property name="PROP_intWbtProjectIteration" value="28" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
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