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VME FMC Carrier VFC
Commits
58639a1a
Commit
58639a1a
authored
Jan 31, 2011
by
Andrea Boccardi
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Plain Diff
chenges in the use of the FP gpio
parent
777894d8
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5 changed files
with
14 additions
and
84 deletions
+14
-84
ToDo.txt
trunk/hdl/ToDo.txt
+0
-39
ApplicationFpga.v
trunk/hdl/design/ApplicationFpga.v
+4
-3
SystemFpga.v
trunk/hdl/design/SystemFpga.v
+5
-34
tb_VFC.v
trunk/hdl/testbench/tb_VFC.v
+2
-2
mysim.py
trunk/software/mysim.py
+3
-6
No files found.
trunk/hdl/ToDo.txt
deleted
100644 → 0
View file @
777894d8
Change the custom interface of the VMEInterface for a wishbone one
Si57x:
model
interface
AD9516 (PLL):
model
AD5666 (DAC):
model
AD9910 (DDS):
model
interface
AD7888 (ADC):
model
MT41J128M16 (DDR):
model
interface <= Xilinx with wishbone by Mathieu
CY7C1470 (SRAM):
model <= from Cypress but probably with excessive reolution (10ps)
interface
M25P128 (E2PROM):
model <= from numonix, but to be reworked
interface <= SPI one is enough?
DS18B20U+ (Temp + UniqueID):
model
Interface <= 1-wire from KK?
Xilinx-MGT
Xilinx-IOSerializer
trunk/hdl/design/ApplicationFpga.v
View file @
58639a1a
...
...
@@ -67,10 +67,11 @@ always @(posedge Clk_k) Rst_rq <= `dly ~DeboucedPushButton_q || RstWB;
// Front Panel Signals
//#####################################
assign
FpGpIo_iob4
[
4
]
=
Clk_k
;
assign
FpGpIo_iob4
[
3
]
=
Rst_rq
;
assign
FpGpIo_iob4
[
2
]
=
We
&&
Cyc
&&
StbDebugRegs
;
assign
FpGpIo_iob4
[
4
]
=
AFpgaProgD_iob8
[
3
]
;
assign
FpGpIo_iob4
[
3
]
=
AFpgaProgD_iob8
[
1
]
;
assign
FpGpIo_iob4
[
2
]
=
AFpgaProgD_iob8
[
2
]
;
assign
FpGpIo_iob4
[
1
]
=
1'bz
;
assign
AFpgaProgD_iob8
[
0
]
=
FpGpIo_iob4
[
1
]
;
//#####################################
// WishBone Serial Interface
...
...
trunk/hdl/design/SystemFpga.v
View file @
58639a1a
...
...
@@ -474,40 +474,6 @@ assign IntSource_b8[7:2] = GenericOutputReg1[7:2];
assign
IntSource_b8
[
1
]
=
SpiIdle
;
assign
IntSource_b8
[
0
]
=
SpiWaitingData
;
/*VmeInterfaceWB i_VmeInterface(
.rst_i(Rst_rq),
.clk_i(Clk_k),
.adr_o(Adr_b22),
.dat_o(DatMasterO_b32),
.dat_i(DatMasterI_b32),
.we_o(We),
.stb_o(StbMaster),
.ack_i(AckMaster),
.cyc_o(Cyc),
.UseGa_i(UseGa_i),
.ManualAddress_i(ManualAddress_ib5),
.vme_ga(VmeGa_ib5n),
.vme_gap(VmeGaP_in),
.vme_as(VmeAs_in),
.vme_ds1(VmeDs_inb2[1]),
.vme_ds2(VmeDs_inb2[2]),
.vme_am(VmeAm_ib6),
.vme_wr(VmeWrite_in),
.vme_dtack(VmeDtAck_n),
.vme_lword(VmeLword_io),
.vme_addr(VmeA_iob31),
.vme_data(VmeD_iob32),
.VmeDOe_o(VmeDOe),
.VmeDDirFpgaToVme_o(VmeDDirVfcToVme_o),
.vme_iackinn(VmeIackIn_in),
.vme_iackn(VmeIack_in),
.vme_iack_outn(VmeIackOut_on),
.vme_irqn(VmeIrq_b7n),
.intlev_reg(InterrupLevel),
.IrqVector_i(IntVector_b8),
.assert_interrupt(AssertInterrupt),
.clear_int(IntAcknowledged)); */
VmeToWishBone
i_VmeInterface
(
.
Rst_irq
(
Rst_rq
)
,
.
Clk_ik
(
Clk_k
)
,
...
...
@@ -653,6 +619,11 @@ assign AFpgaProgProgram_o = 1'bz;
assign
SpiMiSo_b32
[
31
]
=
SpiMoSi
;
assign
SpiMiSo_b32
[
30
]
=
AFpgaProgD_iob8
[
0
]
;
assign
AFpgaProgD_iob8
[
3
]
=
SpiSS_nb32
[
30
]
;
assign
AFpgaProgD_iob8
[
2
]
=
SpiMoSi
;
assign
AFpgaProgD_iob8
[
1
]
=
SpiSClk_k
;
assign
SpiMiSo_b32
[
8
]
=
FlashSFpgaQ_i
;
//Think about removing it and placing it in a special place (CSR space)
assign
FlashSFpgaCs_on
=
SpiSS_nb32
[
8
]
;
//Think about removing it and placing it in a special place (CSR space)
assign
FlashSFpgaD_o
=
SpiMoSi
;
//Think about removing it and placing it in a special place (CSR space)
...
...
trunk/hdl/testbench/tb_VFC.v
View file @
58639a1a
...
...
@@ -72,7 +72,7 @@ wire GapSlot4_n = ^(5'd4);
wire
[
4
:
0
]
GaSlot4_nb5
=
~
(
5'd4
)
;
wire
VmeIackInSlot4_n
=
VmeIack_n
;
wire
VmeIackOutSlot4_n
;
wire
[
3
:
0
]
FpGpIo_b4
=
'
hz
;
wire
[
4
:
1
]
FpGpIo_b4
=
'
hz
;
reg
WaveformGeneratorOut
=
1'b0
;
...
...
@@ -81,7 +81,7 @@ always begin
WaveformGeneratorOut
=
~
WaveformGeneratorOut
;
end
assign
FpGpIo_b4
[
0
]
=
WaveformGeneratorOut
;
assign
FpGpIo_b4
[
1
]
=
FpGpIo_b4
[
2
]
;
VFCBoard
i_VFCBoard
(
.
VmeIrq_ozb7
(
VmeIrq_b7
)
,
...
...
trunk/software/mysim.py
View file @
58639a1a
...
...
@@ -17,13 +17,10 @@ WaitSimulation('1000')
print
"Release: "
,
hex
(
MyBoard
.
ReleaseID
.
Read
())
print
""
print
"Starting to check the SPI using the SPI feedback channell (3
1
)"
print
"Starting to check the SPI using the SPI feedback channell (3
0
)"
print
""
print
"Checking the SPI master with short accesses with all the CPol CPha combinations and MSB 1st"
print
""
print
"SPI access CPol=0 CPha=0 MSB1st 8bit 0xaa halfperiod=4 wait=12"
Result
=
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
0
,
8
,
0xaa
,
4
,
12
)
print
"SPI access CPol=0 CPha=0 MSB1st 32bit 0xaa halfperiod=4 wait=12"
Result
=
MyBoard
.
SpiAccess
(
30
,
0
,
0
,
0
,
31
,
0x111133aa
,
4
,
12
)
print
"Obtained value: "
,
hex
(
Result
)
WaitSimulation
(
10000
)
...
...
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