Commit 777894d8 authored by Andrea Boccardi's avatar Andrea Boccardi

...

parent f7146861
Release 12.3 ngdbuild M.70d (nt)
Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc
SFpga.ngd
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3
SFpga.ngc SFpga.ngd
Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ...
Gathering constraint information from source properties...
......@@ -49,10 +49,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 16
Total memory usage is 87012 kilobytes
Total memory usage is 155028 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 5 sec
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"...
......@@ -210,3 +210,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:01 2011
Fri Jan 28 15:08:32 2011
# NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 par M.70d (nt)
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Fri Jan 28 11:49:02 2011
PCBE13225:: Fri Jan 28 15:05:49 2011
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -26,7 +26,7 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1%
Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
......@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 2
Number used exclusively as route-thrus: 14
Number with same-slice register load: 9
Number used exclusively as route-thrus: 12
Number with same-slice register load: 7
Number with same-slice carry load: 5
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 20 secs
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal DdsRamSwpOvr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<0>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -154,29 +154,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 4748 unrouted; REAL time: 23 secs
Phase 1 : 4750 unrouted; REAL time: 11 secs
Phase 2 : 4243 unrouted; REAL time: 30 secs
Phase 2 : 4245 unrouted; REAL time: 14 secs
Phase 3 : 1611 unrouted; REAL time: 5 mins 41 secs
Phase 3 : 1604 unrouted; REAL time: 2 mins 34 secs
Phase 4 : 1611 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 52 secs
Phase 4 : 1604 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 39 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Total REAL time to Router completion: 5 mins 56 secs
Total CPU time to Router completion: 5 mins 54 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Total REAL time to Router completion: 2 mins 41 secs
Total CPU time to Router completion: 2 mins 40 secs
Partition Implementation Status
-------------------------------
......@@ -194,14 +194,14 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 203 | 0.325 | 1.693 |
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 204 | 0.325 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 6 | 0.009 | 1.690 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.189 | 1.692 |
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.190 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/Stb_oq | Local| | 17 | 0.000 | 2.404 |
| e/Stb_oq | Local| | 17 | 0.000 | 2.145 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -220,7 +220,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.649ns| 4.684ns| 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.404ns| 4.929ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.439ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 5.833ns| 2.500ns| 0| 0
......@@ -241,10 +241,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 49 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 5 mins 59 secs
Total CPU time to PAR completion: 5 mins 58 secs
Total REAL time to PAR completion: 2 mins 43 secs
Total CPU time to PAR completion: 2 mins 42 secs
Peak Memory Usage: 366 MB
Peak Memory Usage: 559 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
//! **************************************************************************
// Written by: Map M.70d on Fri Jan 28 11:48:58 2011
// Written by: Map M.70d on Fri Jan 28 15:05:46 2011
//! **************************************************************************
SCHEMATIC START;
......
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.649" best="4.684" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.439" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="6.152" best="2.181" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.464" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.404" best="4.929" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.439" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="6.152" best="2.181" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.464" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
Release 12.3 - xst M.70d (nt)
Release 12.3 - xst M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: SFpga.prj
......@@ -1032,7 +1032,7 @@ Delay: 2.365ns (Levels of Logic = 25)
=========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 6.551ns (frequency: 152.654MHz)
Total number of paths / destination ports: 26774 / 1542
Total number of paths / destination ports: 26773 / 1542
-------------------------------------------------------------------------
Delay: 6.551ns (Levels of Logic = 10)
Source: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF)
......@@ -1121,7 +1121,7 @@ Offset: 12.206ns (Levels of Logic = 10)
LUT6:I1->O 6 0.254 0.973 i_Core/i_VmeInterface/GapError1 (i_Core/i_VmeInterface/GapError)
LUT4:I1->O 1 0.235 1.035 i_Core/i_VmeInterface/Mmux_BoardBaseAddr_b521 (i_Core/i_VmeInterface/BoardBaseAddr_b5<1>)
LUT6:I0->O 1 0.254 0.808 i_Core/i_VmeInterface/ValidRWBA_a81 (i_Core/i_VmeInterface/ValidRWBA_a8)
LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N294)
LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N296)
LUT6:I0->O 3 0.254 0.879 i_Core/i_VmeInterface/ValidRWBA_a83 (i_Core/i_VmeInterface/ValidRWBA_a)
LUT4:I1->O 1 0.235 0.580 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1_SW0 (N42)
LUT6:I5->O 8 0.254 1.031 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1 (N3)
......@@ -1254,12 +1254,12 @@ i_Core/i_VmeInterface/Stb_oq| 2.049| | | |
=========================================================================
Total REAL time to Xst completion: 28.00 secs
Total CPU time to Xst completion: 27.13 secs
Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 17.41 secs
-->
Total memory usage is 155300 kilobytes
Total memory usage is 280792 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 129 ( 0 filtered)
......
Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:02 2011
Fri Jan 28 15:08:33 2011
All signals are completely routed.
......
......@@ -15,17 +15,17 @@
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
</tr>
<tr>
<td>XILINX</td>
......@@ -35,13 +35,6 @@
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
......@@ -515,31 +508,31 @@
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
</tr>
</TABLE>
</BODY> </HTML>
\ No newline at end of file
Release 12.3 Map M.70d (nt)
Release 12.3 Map M.70d (nt64)
Xilinx Map Application Log File for Design 'SFpga'
Design Information
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Jan 28 11:48:01 2011
Mapped Date : Fri Jan 28 15:05:14 2011
Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
......@@ -87,58 +87,58 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 25 secs
Total CPU time at the beginning of Placer: 24 secs
Total REAL time at the beginning of Placer: 12 secs
Total CPU time at the beginning of Placer: 11 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:cc31257e) REAL time: 32 secs
Phase 1.1 Initial Placement Analysis (Checksum:cc31257e) REAL time: 16 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:cc31257e) REAL time: 33 secs
Phase 2.7 Design Feasibility Check (Checksum:cc31257e) REAL time: 17 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:cc31257e) REAL time: 33 secs
Phase 3.31 Local Placement Optimization (Checksum:cc31257e) REAL time: 17 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:aaca966e) REAL time: 40 secs
(Checksum:aaca966e) REAL time: 21 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:aaca966e) REAL time: 40 secs
Phase 5.36 Local Placement Optimization (Checksum:aaca966e) REAL time: 21 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:aaca966e) REAL time: 40 secs
Phase 6.30 Global Clock Region Assignment (Checksum:aaca966e) REAL time: 21 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:98519d88) REAL time: 41 secs
Phase 7.3 Local Placement Optimization (Checksum:98519d88) REAL time: 22 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:aaea37e3) REAL time: 41 secs
Phase 8.5 Local Placement Optimization (Checksum:aaea37e3) REAL time: 22 secs
Phase 9.8 Global Placement
....
....................
Phase 9.8 Global Placement (Checksum:f9eafb45) REAL time: 44 secs
.........
..........................................
Phase 9.8 Global Placement (Checksum:de2814d1) REAL time: 24 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:f9eafb45) REAL time: 44 secs
Phase 10.5 Local Placement Optimization (Checksum:de2814d1) REAL time: 24 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:af7d4423) REAL time: 45 secs
Phase 11.18 Placement Optimization (Checksum:b777ab7) REAL time: 25 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:af7d4423) REAL time: 45 secs
Phase 12.5 Local Placement Optimization (Checksum:b777ab7) REAL time: 25 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:1a6c36bd) REAL time: 46 secs
Phase 13.34 Placement Validation (Checksum:f00dac81) REAL time: 25 secs
Total REAL time to Placer completion: 55 secs
Total CPU time to Placer completion: 55 secs
Total REAL time to Placer completion: 30 secs
Total CPU time to Placer completion: 29 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
......@@ -253,7 +253,7 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1%
Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
......@@ -269,17 +269,17 @@ Slice Logic Utilization:
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 2
Number used exclusively as route-thrus: 14
Number with same-slice register load: 9
Number used exclusively as route-thrus: 12
Number with same-slice register load: 7
Number with same-slice carry load: 5
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of unique control sets: 27
Number of slice register sites lost
to control set restrictions: 71 out of 184,304 1%
......@@ -325,9 +325,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 396 MB
Total REAL time to MAP completion: 58 secs
Total CPU time to MAP completion: 58 secs
Peak Memory Usage: 618 MB
Total REAL time to MAP completion: 32 secs
Total CPU time to MAP completion: 31 secs
Mapping completed.
See MAP report file "SFpga_map.mrp" for details.
Release 12.3 Map M.70d (nt)
Release 12.3 Map M.70d (nt64)
Xilinx Mapping Report File for Design 'SFpga'
Design Information
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Jan 28 11:48:01 2011
Mapped Date : Fri Jan 28 15:05:14 2011
Design Summary
--------------
......@@ -22,7 +22,7 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1%
Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
......@@ -38,17 +38,17 @@ Slice Logic Utilization:
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 2
Number used exclusively as route-thrus: 14
Number with same-slice register load: 9
Number used exclusively as route-thrus: 12
Number with same-slice register load: 7
Number with same-slice carry load: 5
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of unique control sets: 27
Number of slice register sites lost
to control set restrictions: 71 out of 184,304 1%
......@@ -94,9 +94,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 396 MB
Total REAL time to MAP completion: 58 secs
Total CPU time to MAP completion: 58 secs
Peak Memory Usage: 618 MB
Total REAL time to MAP completion: 32 secs
Total CPU time to MAP completion: 31 secs
Table of Contents
-----------------
......
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Fri Jan 28 11:49:00 2011">
<application stringID="Map" timeStamp="Fri Jan 28 15:05:47 2011">
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<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
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<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -120,9 +116,9 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="405884"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="58 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="58 secs "/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="632572"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="32 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="31 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="765">
......@@ -131,7 +127,7 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="851">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="849">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="616"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="124"/>
......@@ -148,21 +144,21 @@
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="4"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="392">
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="386">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="51"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="337"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="331"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1060">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="372"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="209"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="479"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1046">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="356"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="197"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="493"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
......
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